CN105656599B - A kind of data transfer clock method for continuously adjusting and device - Google Patents
A kind of data transfer clock method for continuously adjusting and device Download PDFInfo
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Abstract
The embodiment of the invention discloses a kind of data transfer clock method for continuously adjusting and devices, which comprises receives the data that prime module is exported with given pace and stores in data buffer unit；According to the current buffer status of monitoring data buffer cell to determine error signal；Clock frequency so that it is determined that new is carried out after second-order filter etc. is handled to error signal；The data in data buffer unit are read according to new clock frequency and carry out high speed parallel-serial conversion, serial data signal and clock signal after output conversion.Data clock rate is continuously adjusted to realize, and finally converge to actual message transmission rate up, the stability of clock frequency, reduction shake, can also increase the reliability that receiving end receives data, improve the rate of data transmit-receive when high-speed transfer not only can be improved.
Description
Technical field
The present invention relates to field of data transmission, and in particular to digital information transmission technical more particularly to a kind of transmission of data
Clock method for continuously adjusting and device.
Background technique
In communication or data processing system, equipment room is frequently necessary to carry out the interaction of high-speed data, and for some special
With equipment, due to lacking the interfaces based on complex protocol such as network interface, the data interaction of equipment room generallys use relatively simple
Electric level interface form transmitted, such as in the prior art in order to meet it is such application and formed a series of electric level interface marks
It is quasi-: RS232, LVDS (Low Voltage Differential Signaling, i.e. technology of Low Voltage Differential Signaling interface), ECL
Interface standards such as (Emitter Coupled Logic, i.e. emitter-coupled logic (ECL)).
Wherein RS232 interface standard uses asynchronous transfer mode, equipment room no data clock signal, just with appointing
Rate carry out data reception, transmission rate is usually tens Kbps, which is generally only applicable to low rate
Data transmission.And in LVDS and ECL interface standard, clock signal is transmitted with data in equipment room, wherein LVDS interface mark
Standard uses parallel transmission, and in addition to clock signal, equipment room usually also needs more data lines, and single-pass data transmission rate can reach
To 200Mbps or more, therefore, it can be used for the data transmission of higher rate；And ECL interface standard then uses differential level, only
It needs clock signal all the way and data-signal, transmission rate can be adapted for high speed data transfer up to 1Gbps or more all the way.
But either LVDS, ECL or other types of high speed interface, for most of applications, transmission
Signal includes two kinds: continuous clock signal and continuous data-signal.Receiving device is believed according to the continuous clock received
Number the data-signal received is sampled, to obtain valid data.Illustrate below by way of a specific embodiment
Equipment room carries out the process of real time high-speed data interaction in the prior art, it is assumed that and equipment A is transmitting terminal, and equipment B is receiving end, by
Then real-time, interactive, therefore, equipment A need to receive the data that prime processing equipment is sent, while carrying out data processing, and will
Data that treated are sent to equipment B in real time.And actually received data rate and preset Theoretical Rate have deviation to equipment A
(belonging to normal range (NR), such as the Doppler frequency shift in the temperature drift of crystal oscillator, wireless communication influences), it is assumed that the expection rate of equipment A
For Rbps, and the rate error as caused by all kinds of factors is △ (this error is as the time is also in dynamic change), then equipment A
Needing the rate transmitted to equipment B is (R+ △) bps.If equipment A sends data to equipment B with the rate of Rbps, pass through
After certain time, it will the phenomenon that data buffer unit reads empty (△ is positive) or overflows (△ is negative) occur.In response to this problem,
It is mainly solved at present using steps adjusting is carried out to clock frequency, i.e., first presets a regulated quantity △ ', when discovery data
The when marquis that buffer cell will overflow, by clock frequency increase △ ', when find data buffer unit will read sky when marquis by when
Clock frequency reduces △ ', and the spilling up and down of buffer area is avoided with this.But clock frequency is adjusted using this method, by
It is jump in the variation of clock frequency, therefore, will cause the low problem of data receiver poor reliability, message transmission rate.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of data transfer clock method for continuously adjusting and device, to improve
The transmission rate of data and receiving end receive the reliability of data.
The embodiment of the present invention uses following technical scheme:
In a first aspect, the embodiment of the invention provides a kind of data transfer clock method for continuously adjusting, comprising:
It receives the data that prime module is exported with given pace and is stored in data buffer unit；
The current buffer status of the data buffer unit is monitored, if the current buffer status of the data buffer unit is full
The preset cache threshold of foot, then determine error signal according to the current buffer status of the data buffer unit；
Second-order filter is carried out to the error signal, generates filtered clock compensation signal；
New clock frequency is determined according to the clock compensation signal and preset original frequency word；
The data in the data buffer unit are read according to the new clock frequency and carry out high speed parallel-serial conversion, it is defeated
Serial data signal and clock signal after converting out.
Second aspect, the embodiment of the invention also provides a kind of data transfer clock continuous regulating mechanisms, comprising:
Data buffer unit, for receiving data that prime module is exported with given pace and being stored；
Error characteristics converting unit, for monitoring the current buffer status of the data buffer unit, if the data are slow
It rushes the current buffer status of unit and meets preset cache threshold, then it is true according to the current buffer status of the data buffer unit
Determine error signal；
Second-order filter unit generates filtered clock compensation signal for carrying out second-order filter to the error signal；
Numerical frequency comprehensive unit, when for determining new according to the clock compensation signal and preset original frequency word
Clock frequency；
High speed parallel serial conversion unit, for reading the data in the data buffer unit according to the new clock frequency
And high speed parallel-serial conversion is carried out, serial data signal and clock signal after output conversion.
The advantageous effects for the technical solution that the embodiment of the present invention proposes are:
The technical solution of the embodiment of the present invention passes through the data that reception prime module is exported with given pace and delays in data
Rush in unit and store, according to the current buffer status of monitoring data buffer cell to determine error signal, and to error signal into
So that it is determined that new clock frequency, reads the number in data buffer unit according to new clock frequency after the processing such as row second-order filter
According to and carry out high speed parallel-serial conversion, the serial data signal and clock signal after output conversion, to realize to data clock frequency
Rate is continuously adjusted, and finally converges to actual message transmission rate up, clock when high-speed transfer not only can be improved
The stability of frequency reduces shake, can also increase the reliability that receiving end receives data, improve the rate of data transmit-receive.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, institute in being described below to the embodiment of the present invention
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the invention
Example, for those of ordinary skill in the art, without creative efforts, can also implement according to the present invention
The content of example and these attached drawings obtain other attached drawings.
Fig. 1 is the flow diagram of data transfer clock method for continuously adjusting described in the specific embodiment of the invention one；
Fig. 2 is the structural block diagram of data transfer clock continuous regulating mechanism described in the specific embodiment of the invention two.
Specific embodiment
To keep the technical problems solved, the adopted technical scheme and the technical effect achieved by the invention clearer, below
It will the technical scheme of the embodiment of the invention will be described in further detail in conjunction with attached drawing, it is clear that described embodiment is only
It is a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those skilled in the art exist
Every other embodiment obtained under the premise of creative work is not made, shall fall within the protection scope of the present invention.
To further illustrate the technical scheme of the present invention below with reference to the accompanying drawings and specific embodiments.
Embodiment one
Fig. 1 is the flow diagram of data transfer clock method for continuously adjusting described in the specific embodiment of the invention one, such as
Shown in Fig. 1, the method may include following steps:
Step S101 receives the data that prime module is exported with given pace and stores in data buffer unit；
Step S102 monitors the current buffer status of the data buffer unit, if the data buffer unit is current
Buffer status meets preset cache threshold, then determines error signal according to the current buffer status of the data buffer unit；
Step S103 carries out second-order filter to the error signal, generates filtered clock compensation signal；
Step S104 determines new clock frequency according to the clock compensation signal and preset original frequency word；
Step S105 reads the data in the data buffer unit according to the new clock frequency and carries out high speed simultaneously
String conversion, serial data signal and clock signal after output conversion.
Technical solution of the present invention is primarily adapted for use in equipment room and needs the case where carrying out high-speed serial data transmission, this implementation
The executing subject of example can be data transfer clock continuous regulating mechanism, can be deployed in the equipment end for needing to send data,
Can also individually dispose and by network or other modes respectively with the equipment end for needing to send data and need to receive data
Equipment end connection, continuously adjusts data clock rate to realize, the stabilization of clock frequency when improving high-speed transfer
Property, reduce shake, and increase receiving end receive data reliability, improve the rate of data transmit-receive.
It is illustrated so that data transfer clock continuous regulating mechanism is individually disposed as an example below, specifically, for example, when needing
When the equipment A for sending data will send in real time data to the equipment B for needing to receive data, equipment A can be through this embodiment
The data transfer clock continuous regulating mechanism of offer is attached with equipment B, so that data transfer clock continuous regulating mechanism can
The data of equipment A are transmitted to receive prime module with rate R, and are stored in data buffer unit, meanwhile, to data buffering
The current buffer status of unit is monitored, and judges whether the current buffer status of data buffer unit meets preset caching threshold
Value, if satisfied, then determining error signal according to the current buffer status of data buffer unit.In the present embodiment, data buffering
The current buffer status of unit may include the data volume of data buffer unit current cache, if data buffer unit is currently delayed
The data volume deposited is greater than the half of the total capacity of data buffer unit, then it represents that the current buffer status of data buffer unit meets
Preset cache threshold, at this point it is possible to determine error signal v according to the following formula:
Wherein, v is error signal, and e is natural constant, and L is the total capacity of data buffer unit, and l is data buffer unit
The data volume of current cache, R are the rate of prime module output data, and σ is response time regulatory factor, and value is a positive number,
It can be set according to the variation degree of the rate R of prime module output data.
Preferably, in the present embodiment, response time regulatory factor σ not less than 1 and is not more than 128.For example, if prime
The rate R of module output data change with time it is larger, then σ can use a larger value, to track this variation；If prime mould
The rate R of block output data change with time it is smaller, then σ can use a smaller value, to obtain more stable tracking.
Further, in the present embodiment, second order filter can be carried out to above-mentioned error signal v using second-order filter loop
Wave, to generate filtered clock compensation signal delta f(n), wherein Δ f(n)=k1*v(n)+vreg(n), vreg(n)=vreg(n-1)+
k2*vlast, vreg(n)For the register in second-order filter loop, initial value 0, vlastIt is the last error signal generated, k1、
k2For loop coefficient, it is preferable that loop coefficient k1、k2For the number not less than 0 and no more than 1.N indicates subscript, is being greater than 0 just
Integer.For example, the error signal after n-th progress second-order filter can be expressed as v(n), similarly, n-th generates filtered
Clock compensation signal can be expressed as Δ f(n)。
Further, data transfer clock continuous regulating mechanism can also determine respective tones according to preset original frequency word
The initial clock frequency f of rate(0), and the filtered clock compensation signal delta f for combining n-th to generate(n), so that it is determined that n-th
The new clock frequency f generated(n), the present embodiment obtains f by add operation(n)=f(0)+Δf(n), then data transfer clock connects
Continuous regulating device can according to new clock frequency read data buffer unit in data and carry out high speed parallel-serial conversion, with to
Serial data signal and clock signal after equipment B output conversion.Data clock rate is continuously adjusted to realize, and
Finally converge to actual message transmission rate up, the stability of clock frequency, reduction when high-speed transfer not only can be improved
Shake can also increase the reliability that receiving end receives data, improve the rate of data transmit-receive.
Embodiment two
Fig. 2 is the structural block diagram of data transfer clock continuous regulating mechanism described in the specific embodiment of the invention two, such as Fig. 2
Shown, data transfer clock continuous regulating mechanism described in the present embodiment may include:
Data buffer unit 201, for receiving data that prime module is exported with given pace and being stored；
Error characteristics converting unit 202, for monitoring the current buffer status of the data buffer unit, if the data
The current buffer status of buffer cell meets preset cache threshold, then the buffer status current according to the data buffer unit
Determine error signal；
Second-order filter unit 203 generates filtered clock compensation letter for carrying out second-order filter to the error signal
Number；
Numerical frequency comprehensive unit 204 is new for being determined according to the clock compensation signal and preset original frequency word
Clock frequency；
High speed parallel serial conversion unit 205, for being read in the data buffer unit according to the new clock frequency
Data simultaneously carry out high speed parallel-serial conversion, serial data signal and clock signal after output conversion.
Further, the error characteristics converting unit 202 is specifically used for:
The current buffer status of the data buffer unit is monitored, the current buffer status of the data buffer unit includes
The data volume of the data buffer unit current cache；
If the data volume of the data buffer unit current cache is greater than the half of the total capacity of the data buffer unit
When, then the error signal is determined according to the following formula:
Wherein, v is the error signal, and e is natural constant, and L is the total capacity of the data buffer unit, and l is described
The data volume of data buffer unit current cache, R be the prime module output data rate, σ be the response time adjust because
Son, value are a positive number, are set according to the variation degree of the rate R of prime module output data.
Further, the response time regulatory factor σ not less than 1 and is not more than 128.
Further, the second-order filter unit 203 is specifically used for:
Generate filtered clock compensation signal delta f(n)；
Wherein, Δ f(n)=k1*v(n)+vreg(n), vreg(n)=vreg(n-1)+k2*vlast, vreg(n)For in second-order filter loop
Register, initial value 0, vlastIt is the last error signal generated, k1、k2For loop coefficient, n indicates subscript, is greater than 0
Positive integer.
Further, the loop coefficient k1、k2Not less than 0 and it is not more than 1.
Further, the numerical frequency comprehensive unit 204 is specifically used for:
The initial clock frequency of corresponding frequencies is determined according to the preset original frequency word；
The initial clock frequency is added with the clock compensation signal, obtains new clock frequency.
Data transfer clock continuous regulating mechanism provided in this embodiment can execute the number of the offer of the embodiment of the present invention one
According to the technical solution of transmission clock method for continuously adjusting, it is similar that the realization principle and technical effect are similar, and details are not described herein again.
Above embodiments provide technical solution in all or part of the content can be realized by software programming, software
Program store in a readable storage medium, storage medium for example: hard disk, CD or floppy disk in computer.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (8)
1. a kind of data transfer clock method for continuously adjusting characterized by comprising
It receives the data that prime module is exported with given pace and is stored in data buffer unit；
Monitor the current buffer status of the data buffer unit, if the current buffer status of the data buffer unit meet it is pre-
If cache threshold, then error signal is determined according to the current buffer status of the data buffer unit；
Second-order filter is carried out to the error signal, generates filtered clock compensation signal；
New clock frequency is determined according to the clock compensation signal and preset original frequency word；
The data in the data buffer unit are read according to the new clock frequency and carry out high speed parallel-serial conversion, and output turns
Serial data signal and clock signal after changing,
Wherein determine that the operation of error signal specifically includes according to the current buffer status of the data buffer unit:
The current buffer status of the data buffer unit is monitored, the current buffer status of the data buffer unit includes described
The data volume of data buffer unit current cache；
If the data volume of the data buffer unit current cache is greater than the half of the total capacity of the data buffer unit,
The error signal is determined according to the following formula:
Wherein, v is the error signal, and e is natural constant, and L is the total capacity of the data buffer unit, and l is the data
The data volume of buffer cell current cache, R are the rate of the prime module output data, and σ is response time regulatory factor,
Value is a positive number, is set according to the variation degree of the rate R of prime module output data.
2. the method as described in claim 1, which is characterized in that the response time regulatory factor σ is not less than 1 and is not more than
128。
3. the method as described in claim 1, which is characterized in that it is described that second-order filter is carried out to the error signal, generate filter
The operation of clock compensation signal after wave specifically includes:
Second-order filter is carried out to the error signal using second-order filter loop；
Generate filtered clock compensation signal delta f(n)；
Wherein, Δ f(n)=k1*v(n)+vreg(n), vreg(n)=vreg(n-1)+k2*vlast, vreg(n)For the deposit in second-order filter loop
Device, initial value 0, v(n)It is that n-th carries out the error signal after the second-order filter, vlastIt is the last error letter generated
Number, k1、k2For loop coefficient, n indicates subscript, is greater than 0 positive integer.
4. method as claimed in any one of claims 1 to 3, which is characterized in that described according to the clock compensation signal and pre-
If original frequency word determine that the operation of new clock frequency specifically includes:
The initial clock frequency of corresponding frequencies is determined according to the preset original frequency word；
The initial clock frequency is added with the clock compensation signal, obtains new clock frequency.
5. a kind of data transfer clock continuous regulating mechanism characterized by comprising
Data buffer unit, for receiving data that prime module is exported with given pace and being stored；
Error characteristics converting unit, for monitoring the current buffer status of the data buffer unit, if the data buffering list
The current buffer status of member meets preset cache threshold, then is determined and missed according to the current buffer status of the data buffer unit
Difference signal；
Second-order filter unit generates filtered clock compensation signal for carrying out second-order filter to the error signal；
Numerical frequency comprehensive unit, for determining new clock frequency according to the clock compensation signal and preset original frequency word
Rate；
High speed parallel serial conversion unit is gone forward side by side for reading the data in the data buffer unit according to the new clock frequency
Row high speed parallel-serial conversion, serial data signal and clock signal after output conversion,
Wherein the error characteristics converting unit is specifically used for:
The current buffer status of the data buffer unit is monitored, the current buffer status of the data buffer unit includes described
The data volume of data buffer unit current cache；
If the data volume of the data buffer unit current cache is greater than the half of the total capacity of the data buffer unit,
The error signal is determined according to the following formula:
Wherein, v is the error signal, and e is natural constant, and L is the total capacity of the data buffer unit, and l is the data
The data volume of buffer cell current cache, R are the rate of the prime module output data, and σ is response time regulatory factor,
Value is a positive number, is set according to the variation degree of the rate R of prime module output data.
6. device as claimed in claim 5, which is characterized in that the response time regulatory factor σ is not less than 1 and is not more than
128。
7. device as claimed in claim 5, which is characterized in that the second-order filter unit is specifically used for:
Generate filtered clock compensation signal delta f(n)；
Wherein, Δ f(n)=k1*v(n)+vreg(n), vreg(n)=vreg(n-1)+k2*vlast, vreg(n)For posting in second-order filter loop
Storage, initial value 0, v(n)It is that the second-order filter unit n-th carries out the error signal after second-order filter, vlastIt is upper one
The error signal of secondary generation, k1、k2For loop coefficient, n indicates subscript, is greater than 0 positive integer.
8. such as the described in any item devices of claim 5~7, which is characterized in that the numerical frequency comprehensive unit is specifically used for:
The initial clock frequency of corresponding frequencies is determined according to the preset original frequency word；
The initial clock frequency is added with the clock compensation signal, obtains new clock frequency.
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| CN101964656A (en) * | 2010-09-01 | 2011-02-02 | 硅谷数模半导体（北京）有限公司 | Phase locked loop |
| CN102243880A (en) * | 2011-03-16 | 2011-11-16 | 中国科学院上海光学精密机械研究所 | Variable parameter self-adaptive PRML data receiver and data processing method thereof |
| CN103236896A (en) * | 2013-04-07 | 2013-08-07 | 北京全路通信信号研究设计院有限公司 | Clock adjusting method and clock adjusting system for vehicular control equipment |
| CN103490841A (en) * | 2013-09-25 | 2014-01-01 | 科大智能（合肥）科技有限公司 | Clock recovery method based on distributed frame header in multi-path E1 multiplexing system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7882384B2 (en) * | 2006-08-31 | 2011-02-01 | National Semiconductor Corporation | Setting and minimizing a derived clock frequency based on an input time interval |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101964656A (en) * | 2010-09-01 | 2011-02-02 | 硅谷数模半导体（北京）有限公司 | Phase locked loop |
| CN102243880A (en) * | 2011-03-16 | 2011-11-16 | 中国科学院上海光学精密机械研究所 | Variable parameter self-adaptive PRML data receiver and data processing method thereof |
| CN103236896A (en) * | 2013-04-07 | 2013-08-07 | 北京全路通信信号研究设计院有限公司 | Clock adjusting method and clock adjusting system for vehicular control equipment |
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