CN105656592B - EtherCAT communication systems main website and communication means - Google Patents
EtherCAT communication systems main website and communication means Download PDFInfo
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- CN105656592B CN105656592B CN201511031363.2A CN201511031363A CN105656592B CN 105656592 B CN105656592 B CN 105656592B CN 201511031363 A CN201511031363 A CN 201511031363A CN 105656592 B CN105656592 B CN 105656592B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40019—Details regarding a bus master
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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Abstract
The present invention provides a kind of EtherCAT communication systems main website and communication means, the main website includes main processing block, FPGA and ethernet transceiver；The main processing block includes PDO interactive units, and the FPGA includes PDO Transmit-Receive Units, distribution clock unit and physical layer control unit；Wherein：The distribution clock unit, for realizing that motion controller clock is synchronous with the clock of servo slave station according to the clock signal of FPGA；The data transceiving unit sends PDO interactive units to for the slave station interaction data from PDO interactive units to be encapsulated as EtherCAT data frames and the EtherCAT data frame solutions from physical layer control unit are honored as a queen according to communication cycle；The physical layer control unit, for realizing the full duplex transmitting-receiving and the transmission of distribution clock message of EtherCAT data frames.The present invention is synchronous with the clock of servo slave station by the hardware realization motion controller of FPGA, and accordingly the transmitting-receiving of property performance period data, it can be achieved that accurate master-salve station synchronous communication.
Description
Technical field
The present invention relates to the communications fields EtherCAT, more specifically to a kind of EtherCAT communication systems main website and
Communication means.
Background technology
EtherCAT (Ethernet auto-control technology, abbreviation ECAT) is an open architecture based on Ethernet
Field bus system, with its exclusive " on the fly " communication mode, when communications data frame being made to pass through each website, in number
In the case of not stopped according to frame, the data of respective site are handled, to significantly reduce data processing time, shorten communication
Period.In addition the synchronization mechanism of its distribution clock (Distribute Clock, DC) so that EtherCAT is widely used in height
Fast, high-precision motion control field.
EtherCAT slave stations are carried out by EtherCAT from station control (ESC).And main website does not have dedicated ASIC
(Application Specific Integrated Circuits, application-specific integrated circuit), EtherCAT main websites are usually by transporting
Pure software of the row in operating system (Windows, Linux, VxWorks etc.), and the driving of combined standard Ethernet card is realized.
In practical applications, EtherCAT main websites often operate in motion controller one end, and motion controller will produce week
The data of phase planning, and can these data be sent to each servo slave station in real time by EtherCAT main websites, this is to influence to be somebody's turn to do
The key factor of the control performance of control system.Therefore the real-time of EtherCAT main websites and the synchronism of main website and slave station
Can, it is vital for high speed, high-precision motion control.
To realize the real-time synchronization of EtherCAT main websites and servo slave station, the cycle interruption clock of motion controller must be with
The distribution clock (DC) of all servo slave stations is synchronous, and otherwise (such as interpolation is transported for the multi-axial Simultaneous movement of motion controller period planning
It is dynamic) data cannot be guaranteed to be executed synchronously in server-side.So, control accuracy is not just known where to begin.
Traditional EtherCAT main websites are the pure software frameworks based on operating system OS (Operating System).Due to
The scheduling of operating system multitask is extremely complex and is non real-time, thus want to execute on an operating system 1ms with
Under EtherCAT real-time tasks, it is necessary to operating system supplier depth cooperation (such as Windows) or to operating system (such as
Linux etc.) stamp real-time patch.Such as it is logical for EtherCAT by the timer (Timer) that real-time patch RT Patch are generated
Letter provides master clock (Clock M), as shown in Figure 1, EtherCAT main websites directly set this master clock to reference clock
Slave station SL0 (Slave0) is used as its distribution clock, and servo slave station thereafter is again with reference to progress with the distribution clock of reference clock
It is synchronous.Since the send and receive packets behavior of EtherCAT main websites passes through the Ethernet Adaptation Unit (Ethernet under operating system
Adapter there are delay variations after driver), this will necessarily give the distribution clock of entire EtherCAT network direct
A shake is introduced, to destroy the net synchronization capability between servo slave station, therefore traditional EtherCAT main websites scheme can not ensure
The cycle interruption clock of motion controller reaches synchronous with the distribution clock of servo slave station.
However, being either that operating system beats real-time patch with operating system supplier depth cooperation or still, all need
By changing the scheduling of operating system underlying task, to improve the real-time of EtherCAT master tasks.But this will certainly be to behaviour
The stability for making system brings prodigious challenge and risk.And even by such Real-Time Improvement, it is desirable to obtain 500us with
Under real-time performance, and the CPU for needing performance superpower could realize, this certainly will cause to impact to the cost of system again.
Invention content
The technical problem to be solved in the present invention is, real-time performance is poor in being communicated for above-mentioned EtherCAT, cost compared with
High problem provides a kind of EtherCAT communication systems main website and communication means.
The technical solution that the present invention solves above-mentioned technical problem is to provide a kind of EtherCAT communication systems main website, including
Main processing block, FPGA and ethernet transceiver, and reference clock slave station and servo are connected by the ethernet transceiver
Slave station；The main processing block includes PDO interactive units, and the FPGA includes PDO Transmit-Receive Units, distribution clock unit and object
Manage layer control unit；Wherein：The distribution clock unit generates distribution clock for the clock signal period according to FPGA
Message, to realize that motion controller clock is synchronous with the clock of servo slave station；The PDO Transmit-Receive Units, for according to distribution
Slave station interaction data from PDO interactive units is encapsulated as EtherCAT data frames and will come from by the communication cycle of clock unit
The EtherCAT data frame solutions of physical layer control unit, which are honored as a queen, sends PDO interactive units to；The physical layer control unit, is used for
Control full duplex transmitting-receiving and the transmission of distribution clock message that ethernet transceiver realizes EtherCAT data frames.
In EtherCAT communication systems of the present invention main website, the distribution clock unit includes that delay setting is single
Member, clock transmission unit and startup control unit, wherein：The delay setting unit, for calculating main website to reference clock
Simultaneously result of calculation is arranged to reference clock slave station for the transmission delay and time offset of slave station；The clock transmission unit, is used for
The clock of FPGA is sent to each servo slave station by timing；The startup control unit, for main website and servo slave station when
After clock synchronizes, calculate each servo slave station synchronizing signal start time and main website the interrupt start time, the servo from
The synchronizing signal startup time stood is aligned with the interrupt start time of main website in phase.
In EtherCAT communication systems of the present invention main website, the main processing block of the main website includes document analysis
Unit, station scans unit, state machine administrative unit, dispensing unit and mailbox communication unit, the FPGA include SDO transmitting-receivings
Unit, the SDO Transmit-Receive Units are used to realize document analysis unit, station scans unit, state by physical layer control unit
The data interaction of machine administrative unit, dispensing unit and mailbox communication unit and each servo slave station.
In EtherCAT communication systems of the present invention main website, the main website includes two ethernet transceivers, and
One of ethernet transceiver is for carrying out transmitting-receiving, another ethernet transceiver of data message for realizing main website annular
Redundancy, the physical layer control unit include Port Management unit, the Port Management unit for realizing port connection state and
Ring redundancy processing.
In EtherCAT communication systems of the present invention main website, the physical layer control unit includes packet filtering list
Member, for filtering non-EtherCAT messages.
The present invention also provides a kind of EtherCAT communication systems master station communication method, the main website include main processing block,
FPGA and ethernet transceiver, and reference clock slave station and servo slave station are connected by the ethernet transceiver；The side
Method includes the following steps：
(a) FPGA according to the clock signal period of the FPGA is sent by ethernet transceiver to servo slave station
Distribution clock message, to realize that motion controller clock is synchronous with the clock of servo slave station；
(b) PDO from main processing block is encapsulated as EtherCAT numbers by the FPGA according to the communication cycle of the FPGA
According to frame and the EtherCAT data frame solutions from physical layer control unit are honored as a queen send main processing block to；
(c) the FPGA controls ethernet transceiver realizes the full duplex transmitting-receiving of EtherCAT data frames.
In EtherCAT communication systems master station communication method of the present invention, the step (a) includes：
(a1) FPGA calculates main website to the transmission delay and time offset of reference clock slave station and sets result of calculation
Set reference clock slave station；
(a2) clock of FPGA is sent to each servo slave station by the FPGA timings；
(a3) FPGA calculates the synchronizing signal of each servo slave station after main website is synchronous with the clock of servo slave station
Start the interrupt start time of time and main website, when the synchronizing signal of the servo slave station starts the interrupt start of time and main website
Between be aligned in phase.
In EtherCAT communication systems master station communication method of the present invention, the method further includes：
The FPGA realizes the transmitting-receiving of the SDO between main website and slave station by ethernet transceiver；
The main processing block describes document analysis according to the FPGA slave station equipments received and goes out and the relevant slave station letter of configuration
Breath；
The main processing block is by FPGA to all clock reference slave stations and the servo that are connected in EtherCAT network
Slave station is scanned, and obtains the device descriptive information of online slave station number and each slave station；
The main processing block completes the application layer state handover management of each slave station by FPGA；
The main processing block carries out relevant configuration by FPGA to slave station；
The main processing block realizes mailbox communication by FPGA and servo slave station.
In EtherCAT communication systems master station communication method of the present invention, the main website includes that two Ethernets are received
Send out device, and one of ethernet transceiver for carry out transmitting-receiving, another ethernet transceiver of data message for realizing
Main website ring redundancy, the method includes：The FPGA carries out port connection state, ring redundancy processing.
In EtherCAT communication systems master station communication method of the present invention, the method includes：The FPGA mistakes
Filter non-EtherCAT messages.
EtherCAT communication systems of the present invention main website and communication means pass through the hardware realization motion control of FPGA
Device is synchronous with the clock of servo slave station, and the transmitting-receiving of property performance period data accordingly, increases without the kernel sky in operating system
Module need not also increase real-time patch, you can realize accurate master-salve station synchronous communication.
Description of the drawings
Fig. 1 is the schematic diagram of EtherCAT communications system embodiments of the present invention.
Fig. 2 is the module diagram of EtherCAT communication systems in Fig. 1.
Fig. 3 is the schematic diagram that EtherCAT communication systems clock synchronizes in Fig. 1.
Specific implementation mode
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
As shown in Figs. 1-2, it is the schematic diagram of EtherCAT communication systems of the present invention main website embodiment, can replaces existing
Main website in EtherCAT communication systems, to carry out servo from stand control.The EtherCAT communication systems main website includes main process task
Module 10, FPGA (programmable logic device) 20 and ethernet transceiver (Ethernet PHY) 30, and received by Ethernet
It sends out device 30 and connects reference clock slave station and servo slave station.Above-mentioned main processing block 10, which specifically can be used ARM chips and run, behaviour
Make system (may include operating system user's space and operating system nucleus space), which passes through Peripheral Interface
(Peripheral Interface) is connect with FPGA 20.
In the present embodiment, main processing block 10 realizes application layer ECAT AL (EtherCAT in operating system user's space
Application Layer) function, the data link layer ECAT DLL of the completion EtherCAT communication systems of FPGA 20 main website
(EtherCAT Data Link Layer) function and physical layer ECAT PL (EtherCAT Physical Layer) manage work(
Energy.Ethernet transceiver 30 connects EtherCAT slave stations by the ports RJ45 all the way, carries out the transmitting-receiving of data message, in addition all the way
Ethernet transceiver 30 is used as main website ring redundancy.
Main processing block 10 includes the PDO interactive units 11 for operating in application layer, and FPGA 20 includes operating in data link
PDO Transmit-Receive Units 22, distribution clock unit 21 and the physical layer control unit 24 for operating in physical layer of layer, above-mentioned PDO are handed over
Mutual unit 11, PDO Transmit-Receive Units 22, distribution clock unit 21 and physical layer control unit 24 are in combination with corresponding software reality
It is existing.
Distribution clock unit 21 is used for that (rather than the clock of main processing block 10 to be believed according to the hardware clock signal of FPGA 20
Number) distribution clock message is periodically generated, to realize that motion controller clock is synchronous with the clock of servo slave station.Specifically,
Distribution clock unit 21 includes delay setting unit, clock transmission unit and starts control unit.As shown in figure 3, delay is set
Unit is set in 21 initialization procedure of distribution clock unit, transmission delay and time of the measuring and calculating main website to reference clock slave station SL0
Biasing, and result of calculation is arranged to reference clock slave station SL0；Clock transmission unit is periodically by the data link layer of FPGA 20
(DLL) clock Clock M are sent to each servo slave station SL1, SL2 ..., SLN (N is integer), when being distributed using EtherCAT
Clock synchronization mechanism, it is ensured that on all servo slave station distribution clocks (DC) and master clock stringent synchronization；Start control unit in master
Clock of standing it is synchronous with servo slave station clock it is upper after, calculate each servo slave station synchronizing signal start time and main website interruption
(Interrupt) start the time, and ensure that all slave station synchronizing signals start time and main website interrupt start time in phase
Alignment.
By the distribution clock unit 21 of the hardware clock based on FPGA 20, motion controller is interrupted according to above-mentioned main website
The period planning data of signal work can be synchronized in same period by all servo slave stations and be executed, and realize that high speed, high-precision height are synchronous
Properties Control.
PDO interactive units 11 be used for according to application layer task call generate PDO data, including I/O data, control data,
Status data etc., and the feedback data from servo slave station is handled for application layer task call.PDO Transmit-Receive Units 22 are based on distribution
The communication cycle (hardware clock i.e. based on FPGA 20) of clock unit 21 will come from PDO (Process Data Object) and hand over
The PDO data of mutual unit 11 are encapsulated as EtherCAT data frames and by the EtherCAT data frames from physical layer control unit 24
Solution, which is honored as a queen, sends PDO interactive units 11 to；Physical layer control unit 24 realizes EtherCAT for controlling ethernet transceiver 30
The full duplex of data frame is received and dispatched and the transmission of distribution clock message.
The highest PDO of requirement of real-time in EtherCA physical layers is received and dispatched by above-mentioned demixing technology in EtherCAT main websites
Function is placed in FPGA 20 and realizes, ensures EtherCAT master station communications to real-time in real time using FPGA 20 hardware of itself
Rigors.
In addition, since physical layer management function (i.e. physical layer control unit 24) is also realized in FPGA 20, behaviour is eliminated
Make system to dispatch the driving of ethernet transceiver 30, to eliminate the delay variation of EtherCAT data messages transmitting-receiving
Problem eliminates the shake of EtherCAT data message sending cycles, when EtherCAT communication systems being made to obtain stable distribution
Clock net synchronization capability.Since data link layer of the real-time in FPGA 20 is protected, and the application layer of EtherCAT main websites can
To run directly in the user's space of the operating system of main processing block 10, without increasing module in kernel spacing or mending in real time
Fourth, in the case of obtaining superior strong, moreover it is possible to which the load for maximally reducing operating system ensures the reliable of system
Stable operation.
The main processing block 10 of above-mentioned main website further includes document analysis unit 13, station scans unit 12, state machine management
Unit 15, dispensing unit 14 and mailbox communication unit 16, correspondingly, FPGA 20 include SDO (Service Data
Object) Transmit-Receive Unit 23, the SDO Transmit-Receive Units 23 be used for by physical layer control unit 24 realize document analysis unit 13,
Station scans unit 12, state machine administrative unit 15, dispensing unit 14 and mailbox communication unit 16 and each servo slave station
Data interaction, that is, receive document analysis unit 13, station scans unit 12, state machine administrative unit 15, dispensing unit 14 and
The data message of mailbox communication unit 16 is subsequently forwarded to physical layer control unit 24, while receiving physical layer control unit 24
The data message of return notifies the correlation unit of application layer to read.
Specifically, document analysis unit 13 parsed from the device description file (XML file) of EtherCAT slave stations with
Relevant slave station information is configured, such as：Supplier ID (Vendor ID), product code (Product Code) and process data
PDO (Process Data Object) mappings etc..Station scans unit 12 is for realizing main website to being connected to EtherCAT network
On all slave stations be scanned, obtain the device descriptive information of online slave station number and each slave station.State machine (Finite
State Machine, FSM) administrative unit 15 be used to complete each slave station apply layer state handover management, including four kinds of states
Management：Initialize (INIT), pre-operation (PREOP), safety operation (SAFEOP), mode of operation (OP).Dispensing unit 14 is used for
After slave station enters PREOP states, the operation mode wanted according to user carries out relevant configuration to EtherCAT slave stations, such as logical
Believe period, synchronous mode, DC periods, PDO mappings etc..Mailbox communication unit 16 is for realizing EtherCAT service datas SDO
The read-write of (Service Data Object) can include partly or entirely following application layer protocol depending on main website specification：CoE
(CANopen over EtherCAT)、SoE(Servo over EtherCAT)、FoE(File over EtherCAT)、EoE
(Ethernet over EtherCAT)、AoE(ADS over EtherCAT)、VoE(Vendor over EtherCAT)。
Particularly, above-mentioned physical layer control unit 24 may also include packet filtering unit, for filtering non-EtherCAT reports
Text.
The present invention also provides a kind of EtherCAT communication means, and the wherein main website in EtherCAT communication systems includes main place
Module, FPGA and ethernet transceiver are managed, and reference clock slave station and servo slave station are connected by ethernet transceiver；The party
Method includes the following steps：
(a) FPGA according to the clock signal period of the FPGA is sent to servo slave station by ethernet transceiver and is distributed
Clock message, to realize that motion controller clock is synchronous with the clock of servo slave station.
The step specifically may include：FPGA calculates main website to the transmission delay and time offset of reference clock slave station and will count
Result setting is calculated to reference clock slave station；The clock of FPGA is sent to each servo slave station by FPGA timings；FPGA main website with
After the clock of servo slave station synchronizes, when calculating the synchronizing signal of each servo slave station and starting the interrupt start of time and main website
Between, the synchronizing signal startup time of servo slave station is aligned with the interrupt start time of main website in phase.
(b) PDO from main processing block is encapsulated as EtherCAT data frames according to communication cycle and will come from by FPGA
The EtherCAT data frame solutions of physical layer control unit, which are honored as a queen, sends main processing block to；
(c) FPGA controls the full duplex transmitting-receiving that ethernet transceiver realizes EtherCAT data frames.
In above-mentioned EtherCAT communication means, in addition to PDO data transmit-receives, it may also include：FPGA is received and dispatched by Ethernet
Device realizes the transmitting-receiving of the SDO between main website and slave station；Main processing block describes to parse in file according to the FPGA slave station equipments received
Go out and configures relevant slave station information；Main processing block is by FPGA to all clock references for being connected in EtherCAT network
Slave station and servo slave station are scanned, and obtain the device descriptive information of online slave station number and each slave station；Main processing block is logical
Cross the application layer state handover management that FPGA completes each slave station；Main processing block carries out relevant configuration by FPGA to slave station；It is main
Processing module realizes mailbox communication by FPGA and servo slave station.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
Any one skilled in the art in the technical scope disclosed by the present invention, the change or replacement that can be readily occurred in,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with scope of the claims
Subject to.
Claims (10)
1. a kind of EtherCAT communication systems main website, it is characterised in that：It is received and dispatched including main processing block, FPGA and Ethernet
Device, and reference clock slave station and servo slave station are connected by the ethernet transceiver；The main processing block includes PDO interactions
Unit, the FPGA include PDO Transmit-Receive Units, distribution clock unit and physical layer control unit；Wherein：The distribution clock
Unit generates distribution clock message for the clock signal period according to FPGA, to realize motion controller clock and watch
The clock for obeying station synchronizes；The PDO Transmit-Receive Units will come from PDO for the communication cycle according to distributed clock unit and hand over
The slave station interaction data of mutual unit is encapsulated as EtherCAT data frames and by the EtherCAT data from physical layer control unit
Frame solution, which is honored as a queen, sends PDO interactive units to；The physical layer control unit realizes EtherCAT for controlling ethernet transceiver
The full duplex of data frame is received and dispatched and the transmission of distribution clock message.
2. EtherCAT communication systems according to claim 1 main website, it is characterised in that：The distribution clock unit includes
Be delayed setting unit, clock transmission unit and startup control unit, wherein：The delay setting unit, for calculating main website
To reference clock slave station transmission delay and time offset and by result of calculation setting to reference clock slave station；The clock is sent
The clock of FPGA is sent to each servo slave station by unit for timing；The startup control unit, in main website and servo
After the clock of slave station synchronizes, the synchronizing signal for calculating each servo slave station starts the interrupt start time of time and main website, institute
The synchronizing signal startup time for stating servo slave station is aligned with the interrupt start time of main website in phase.
3. EtherCAT communication systems according to claim 1 main website, it is characterised in that：The main processing block of the main website
It is described including document analysis unit, station scans unit, state machine administrative unit, dispensing unit and mailbox communication unit
FPGA includes SDO Transmit-Receive Units, and the SDO Transmit-Receive Units are used to realize document analysis unit by physical layer control unit, stand
The data interaction of spot scan unit, state machine administrative unit, dispensing unit and mailbox communication unit and each servo slave station.
4. EtherCAT communication systems according to claim 1 main website, it is characterised in that：The main website includes two ether
Net transceiver, and one of ethernet transceiver is for carrying out the transmitting-receiving of data message, another ethernet transceiver is used for
Realize main website ring redundancy, the physical layer control unit includes Port Management unit, and the Port Management unit is for realizing end
Mouth connection status and ring redundancy processing.
5. EtherCAT communication systems according to claim 1 main website, it is characterised in that：The physical layer control unit packet
Packet filtering unit is included, for filtering non-EtherCAT messages.
6. a kind of EtherCAT communication systems master station communication method, it is characterised in that：The main website includes main processing block, FPGA
And ethernet transceiver, and reference clock slave station and servo slave station are connected by the ethernet transceiver；The method packet
Include following steps：
(a) FPGA according to the clock signal period of the FPGA is sent to servo slave station by ethernet transceiver and is distributed
Clock message, to realize that motion controller clock is synchronous with the clock of servo slave station；
(b) PDO from main processing block is encapsulated as EtherCAT data frames by the FPGA according to the communication cycle of the FPGA
And the EtherCAT data frame solutions from physical layer control unit are honored as a queen and send main processing block to；
(c) the FPGA controls ethernet transceiver realizes the full duplex transmitting-receiving of EtherCAT data frames.
7. EtherCAT communication systems master station communication method according to claim 6, it is characterised in that：The step (a)
Including：
(a1) FPGA calculates main website to the transmission delay and time offset of reference clock slave station and arrives result of calculation setting
Reference clock slave station；
(a2) clock of FPGA is sent to each servo slave station by the FPGA timings；
(a3) after main website is synchronous with the clock of servo slave station, the synchronizing signal for calculating each servo slave station starts the FPGA
The synchronizing signal of the interrupt start time of time and main website, the servo slave station start the time and the interrupt start time of main website exists
It is aligned in phase.
8. EtherCAT communication systems master station communication method according to claim 6, it is characterised in that：The method is also wrapped
It includes：
The FPGA realizes the transmitting-receiving of the SDO between main website and slave station by ethernet transceiver；
The main processing block describes document analysis according to the FPGA slave station equipments received and goes out and the relevant slave station information of configuration；
The main processing block is by FPGA to all clock reference slave stations and the servo slave station that are connected in EtherCAT network
It is scanned, obtains the device descriptive information of online slave station number and each slave station；
The main processing block completes the application layer state handover management of each slave station by FPGA；
The main processing block carries out relevant configuration by FPGA to slave station；
The main processing block realizes mailbox communication by FPGA and servo slave station.
9. EtherCAT communication systems master station communication method according to claim 6, it is characterised in that：The main website includes
Two ethernet transceivers, and one of ethernet transceiver is used to carry out the transmitting-receiving of data message, another Ethernet is received
Device is sent out for realizing main website ring redundancy, the method includes：The FPGA carries out port connection state, ring redundancy processing.
10. EtherCAT communication systems master station communication method according to claim 6, it is characterised in that：The method packet
It includes：The FPGA filters non-EtherCAT messages.
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| CN201511031363.2A CN105656592B (en) | 2015-12-31 | 2015-12-31 | EtherCAT communication systems main website and communication means |
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| CN201511031363.2A CN105656592B (en) | 2015-12-31 | 2015-12-31 | EtherCAT communication systems main website and communication means |
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| CN107168161A (en) * | 2017-05-25 | 2017-09-15 | 电子科技大学 | EtherCAT master-salve station communication systems based on ROS systems |
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