CN105655352B - The production method of low temperature polycrystalline silicon tft array substrate - Google Patents
The production method of low temperature polycrystalline silicon tft array substrate Download PDFInfo
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- CN105655352B CN105655352B CN201610024267.3A CN201610024267A CN105655352B CN 105655352 B CN105655352 B CN 105655352B CN 201610024267 A CN201610024267 A CN 201610024267A CN 105655352 B CN105655352 B CN 105655352B
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 79
- 239000000758 substrate Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 239000010410 layer Substances 0.000 claims abstract description 158
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 69
- 238000004380 ashing Methods 0.000 claims abstract description 23
- 239000011229 interlayer Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 14
- 150000002500 ions Chemical class 0.000 claims description 43
- 229920005591 polysilicon Polymers 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 239000011241 protective layer Substances 0.000 claims description 10
- -1 phosphonium ion Chemical class 0.000 claims description 8
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 230000005611 electricity Effects 0.000 claims 2
- 239000012535 impurity Substances 0.000 abstract description 10
- 239000002245 particle Substances 0.000 abstract description 10
- 238000007711 solidification Methods 0.000 abstract description 8
- 230000008023 solidification Effects 0.000 abstract description 8
- 239000010408 film Substances 0.000 description 21
- 238000010586 diagram Methods 0.000 description 7
- 239000010409 thin film Substances 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 229920001621 AMOLED Polymers 0.000 description 3
- 208000037656 Respiratory Sounds Diseases 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005401 electroluminescence Methods 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The present invention provides a kind of production method of low temperature polycrystalline silicon tft array substrate, this method is completely removed remaining solidification photoresist after ion doping totally by the ashing of photoresist twice in succession and removing photoresistance processing, effectively solve the problems, such as that photoresist layer some regions before first time ashing is handled may be covered with impurity particle and stop and cure photoresist residual caused by first time ashing is handled, the interface cleanness degree that gate insulating layer and interlayer insulating film can be improved avoids product yield caused by interface problem from declining.
Description
Technical field
The present invention relates to display technology field more particularly to a kind of production methods of low temperature polycrystalline silicon tft array substrate.
Background technology
Thin film transistor (TFT) (Thin Film Transistor, TFT) is current liquid crystal display device (Liquid Crystal
Display, LCD) and active matrix drive type organic electroluminescence display device and method of manufacturing same (Active Matrix Organic Light-
Emitting Diode, AMOLED) in main driving element, the display performance of direct relation panel display apparatus.
Thin film transistor (TFT) has various structures, and the material for preparing the thin film transistor (TFT) of corresponding construction also has a variety of, low temperature
Polysilicon (Low Temperature Poly-silicon, LTPS) material is wherein more preferred a kind of, since low temperature is more
The atomic rule of crystal silicon arranges, and carrier mobility is high, and for the liquid crystal display device of voltage driven type, low temperature polycrystalline silicon is thin
Film transistor can use the thin film transistor (TFT) of small volume to realize to the inclined of liquid crystal molecule since it is with higher mobility
Turn driving, largely reduce the volume shared by thin film transistor (TFT), increase glazed area, obtains higher brightness reconciliation
Analysis degree；For the active matrix drive type organic electroluminescence display device and method of manufacturing same of current-driven, low-temperature polysilicon film is brilliant
Body pipe can better meet driving current requirement.
Whether LCD or AMOLED includes a tft array substrate.
The manufacturing process of existing low temperature polycrystalline silicon tft array substrate is usually：On underlay substrate from bottom to up successively
Make light shield layer, insulating buffer layer, low-temperature polysilicon silicon semiconductor layer, gate insulating layer, grid, interlayer insulating film, source/drain,
Flatness layer, bottom electrode, protective layer and top layer electrode.Wherein, low-temperature polysilicon silicon semiconductor layer includes positioned at intermediate correspondence again
Channel region in grid and the ion doped region corresponding to source/drain positioned at both ends.
Make ion doped region detailed process be：Photoresist is coated on low-temperature polycrystalline silicon layer first, photoresist is exposed
Patterned photoresist layer is obtained after light, development, baking, to expose two end regions of low-temperature polycrystalline silicon layer；Then with photoresist layer
For shielding layer, ion doping is carried out to two end regions of low-temperature polycrystalline silicon layer；Next photoresist ashing and removing photoresistance are successively carried out.
In this course, some regions of photoresist layer may be covered with impurity particle, block photoresist ashing, lead to not go completely
Removing photoresistance layer causes to cure photoresist residual, and then influences the interface matter of the gate insulating layer, interlayer insulating film that subsequently make
The problems such as measuring, gate insulating layer, interlayer insulating film is caused to generate peeling and crackle eventually leads to product quality decline.
The measure for improving gate insulating layer, layer insulation bed boundary existing at present has：Cleaning condition is changed before film forming
Or plasma treatment is carried out, but these measures are acted on limited and are all ignored because the photoresist layer used in ion doping is at ashing
Before reason some regions may be covered with impurity particle and caused by solidification photoresist residual the problem of.
Invention content
The purpose of the present invention is to provide a kind of production methods of low temperature polycrystalline silicon tft array substrate, can completely remove
Remaining solidification photoresist after ion doping improves the interface cleanness degree of gate insulating layer and interlayer insulating film, avoids interface problem
Caused product yield declines.
To achieve the above object, the present invention provides a kind of production methods of low temperature polycrystalline silicon tft array substrate, including such as
Lower step：
Step 1 provides a underlay substrate, patterned light shield layer is formed on the underlay substrate, in the light shield layer
With deposition covering insulating buffer layer on underlay substrate；
Step 2 forms the patterned low-temperature polycrystalline silicon layer for corresponding to the light shield layer on the insulating buffer layer；
Step 3 is coated with photoresist on the low-temperature polycrystalline silicon layer and buffer layer, patterns the photoresist, shape
At photoresist layer, two end regions of at least partly low-temperature polycrystalline silicon layer are exposed；
Step 4, using the photoresist layer as shielding layer, two end regions of corresponding low-temperature polycrystalline silicon layer are carried out a type of
Ion doping forms low-temperature polysilicon silicon semiconductor layer；
Step 5 carries out first time photoresist ashing and removing photoresistance processing；
Step 6 carries out second of photoresist ashing and removing photoresistance processing, to completely remove photoresist layer；
Step 7, made successively in the low-temperature polysilicon silicon semiconductor layer and insulating buffer layer gate insulating layer, grid,
Interlayer insulating film, source/drain, flatness layer, bottom electrode, protective layer and top layer electrode.
The step 7 further includes being coated on grid and gate insulating layer and patterning photoresist after completing the production grid
Material forms another photoresist layer, using another photoresist layer as shielding layer, to carrying out the remaining of ion doping without step 4
Two end regions of low-temperature polycrystalline silicon layer carry out another type of ion doping, form low-temperature polysilicon silicon semiconductor layer, and continuous
The process of photoresist ashing and removing photoresistance processing twice, makes the interlayer insulating film again later.
The specific manufacturing process of patterned low-temperature polycrystalline silicon layer is in the step 2：First on the insulating buffer layer
One layer of non-crystalline silicon is deposited, then Crystallizing treatment is carried out to non-crystalline silicon, low temperature polycrystalline silicon is made, pattern is then obtained by lithographic process
The low-temperature polycrystalline silicon layer of change.
The photoresist is patterned by exposure, developing manufacture process in the step 3 and obtains the photoresist layer.
A type of ion doping described in step 4 is the N-type ion doping or doping boron ion for adulterating phosphonium ion
P-type ion doping；Another type of ion doping described in step 7 is the p-type ion doping or N-type different from step 4
Ion doping.
The source/drain passes through the via and the low temperature polycrystalline silicon half through interlayer insulating film and gate insulating layer respectively
The both ends of conductor layer are in contact.
The insulating buffer layer, gate insulating layer, interlayer insulating film, flatness layer and protective layer material be silica,
One or both of silicon nitride it is compound.
The top layer electrode passes through via through the protective layer, bottom electrode and flatness layer and the drain contact.
The material of the top layer electrode and bottom electrode is ITO.
Beneficial effects of the present invention：A kind of production method of low temperature polycrystalline silicon tft array substrate provided by the invention passes through
Photoresist ashing and removing photoresistance processing completely remove remaining solidification photoresist after ion doping totally twice in succession, effectively solve light
Resistance layer first time ashing processing before some regions may be covered with impurity particle and stop first time ashing processing caused by
The problem of curing photoresist residual, can improve the interface cleanness degree of gate insulating layer and interlayer insulating film, interface problem is avoided to lead
The product yield of cause declines.
Description of the drawings
For further understanding of the features and technical contents of the present invention, it please refers to below in connection with the detailed of the present invention
Illustrate and attached drawing, however, the drawings only provide reference and explanation, is not intended to limit the present invention.
In attached drawing,
Fig. 1 is the flow chart of the production method of the low temperature polycrystalline silicon tft array substrate of the present invention；
Fig. 2 is the schematic diagram of the step 1 of the production method of the low temperature polycrystalline silicon tft array substrate of the present invention；
Fig. 3 is the schematic diagram of the step 2 of the production method of the low temperature polycrystalline silicon tft array substrate of the present invention；
Fig. 4 is the schematic diagram of the step 3 of the production method of the low temperature polycrystalline silicon tft array substrate of the present invention；
Fig. 5 is the schematic diagram of the step 4 of the production method of the low temperature polycrystalline silicon tft array substrate of the present invention；
Fig. 6 is the schematic diagram of the step 5 of the production method of the low temperature polycrystalline silicon tft array substrate of the present invention；
Fig. 7 is the schematic diagram of the step 6 of the production method of the low temperature polycrystalline silicon tft array substrate of the present invention；
Fig. 8 is the schematic diagram of the step 7 of the production method of the low temperature polycrystalline silicon tft array substrate of the present invention.
Specific implementation mode
Further to illustrate the technological means and its effect of the invention taken, below in conjunction with the preferred implementation of the present invention
Example and its attached drawing are described in detail.
Referring to Fig. 1, the present invention provides a kind of production method of low temperature polycrystalline silicon tft array substrate, include the following steps：
Step 1, as shown in Fig. 2, provide a underlay substrate 10, patterned light shield layer is formed on the underlay substrate 10
11, the deposition covering insulating buffer layer 12 on the light shield layer 11 and underlay substrate 10.
Specifically, the underlay substrate 10 is preferably glass substrate；The material of the light shield layer 11 is lighttight metal；
The material of the insulating buffer layer 12 is the compound of one or both of silica (SiOx), silicon nitride (SiNx), it is preferred that
The insulating buffer layer 12 includes the silicon nitride layer and silicon oxide layer being stacked from bottom to top.
Step 2 corresponds to the patterned of the light shield layer 11 as shown in figure 3, being formed on the insulating buffer layer 12
Low-temperature polycrystalline silicon layer 20.
Specifically, the detailed process of the step 2 is：One layer of non-crystalline silicon is first deposited on the insulating buffer layer 12, then is led to
Cross quasi-molecule laser annealing (Excimer Laser Annealing, ELA) or solid-phase crystallization (Solid Phase
Crystallization, SPC) etc. modes to non-crystalline silicon carry out Crystallizing treatment, so that recrystallized amorphous silicon is changed into low temperature polycrystalline silicon,
Then the patterned low-temperature polycrystalline silicon layer 20 is obtained by lithographic process.
Step 3, as shown in figure 4, being coated with photoresist on the low-temperature polycrystalline silicon layer 20 and insulating buffer layer 12, pass through
Exposure, developing manufacture process pattern the photoresist, form photoresist layer 30, expose the two of at least partly low-temperature polycrystalline silicon layer 20
End regions.
It is noted that if the final low temperature polycrystalline silicon tft array substrate obtained of design only includes the list of N-type or p-type
Type TFT, then patterned photoresist layer 30 should expose two end regions of whole low-temperature polycrystalline silicon layers 20 in the step 3；If design
Final low temperature polycrystalline silicon tft array substrate obtained had not only included N-type TFT but also had included p-type TFT, then patterned light in the step 3
Resistance layer 30 should expose two end regions of part low-temperature polycrystalline silicon layer 20.
Step 4, as shown in figure 5, being shielding layer with the photoresist layer 30, to two end regions of corresponding low-temperature polycrystalline silicon layer 20
A type of ion doping is carried out, low-temperature polysilicon silicon semiconductor layer 20 ' is formed, wherein becoming more by the region of ion doping
The source drain contact area of crystal silicon semiconductor layer 20 ', the region without ion doping become the raceway groove of polysilicon semiconductor layer 20 '
Area.
It is noted that if the final low temperature polycrystalline silicon tft array substrate obtained of design only includes N-type TFT, the step
A type of ion doping described in rapid 4 is the N-type ion doping for adulterating phosphorus (P) ion；If the final low temperature obtained of design
Multi-crystal TFT array substrate only include p-type TFT, then a type of ion doping described in the step 4 be doping boron (B) from
The p-type ion doping of son；If the final low temperature polycrystalline silicon tft array substrate obtained of design had not only included N-type TFT but also had included p-type
TFT, then a type of ion doping described in the step 4 is the one of which of N-type ion doping, p-type ion doping.
As shown in Figure 5, the ion doping process of the step 4 can cause some regions of impurity particle covering photoresist layer 30.
Step 5 carries out first time photoresist ashing and removing photoresistance processing.
As shown in fig. 6, after the step 5 completes the ashing of first time photoresist and removing photoresistance processing, can will be generated in above-mentioned steps 4
Impurity particle and do not removed by the part photoresist layer 30 that impurity particle covers, but the area that photoresist layer 30 is covered by impurity particle
Domain can then remain solidification photoresist since impurity particle blocks photoresist ashing.
Step 6 carries out second of photoresist ashing and removing photoresistance processing.
As described in Figure 7, the step 6 carry out again photoresist ashing and removing photoresistance processing can remove first time photoresist ashing and
Remaining solidification photoresist after removing photoresistance processing provides to completely eliminated photoresist layer 30 for subsequent gate insulating layer film forming
Clean interface avoids interface problem that gate insulating layer is caused to occur peeling off and crackle etc..
Step 7, as shown in figure 8, making grid successively in the low-temperature polysilicon silicon semiconductor layer 20 ' and insulating buffer layer 12
Pole insulating layer 31, grid 41, interlayer insulating film 32, source/drain 42, flatness layer 50, bottom electrode 60, protective layer 70 and top layer
Electrode 80.
It is noted that if the final low temperature polycrystalline silicon tft array substrate obtained of design only includes N-type TFT or p-type
TFT, then the step 7 only make above-mentioned each film layer successively；If the final low temperature polycrystalline silicon tft array substrate obtained of design was both
Include again p-type TFT including N-type TFT, then the step 7 further includes in grid 41 and gate insulating layer after completing the production grid 41
Photoresist is coated with and patterned on 31, forms another photoresist layer, using another photoresist layer as shielding layer, to without step 4
Two end regions for carrying out the remaining low-temperature polycrystalline silicon layer 20 of ion doping carry out another type of ion doping, form low temperature
Polysilicon semiconductor layer, and twice in succession photoresist ashing and removing photoresistance processing process, be subsequent interlayer insulating film 32 at
Film provides clean interface, avoids interface problem that interlayer insulating film 32 is caused peeling and crackle etc. occur, makes again later described
Interlayer insulating film 32.Further, if what is carried out in the step 4 is N-type ion doping, p-type ion is carried out in the step 7
Doping；If what is carried out in the step 4 is p-type ion doping, N-type ion doping is carried out in the step 7.
Specifically, the source/drain 42 passes through via through interlayer insulating film 32 and gate insulating layer 31 and institute respectively
The both ends for stating low-temperature polysilicon silicon semiconductor layer 20 ' are in contact.
The top layer electrode 80 passes through via 81 through the protective layer 70, bottom electrode 60 and flatness layer 50 and institute
State drain contact.
The gate insulating layer 31, interlayer insulating film 32, flatness layer 50 and protective layer 70 material be silica, nitrogen
One or both of SiClx it is compound.
The material of the top layer electrode 80 and bottom electrode 60 is tin indium oxide (Indium Tin Oxide, ITO).
In conclusion the production method of the low temperature polycrystalline silicon tft array substrate of the present invention is ashed by photoresist twice in succession
Remaining solidification photoresist after ion doping is completely removed totally with removing photoresistance processing, photoresist layer is effectively solved and is ashed in first time
Before processing some regions may be covered with impurity particle and solidification caused by stopping first time ashing processing photoresist is remaining asks
Topic, can improve the interface cleanness degree of gate insulating layer and interlayer insulating film, and product yield caused by interface problem is avoided to decline.
The above for those of ordinary skill in the art can according to the technique and scheme of the present invention and technology
Other various corresponding change and deformations are made in design, and all these change and distortions should all belong to the claims in the present invention
Protection domain.
Claims (8)
1. a kind of production method of low temperature polycrystalline silicon tft array substrate, which is characterized in that include the following steps：
Step 1 provides a underlay substrate (10), patterned light shield layer (11) is formed on the underlay substrate (10), in institute
State light shield layer (11) and deposition covering insulating buffer layer (12) on underlay substrate (10)；
Step 2 forms the patterned low temperature polycrystalline silicon for corresponding to the light shield layer (11) on the insulating buffer layer (12)
Layer (20)；
Step 3 is coated with photoresist on the low-temperature polycrystalline silicon layer (20) and insulating buffer layer (12), patterns the photoresist
Material forms photoresist layer (30), exposes two end regions of at least partly low-temperature polycrystalline silicon layer (20)；
Step 4, with the photoresist layer (30) for shielding layer, a type is carried out to two end regions of corresponding low-temperature polycrystalline silicon layer (20)
The ion doping of type forms low-temperature polysilicon silicon semiconductor layer (20 ')；
Step 5 carries out first time photoresist ashing and removing photoresistance processing；
Step 6 carries out second of photoresist ashing and removing photoresistance processing, to completely remove photoresist layer (30)；
Step 7 makes gate insulating layer successively on the low-temperature polysilicon silicon semiconductor layer (20 ') and insulating buffer layer (12)
(31), grid (41), interlayer insulating film (32), source/drain (42), flatness layer (50), bottom electrode (60), protective layer (70),
And top layer electrode (80)；
The insulating buffer layer (12), gate insulating layer (31), interlayer insulating film (32), flatness layer (50) and protective layer (70)
Material be the compound of one or both of silica, silicon nitride.
2. the production method of low temperature polycrystalline silicon tft array substrate as described in claim 1, which is characterized in that the step 7 exists
Further include being coated with and patterning photoresist, shape on grid (41) and gate insulating layer (31) after completing the production grid (41)
At another photoresist layer, using another photoresist layer as shielding layer, to carrying out the remaining low-temperature polysilicon of ion doping without step 4
Two end regions of silicon layer (20) carry out another type of ion doping, form low-temperature polysilicon silicon semiconductor layer (20 '), and continuous
The process of photoresist ashing and removing photoresistance processing twice, makes the interlayer insulating film (32) again later.
3. the production method of low temperature polycrystalline silicon tft array substrate as described in claim 1, which is characterized in that in the step 2
The specific manufacturing process of patterned low-temperature polycrystalline silicon layer (20) is：One layer of amorphous is first deposited on the insulating buffer layer (12)
Silicon, then Crystallizing treatment is carried out to non-crystalline silicon, low temperature polycrystalline silicon is made, patterned low-temperature polysilicon is then obtained by lithographic process
Silicon layer (20).
4. the production method of low temperature polycrystalline silicon tft array substrate as described in claim 1, which is characterized in that in the step 3
The photoresist, which is patterned, by exposure, developing manufacture process obtains the photoresist layer (30).
5. the production method of low temperature polycrystalline silicon tft array substrate as claimed in claim 2, which is characterized in that described in step 4
A type of ion doping be adulterate phosphonium ion N-type ion doping or adulterate boron ion p-type ion doping；Step 7
Described in another type of ion doping be different from step 4 p-type ion doping or N-type ion doping.
6. the production method of low temperature polycrystalline silicon tft array substrate as described in claim 1, which is characterized in that the source/drain
(42) pass through the via for running through interlayer insulating film (32) and gate insulating layer (31) and the low-temperature polysilicon silicon semiconductor layer respectively
The both ends of (20 ') are in contact.
7. the production method of low temperature polycrystalline silicon tft array substrate as described in claim 1, which is characterized in that the top layer electricity
Pole (80) is connect by running through the via (81) of the protective layer (70), bottom electrode (60) and flatness layer (50) with the drain electrode
It touches.
8. the production method of low temperature polycrystalline silicon tft array substrate as described in claim 1, which is characterized in that the top layer electricity
The material of pole (80) and bottom electrode (60) is ITO.
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| CN108666218A (en) * | 2017-03-29 | 2018-10-16 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and display base plate and preparation method thereof, display device |
| WO2018232698A1 (en) * | 2017-06-22 | 2018-12-27 | 深圳市柔宇科技有限公司 | Apparatus for manufacturing array substrate and method for manufacturing array substrate |
| CN107611139B (en) * | 2017-08-10 | 2020-06-30 | 昆山龙腾光电股份有限公司 | Thin film transistor array substrate and manufacturing method thereof |
| CN107623042A (en) * | 2017-09-21 | 2018-01-23 | 深圳市华星光电半导体显示技术有限公司 | Thin-film transistor structure and preparation method thereof |
| CN108538860B (en) * | 2018-04-27 | 2021-06-25 | 武汉华星光电技术有限公司 | Manufacturing method of top gate type amorphous silicon TFT substrate |
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| CN1426544A (en) * | 2000-04-26 | 2003-06-25 | 东进瑟弥侃株式会社 | Light carving rubber stripper composition |
| CN105206568A (en) * | 2015-10-16 | 2015-12-30 | 京东方科技集团股份有限公司 | Low-temperature multi-crystalline silicon TFT array substrate preparation method and array substrate obtained through same |
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| CN105206568A (en) * | 2015-10-16 | 2015-12-30 | 京东方科技集团股份有限公司 | Low-temperature multi-crystalline silicon TFT array substrate preparation method and array substrate obtained through same |
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