CN105655328B - Active component and apply its semiconductor element - Google Patents
Active component and apply its semiconductor element Download PDFInfo
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- CN105655328B CN105655328B CN201410641127.1A CN201410641127A CN105655328B CN 105655328 B CN105655328 B CN 105655328B CN 201410641127 A CN201410641127 A CN 201410641127A CN 105655328 B CN105655328 B CN 105655328B
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Abstract
The invention discloses a kind of active component and its semiconductor element is applied, which includes a substrate；There is one first trap the surface of one first conductive state and self-reference substrate to extend downwardly；One diffusion zone adulterates the impurity of the first conductive state and is extended downwardly from the surface of the first trap；It is formed in diffusion zone with multiple active components, and these active components are arranged apartly.Active component is electrically insulated from by diffusion zone.The active component of embodiment be by one conductive guard bar structure by self-isolation (self isolated).Therefore, including the semiconductor element of the active component without shallow trench isolation (STI) of embodiment does not have the problem caused by the edges STI.
Description
Technical field
The invention relates to a kind of active component and its semiconductor element is applied, and certainly in particular to one kind
Be isolated (self-isolated) active component and one application this active component the semiconductor element without shallow trench isolation.
Background technology
It is usually used in super large-scale integration (Very-large-scale integration, VLSI) technology
Shallow trench isolation (shallow-trench isolation, STI) isolation active component (such as complementary metal-oxide is partly led
The transistor of body) and define channel width.However, correlative study person has found that the edges STI can cause to be permitted to application element thereof
More serious problems.
Fig. 1 is painted a kind of conventional in layout of semiconductor element.Semiconductor element includes that multiple active components 10 are apart
Ground is set on a substrate, and is all located in one first trap 12 of the first conductive state of tool, such as in the p-type trap of NMOS elements.Again
Person, a lightly doped region (light doping region) have one second conductive state (such as N-) and are located in p-type trap and surround
All active components 10 and p-type trap contact (P-well contact).Adjacent active component 10 is electrically isolated with STI.
Each active component 10 includes a diffusion zone DIF of the first conductive state of tool, one first contact area 111 (such as a drain region)
It is located in diffusion zone DIF with one second contact area 113 (such as source region) and a polysilicon gate PG
(having a gate contact 115 thereon) is formed between the first contact area 111 and the second contact area 113.To traditional half
For conductor element, the STI being present between neighboring active element 10 can cause undesirable STI edge effects (STI
edge issues)。
Fig. 2 is the diagrammatic cross-section of the polysilicon gate for being painted a conventional semiconductors element and the insulant of both sides.More than one
Polysilicon gate PG is formed at a grid oxic horizon GOX, channel 135 be then located at below polysilicon gate PG and insulant STI it
Between.Fig. 3 A are the ID-VG characteristic curves of typical low pressure (LV) NMOS transistor, and wherein grid oxic horizon GOX thickness isW/Lg=0.6 μm/0.4 μm, and these curves are in a drain bias (VD) measure and obtain under 0.1V.Fig. 3 B are one typical
High pressure (HV) NMOS transistor ID-VGCharacteristic curve, wherein grid oxic horizon GOX thickness areW/Lg=10 μm/
1.6 μm, and these curves are in a drain bias (VD) measure and obtain under 0.1V.Please refer to Fig. 1 to Fig. 3 B.The edges STI are typically
Semiconductor element " weakness " (such as at the choosing of Fig. 2 centre circles), abnormal subcritical drain current (subthreshold can be caused
Leakage current) and lead to undesirable bimodal (double hump) subcritical ID-VG characteristic curves (such as Fig. 3 A
Shown in the curve Process-1 in Fig. 3 B).In Fig. 3 A and Fig. 3 B, curve Process-1 represents the typical case for having bimodal leakage current
The I of NMOS transistorD-VGCharacteristic curve, curve Process-2 represent the I of the typical NMOS transistors with improvement STID-VG
Characteristic curve, curve Process-3 is represented, and there is improvement STI and STI abutment wall pockets to adulterate (sidewall STI pocket
Implant the I of typical NMOS transistors)D-VGCharacteristic curve.
In general, the edges STI usually will produce several non-ideal conditions, such as：(1) it is inclined that boron is generated on STI abutment walls
Lead to p-type trap doping loss (p-well dosage loss) from (boron segregation)；(2) stress caused by STI
Variation (STI induced stress) can influence the stability of critical voltage (Vt)；And (3) some interface traps
(interface trap) or dislocation can increase leakage current.These situations can cause undesirable subcritical characteristic and higher leakage
Current problems.Although at present often using a STI abutment wall pockets doping (sidewall STI pocket implant) in
Structure " weakness " at (such as at the choosing of Fig. 2 centre circles), the trap to improve part at STI abutment walls adulterates and inhibits bimodal leakage current
(double-hump leakage) (curve Process-3), structure still have disadvantage, including：(1) knot of high pressure NMOS can be reduced
It collapses (junction breakdown), because knot (NM is lightly doped) can be appreciated that more p-type trap doping in the edges STI, with
And (2) will produce serious narrow passage width effect (snarrow-width effect) when channel width dimension reduces.Therefore,
The doping of STI abutment wall pockets still affects the control of channel doping and critical voltage.
Furthermore due to the conventional configuration of active component 10, as shown in Figure 1, its overlapping polysilicon gate PG and diffusion region
Extension mode between the DIF of domain makes the spacing of neighboring active element 10 that can be restricted, and especially active component 10 is in Fig. 1
Arrangement on the directions x-.Therefore, because must take into account the design principle of diffusion zone DIF, this can be active for conventional configuration
The design principle (tight-pitch layout design rule) of one intensive pitch layout of element generates limitation.
Invention content
The invention relates to a kind of active component and apply its semiconductor element.The active component of embodiment is profit
The self-isolation with a conductive guard bar structure, and include the semiconductor of the embodiment of no shallow trench isolation (STI-free) active component
Element can successfully solve the problems, such as the STI edge effects (STI edge issues) that conventional semiconductors element suffers from.
It is to propose a kind of semiconductor element, including a substrate, one first trap have one first conductive state according to an embodiment
And the surface of self-reference substrate extends downwardly, adulterates a diffusion zone (diffusion region) for the impurity of the first conductive state simultaneously
It is extended downwardly from the surface of the first trap and multiple active components is formed in diffusion zone.Wherein, these active components are each other
It is arranged at a distance of ground, and is electrically insulated from by diffusion zone.
It is to propose a kind of active component, the expansion with one first conductive state being formed at a substrate according to embodiment
It dissipates in region.Active component includes a conductive guard bar structure (conductive guarding structure), one first contact
Region (first contact region) and one second contact area (second contact region).Conductive guardrail knot
Structure includes a middle part (middle portion), one first shield portion (first guarding portion) and the second shield portion
(second guarding portion).The side of first shield portion connection middle part is located at the one first of diffusion zone to define
Region, wherein first area are to be surrounded to form by the first shield portion and middle part.One second shield portion is opposite with the first shield portion and connects
The other side of middle part is located at a second area of diffusion zone to define, and wherein second area is by the second shield portion and middle part
Around into.First contact area has one second conductive state and is formed in the first area of conductive guard bar structure, and first
Contact area be with the first shield portion and the middle part apart.Second contact area has the second conductive state and is formed in conductive guardrail
In the second area of structure, and the second contact area be with the second shield portion and middle part apart.
More preferably understand in order to which the above-mentioned and other aspect to the present invention has, special embodiment below, and coordinates institute's attached drawing
Formula is described in detail below.However, protection scope of the present invention is subject to be defined depending on appended claims range.
Description of the drawings
Fig. 1 is painted a kind of conventional in layout of semiconductor element.
Fig. 2 is the diagrammatic cross-section of the polysilicon gate for being painted a conventional semiconductors element and the insulant of both sides.
Fig. 3 A are the I of typical low pressure (LV) NMOS transistorD-VGCharacteristic curve, wherein grid oxic horizon GOX thickness
ForW/Lg=0.6 μm/0.4 μm, and these curves are in a drain bias (VD) measure and obtain under 0.1V.
Fig. 3 B are the I of typical high pressure (HV) NMOS transistorD-VGCharacteristic curve, wherein grid oxic horizon GOX thickness
ForW/Lg=10 μm/1.6 μm, and these curves are in a drain bias (VD) measure and obtain under 0.1V.
Fig. 4 is the layout of the semiconductor element of the embodiment of the present invention.
Fig. 5 A are the schematic diagram of an active component of the semiconductor element of the embodiment of the present invention.
Fig. 5 B are the explosive view of a conductive guard bar structure of active component in Fig. 5 A.
Fig. 6 is the schematic diagram of two neighboring active elements in the semiconductor element for be painted Fig. 4.
Fig. 7 is painted two neighboring active elements in Fig. 4 of the embodiment of the present invention, and the source electrode in active component and leakage
The schematic diagram of drain current between pole.
Fig. 8 is to clearly show that no bimodal leakage current generates, and empirical value is and the simulation curve of theoretical model ideal
It overlaps.
Fig. 9 is that the page buffer circuit of the nand flash memory with reed bit line cell (BL Clamp Devices) designs.
Figure 10 is the layout for being painted a high-voltage semiconductor element in an embodiment.
Figure 11 is the cloth for the applicable CMOS including multiple active components of one of which for being painted one embodiment of the invention
Office.
Figure 12 A- Figure 12 D be painted respectively stereogram according to an embodiment of TCAD simulated experiments without STI transistors and
Along the sectional view of YZ- planes, XZ- planes and XY-plane.
Figure 13 A are painted the I without STI transistors of embodiment in TCAD simulated experimentsD-VGCharacteristic curve, wherein being to apply electricity
Press Vg1 and Vg2 in embodiment without STI transistors " Gate 1 " and " Gate2 " element.
Figure 13 B are the electricity for applying Vg1=0.5V, Vg2=3.8V and Vds=0.1V in " Gate 1 " and " Gate 2 " element
Current density emulates schematic diagram.
Figure 14 A are painted the I without STI transistors of embodiment in TCAD simulated experimentsD-VGCharacteristic curve, wherein being to change not
It it is 0.1 μm, 0.15 μm and 0.2 μm with width W2.
Figure 14 B are painted the I without STI transistors of embodiment in TCAD simulated experimentsD-VGCharacteristic curve, wherein being to change not
It it is 0.25 μm, 0.3 μm and 0.4 μm with passage length Lg.
Figure 15 A be TCAD simulated experiments in, an embodiment without STI transistors along the sectional view of XY-plane.
Figure 15 B- Figure 15 D are painted the I without STI transistors of embodiment in TCAD simulated experimentsD-VGCharacteristic curve, wherein scheming
The Vg2=3.8V and Vd1=of the Vg2=0V and Vd1=3.8V of the Vg2=0V and Vd1=0.1V of 15B, Figure 15 C, Figure 15 D
The Vg2=3.8V and Vd1=3.8V of 0.1V and Figure 15 E.
Figure 16 be painted embodiment in TCAD simulated experiments without the I-V in STI transistorsd1Characteristic curve.
【Symbol description】
10、20：Active component
12、PW：First trap
111：First contact area
113：Second contact area
115：Gate contact
135：Channel
22：Lightly doped region
24：Spacer
201：Conductive guard bar structure
201m：Middle part
2011：First shield portion
2012：Second shield portion
201a：First area
201b：Second area
211：First contact area
213：Second contact area
251：First contact
253：Second contact
255：Gate contact
S：Substrate
DIF：Diffusion zone
PG：Polysilicon gate
STI：Insulant
GOX：Grid oxic horizon
S1：First isolation distance
S2：Second isolation distance
W’：Effective channel width
W：The width of first area and second area
W2：The width in the first shield portion and the second shield portion
Lg：Passage length
doffset：Minimum range of the contact area to shield portion of the first shield portion/second
Specific implementation mode
It is to propose an active component and using its semiconductor element in the embodiment held within the present invention.Embodiment
Active component be that self-isolation (self- is reached with a conductive guard bar structure (conductive guarding structure)
Isolated), an e.g. polysilicon guard bar structure is also as the grid of active component.And Application Example is active without STI
The semiconductor element of element can successfully solve STI edge effects (the STI edge present in conventional semiconductors element
issues).The embodiment of the present invention can be applied to low pressure (LV) semiconductor element of many different aspects and high pressure (HV) is partly led
Volume elements part, the present invention are not limited with certain using aspect.It is to propose embodiment below, cooperation diagram is with the present invention will be described in detail
The one of which active component of proposition and the new layout of semiconductor element.However the present invention is not limited to this.In embodiment
Narration, such as thin portion structure, the size of coherent element and material selection are used, by way of example only not to the present invention
The range to be protected limits.
Furthermore the present invention not shows all possible embodiment.It can be without departing from the spirit and scope of the present invention
Structure and technique are changed and modified, to meet the needs of practical application.Therefore, not in other implementations proposed by the present invention
Aspect may also can be applied.Furthermore the dimension scale in schema is not drawn according to actual product equal proportion.Therefore, explanation
Book and diagramatic content are only described herein the use of embodiment, rather than are used as the scope of the present invention is limited.
Fig. 4 is the layout of the semiconductor element of the embodiment of the present invention.Fig. 5 A are the semiconductor member of the embodiment of the present invention
The schematic diagram of one active component of part.Fig. 5 B are the explosive view of a conductive guard bar structure of active component in Fig. 5 A.Fig. 6 is to be painted
The schematic diagram of two neighboring active elements in the semiconductor element of Fig. 4.Please refer to Fig. 4-Fig. 6.
In embodiment, semiconductor element includes a substrate S, one first trap with one first conductive state (such as p-type)
PW, a diffusion zone DIF and multiple active components 20 are formed in diffusion zone DIF (Fig. 4 and Fig. 6).First trap PW is from base
A surface of plate S extends downwardly, and the diffusion zone DIF with the first conductive state (such as p-type) is the table from the first trap PW
Extend (Fig. 6) downwards.As shown in figure 4, these active components 20 are arranged apartly, and all active components 20 are all formed
In in continuous diffusion zone DIF, wherein active component 20 is electrically insulated from by diffusion zone DIF.It is not shallow
Channel isolation (Shallow trench isolation, STI) is present between two adjacent active components 20.In an embodiment
In, diffusion zone DIF is the impurity of the first conductive state of heavily doped tool, such as P+, to provide field insulation (field
isolation)。
Furthermore each active component 20 includes a conductive guard bar structure (conductive guarding structure) 201
It is formed on diffusion zone DIF and a lightly doped region (light doping region) 22 has one second conductive state (example
Such as N-), and a surface of 22 self-diffusion region DIF of lightly doped region extends downwardly and is correspondingly located at conductive guard bar structure 201
Within.According to embodiment, an area of isolation (isolating region) between adjacent active component 20 (such as scheme
The region of middle mark isolation distance S1 or S2), it is to be defined by the conductive guard bar structure 201 of neighboring active element 20.Such as Fig. 4 institutes
Show, the neighboring active element 20 as the directions x- arrange is with the area of isolation institute with the first isolation distance S1 along a first direction
Isolation, and be with the isolated area with the second isolation distance S2 along the neighboring active element 20 of the second direction such as directions y- arrangement
Domain is completely cut off.First isolation distance S1 and the second isolation distance S2 can be unequal or equal.In one embodiment, first isolation away from
It is to be equal to the second isolation distance S2 from S1.According to embodiment, the space (S1/S2) between adjacent active component 20 is without shallow
Channel isolation (STI) exists, therefore the design of embodiment can be such that semiconductor element altogether dispenses in any STI edge effects (example
Such as the difference, etc. that bimodal subcritical drain current, breakdown voltage decline, difference STI is laid out).
In one embodiment, conductive guard bar structure 201 includes a middle part (middle portion) 201m, one first shield portion
(first guarding portion) 2011 and one second shield portion (second guarding portion) 2012, such as Fig. 5 A
Shown in Fig. 5 B.First shield portion 2011 connects the side of middle part 201m, to define one first area for being located at diffusion zone DIF
Domain (first region) 201a.Second shield portion 2012 is opposite with the first shield portion 2011 and connect the another of middle part 201m
Side, to define a second area (second region) 201b for being located at diffusion zone DIF.Therefore, first area 201a is
By the first shield portion 2011 and middle part 201m around forming, second area 201b is enclosed by the second shield portion 2012 and middle part 201
Around into.
As shown in figure 4, first area 201a and second area 201b is located in lightly doped region 22 in active component 20.
Lightly doped region 22 is to surround first area 201a and second area 201b but spaced a distance with it.In one embodiment, gently mix
Miscellaneous region 22 is located at corresponding first shield portion 2011 and the second shield portion 2012.Such as lightly doped region 22 boundary (i.e. Fig. 4 and
Dotted line in Fig. 5 A in an active component 20 is signified) it is in substantial corresponding first shield portion 2011 and 2012 hem width of the second shield portion
Between, as shown in Fig. 4 and Fig. 5 A.
Furthermore each active component 20 further includes with the second conductive state (such as N+) and is formed in conductive guard bar structure 201
First area 201a in one first contact area (first contact region) 211, and have the second conductive state (example
Such as N+) and it is formed in one second contact area (second contact in the second area 201b of conductive guard bar structure 201
region)213.And first contact area 211 be with the first shield portion 2011 and middle part 201m be spaced come, the second contact area
213 be to be spaced to come with the second shield portion 2012 and middle part 201m.In one embodiment, the contact of the first contact area 211 and second
It region 213 can be respectively as a drain region of active component 20 (drain region) and source region (source
region)。
As shown in fig. 6, it (is, for example, as leakage that each active component 20, which further includes one first contact (first contact) 251,
Pole) it is formed in the first contact area 211 and one second contact (second contact) 253 (being, for example, as source electrode) shape
At in the second contact area 213.Furthermore a gate contact (gate contact) 255 is contact conduction guard bar structure 201.One
In embodiment, gate contact 255 can be formed on the third contact area 215 of the middle part 201m of conductive guard bar structure 201,
Wherein gate contact 255 is correspondingly located in lightly doped region 22.However, gate contact 255 is not restricted to be painted in diagram
The position shown, it is also possible to other positions are formed in, as long as gate contact 255 can be electrically connected with conductive guard bar structure 201.
In the fabrication process, opening (corresponding first area 201a and second area 201b) shape of conductive guard bar structure 201
Cheng Hou is to be formed to be lightly doped in 201 lower section of conductive guard bar structure in a manner of adulterating a small amount of second conductive state (such as N-) impurity
Region 22, as shown in Figure 6.Later, the spacer (spacers, such as oxide) 24 being formed in a suitably dimensioned in opening is to define
Go out the first contact area 211 and the second contact area 213.Due to the area of the first contact area 211 and the second contact area 213
Very small (especially to the semiconductor element applied to small-sized electronic product), can be initially formed the first contact 251, the second contact 253
With gate contact 255, then the second conductive state impurity (such as N of high concentration is adulterated in a manner of plug injection (plug implant)
+) below these contacts.However, the present invention is not limited thereto manufacture.As preceding narration the step of by way of example only it
With the condition of visual practical application is required and does adjustment or variation appropriate.
According to an embodiment, the material of conductive guard bar structure 201 can be polysilicon, and in conductive guard bar structure 201
Between portion 201m can be used as the grid (i.e. polysilicon gate) of active component 20.Fig. 7 is painted two in Fig. 4 of the embodiment of the present invention
Neighboring active element, and between the source electrode and drain electrode of active component drain current schematic diagram.Referring to Fig. 4 and figure
7.It is in (such as side x- along a first direction as the middle part 201m of the conductive guard bar structure 201 of the grid of active component 20
To) on have effective channel width (effective channel width) W ', on along second direction (such as directions y-)
With a passage length (channel length) Lg.
In one embodiment, first direction (such as directions x-) is perpendicular to second direction (such as directions y-).Such as Fig. 4 and Fig. 7 institutes
Show, first area 201a and second area 201b are the distances for being separated by passage length Lg.Furthermore the first shield portion 2011 and second
(such as directions x-) respectively has a width W2, first area 201a and second area 201b along the along a first direction in shield portion 2012
One direction respectively has a width W.It is formed in the first contact 251 of the first contact area 211 and is formed in the second contact area 213
The second contact 253 can respectively as drain electrode and source electrode.As shown in fig. 7, the drain current between source electrode and drain electrode includes：
The electric current (i.e. vertical segment) and flow path of shortest path flowing the side electricity longer compared with shortest path between source electrode and drain electrode
It flows (sidewall current, the i.e. curve of both sides).Therefore, the one of active component 20 effective channel width W ' is in embodiment
The summation (being denoted as W+2 × W2) of approximately equal to width W and double-width W2.Side electric current has longer effective channel length, i.e.,
More than Lg, generated without the problem of bimodal leakage current.In one embodiment, when diffusion zone DIF includes the first of high concentration leading
Electric state dopant such as P+ then forms P+ encirclement grids in 22 outside of lightly doped region and reaches field insulation (field
isolation).According to embodiment, the parasitic leakage current (parasitic leakage) of two adjacent transistors can effectively be expanded
Region DIF is dissipated to be inhibited, and this inhibition can be because the space (S1/S2) between two active components (such as NMOS) be with sufficient concentrations of
P-type is adulterated (P+) and is reached.Fig. 8 is the I that a mosfet transistor of the embodiment of the present invention is laid outD-VGCharacteristic curve.Fig. 8 is clear
Chu is displayed without bimodal leakage current and generates, and empirical value is overlapped with the simulation curve ideal of theoretical model.Furthermore when Vg is low
Extremely low leakage current value is only observed when 0.7V.
According to above-mentioned, using have the semiconductor element of the active component of embodiment be there are several characteristics, such as：(1) do not have
There is the diffusion zone DIF of separation (no STI is present in the active area of element)；(2) using conductive guard bar structure (such as polysilicon gate
Pole) 201 define passage length and channel width in itself；(3) lightly doped region 22 (such as N-) and doped region 22 (such as N+) be (i.e.
First contact area 211, the second contact area 213 and gate contact portion 215) it is to completely cut off in each area of grid；And (4)
Isolation distance between conductive guard bar structure 201 can reach good field insulation with P+ impurities.Compared to as shown in Figure 1
Semiconductor element conventional in layout, embodiment semiconductor element layout (as shown in Figure 4) have many advantages.For example, phase
Due to there is no shallow trench isolation (STI), the design of embodiment can in space (S1/S2) between adjacent active component 20
Make semiconductor element altogether dispense in any STI edge effects (such as bimodal subcritical drain current, breakdown voltage decline, it is different
The difference etc. of STI layouts).Furthermore due to the special configuration of the active component of embodiment 20, without such as traditional diffusion zone
The presence of mode is overlapped and extended between DIF and polysilicon gate, therefore the distance between active component 20 is reduced again.
The active component of embodiment can be applied to high pressure (HV) semiconductor element or low pressure (LV) semiconductor element.It is below
Illustrate feasible one of which design rule among a high-voltage semiconductor element or a low-voltage semiconductor element.But it carries below
The relevant parameter numerical value gone out is merely illustration and is used, not limiting the range to be protected of the invention.
Fig. 4 is please referred to, the layout of a low-voltage semiconductor element in an embodiment can be represented.For operated at 3V one
For the element of nand flash memory, maximum bias needs about in 3.8V or so.It is the low-voltage semiconductor for proposing to operate at 3V below
One group of relevant parameter of element explains.In one embodiment, to the low-voltage semiconductor element operated at 3V, passage length Lg
Reducible 0.3 μm to about 0.4 μm with the maximum bias 3.8V of support.The minimum widith W of first area 201a and second area 201b is about
0.2 μm, one of the first contact area 211 and the second contact area 213 (i.e. each drain/source) have about 0.1 μm
× 0.1 μm of area.About 0.1 μm to about 0.15 μm of the minimum widith W2 in the first shield portion 2011 and the second shield portion 2012.It is adjacent to have
The space (assuming that S1=S2=S) of source element 20 is, for example, about 0.18 μm to about 0.28 μm of distance.Furthermore active component 20 it
About 0.68 μm of spacing (pitch) DP.Since the active component space D P of embodiment reaches about 0.68 μm, meet nand flash memory
Page buffer circuit design (page buffer circuit design).
Fig. 9 is that the page buffer circuit of the nand flash memory with reed bit line cell (BL Clamp Devices) designs.
In the design of nand flash memory page buffer, BLC, BLK and BLC_I element (and element of three circle favored areas) are critically important.
These elements need tight critical voltage (Vt) distribution can accurately control bit line bias in sensing.Furthermore due to being permitted
Multi-page buffer circuit exists, it is therefore desirable to one can the placement rule of tightly configured element exist.And the element of embodiment is special
Do not meet this purpose, has at least the following advantages：Including (1) due to regular regardless of diffusion zone, embodiment
Layout can reach closer configuration spacing than conventional in layout；(2) tight critical voltage (Vt) distribution and no edges STI are drawn
The problem of rising and variation.
Figure 10 is the layout for being painted a high-voltage semiconductor element in an embodiment.It please refers to above-mentioned about the active of embodiment
The associated components description of contents of element.And identical element is to continue to use identical label to clearly appear from embodiment in Figure 10 and Fig. 4.
Its details (such as the lightly doped region 22 (N-) in polysilicon gate, in the 201a/ second areas 201b of first area
One contact area, 211/ second contact area 213) it has described as before, details are not described herein.Low pressure and high-voltage semiconductor element
Design primary difference is that, the first contact area 211 and the second contact area 213 are respectively in high-voltage semiconductor element
The distance in one shield portion 2011 and the second shield portion 2012 must increase, to support operation with high pressure.Due to contact area (211/213/
215) N+ is carried out after contact etching, and heavy doping contact area (211/213/215) can be limited in the contact of small area
Region.
It is the one of which design rule of the high voltage device for the nand flash memory for illustrating to operate at 30V below.But below
The relevant parameter numerical value of proposition is merely illustration and is used, and not limits protection domain and is used.As shown in Figure 10, the one of an embodiment
In high-voltage semiconductor element, reducible 1.2 μm to about 2 μm of passage length Lg is to support input operating range 30V.One embodiment
In, arrive polysilicon gate (i.e. the first shield portion from contact area (i.e. N+, the first contact area 211 and the second contact area 213)
2011 and the second shield portion 2012) minimum range be to be denoted as doffset, distance doffsetIt is about 0.5 μm to about 1 μm sufficient to provide
Enough N+ drain bias (N+drain offset), thus it is caused to reduce GIDL (gate induced drain leakage)
Collapse.In one embodiment, distance doffset is about 0.8 μm.Furthermore in an embodiment, the first contact area 211 and/or second
Contact area 213 one of them (i.e. each drain/source) has the area of 0.1 μm of about 0.1 μ m.In one embodiment, first
About 0.2 μm of the minimum widith W2 in shield portion 2011 and the second shield portion 2012.Therefore, to the high-voltage semiconductor element of an embodiment and
Speech, distance doffsetThe relationship of (about 0.5 μm to 1 μm) and width W2 (about 0.2 μm) is represented by 2.5 × W2≤doffset≤5×
W2.In one embodiment, about 2.1 μm of minimal channel width W '.Furthermore the space of neighboring active element 20 (there is p-type doping to reach
Insulation) (assuming that S1=S2=S) be with about 1 μm of minimum range.
Although being with P-type conduction state and lightly doped region 22 in above-described embodiment with the first trap with N- conductive states,
The present invention is not limited thereto.To a PMOS techniques, as long as also can be with the application of the invention, the doping conductive state of reversion trap and knot be
It can.Such as the p-type trap and N-type lightly doped region 22 of NMOS elements, it is substituted by N-type trap and p-type lightly doped district in PMOS elements
Domain.Therefore, multiple NMOS elements of a shared p-type trap, and multiple PMOS elements of a shared N-type trap are may include in a CMOS.
Figure 11 is the layout for the applicable CMOS including multiple active components of one of which for being painted one embodiment of the invention.To large size
One CMOS layout designs of element, can be by multiple PMOS elements of multiple NMOS elements of a shared p-type trap and a shared N-type trap
Separate, as shown in figure 11.
Furthermore the active component of embodiment also can easily form silicon-on-insulator (SOI, the silicon- in thin main body
On-insulation) on wafer.
(DIF isolation) is isolated in diffusion zone can be in etching polysilicon (Self-aligned etching) to form conductive guardrail
It is made when structure 201, therefore, space (S1/S2) can be further reduced.Due to there is no trap to detach (well isolation)
Consider, it may be possible to design N/P MOSFET so that layout optimization in adjacent domain.Furthermore contact (body due to lacking body
Contact)-and belong to buoyant body (floating-body) MOSFET.
<Related experiment, mould fitted results>
Many related experiments and emulation (such as Computer Aided Design ＆ Imitation software Technology Computer
Aided Design, " TCAD ") it is for observing embodiment layout designs as a result, being to propose that wherein several proofs are implemented below
Example layout designs have excellent effect (such as between active component with good field insulation, the denier of no STI transistors
Drain current etc.).Figure 12 A- Figure 12 D are painted the standing without STI transistors of the embodiment according to TCAD simulated experiments respectively
Body figure and sectional view along YZ- planes, XZ- planes and XY-plane.It is said referring to the content of Fig. 4 and aforementioned relevant parameter
It is bright.In TCAD simulated experiments, two adjacent active components are represented with " Gate 1 " and " Gate 2 ", and relevant parameter includes：GOX
(gate oxide)=7nm, SPR=60nm, Lg (passage length)=0.4 μm, W1=0.2 μm, W2=0.1 μm, diffused contact
(i.e. N+, the first contact area 211 and the second contact area 213)=0.1 μm of 0.1 μ m, p-type trap to active region (AA) away from
From=0.5 μm, heavy dopant concentration (HDD)=1 × 1020cm-3, concentration (LDD)=5 × 10 is lightly doped18cm-3, N+ grid dopings are dense
Degree=1 × 1020cm-3, p-type trap doping concentration=6 × 1017cm-3And DP=0.68 μm of the spacing (pitch) of active component.
Figure 13 A are painted the I without STI transistors of embodiment in TCAD simulated experimentsD-VGCharacteristic curve.Wherein, it is to apply
Voltage Vg1 and Vg2 is in embodiment without STI transistors " Gate 1 " and " Gate2 " element.In Figure 13 A, two TID-VGCharacteristic is bent
Line is to be obtained respectively by applying the voltage of the Vg2 of the Vg1 and 3.8V of 0V.According to Figure 13 A's as a result, variation be applied to mark
The bias of the element of " Gate 2 " can't change the I of the element of mark " Gate 1 "D-VGCharacteristic curve, therefore provable implementation
Example provides good field insulation.Figure 13 B be in " Gate 1 " and " Gate 2 " element apply Vg1=0.5V, Vg2=3.8V and
The current density of Vds=0.1V emulates schematic diagram.From the emulation of the current density of Figure 13 B it is found that drain current is largely along most
Short-range path flowing, therefore effective channel width can also be considered as equal to W1.
Figure 14 A are painted the I without STI transistors of embodiment in TCAD simulated experimentsD-VGCharacteristic curve, wherein being to change not
It it is 0.1 μm, 0.15 μm and 0.2 μm with width W2.In Figure 14 A, the relevant parameter of no STI transistors includes：Vds=0.1V, Vg2
=3.8V, W1=0.2 μm, Lg=0.4 μm and p-type trap doping concentration=6 × 1017cm-3.Figure 14 B are painted in TCAD simulated experiments
The I without STI transistors of embodimentD-VGCharacteristic curve, wherein be the different passage length Lg of variation being 0.25 μm, 0.3 μm and 0.4
μm.In Figure 14 B, the relevant parameters of no STI transistors includes Vds=0.1V, Vg2=3.8V, W1=0.2 μm, W2=0.1 μm,
With p-type trap doping concentration=6 × 1017cm-3.Figure 14 A and Figure 14 B's the result is that pointing out narrow passage (narrow-width) effect
With short channel (short-channel) effect be mirror to.Furthermore work as W2=0.2um, the space length between active component can
To reduce to only 0.08 μm, and the leakage current increasing degree that can be aroused attention also is not observed.
Figure 15 A be TCAD simulated experiments in, an embodiment without STI transistors along the sectional view of XY-plane, wherein being
Mark applies voltage on the contact area of active component.Figure 15 B- Figure 15 D be painted embodiment in TCAD simulated experiments without STI
The ID-VG characteristic curves of transistor, the wherein Vg2=0V and Vd1=0.1V of Figure 15 B, the Vg2=0V and Vd1=of Figure 15 C
The Vg2=3.8V and Vd1=3.8V of Vg2=3.8V and Vd1=0.1V and Figure 15 E of 3.8V, Figure 15 D.Schemed according to Figure 15 B-
The simulation experiment result of 15D is shown, no matter bias condition, transistor " Gate-2 " maintains atomic small drain current, table
It is shown with excellent field insulation effect.
Figure 16 be painted embodiment in TCAD simulated experiments without the I-Vd1 characteristic curves in STI transistors, wherein Vg2=
The drain current of 3.8V and Vg1=3.8V, and Id1 curves represent transistor " Gate-1 ", Id2 curves represent transistor " Gate-
2 " drain current and Ip-well curves represent the electric current of p-type trap.It is shown according to the simulation experiment result of Figure 16, works as Vd1
When increase, p-type trap electric current also rises therewith.The drain current Id2 of even if when Vd1 increases to 8V, transistor " Gate-2 "
It still maintains infinitely small.
In conclusion in the semiconductor element of the active component of Application Example, each active component is conductive using one
Guard bar structure (such as polysilicon gate) defines passage length and width.The semiconductor element of embodiment may include NMOS, PMOS
Or CMOS.To NMOS, N+ knots are to be surrounded by conductive guard bar structure (such as polysilicon gate), therefore make active component (no STI) can
The self-isolation (self-isolated) by conductive guard bar structure (such as polysilicon gate).Furthermore the area on the outside of conductive guard bar structure
It domain (i.e. diffusion zone DIF) can be with doped p-type impurity to reach field insulation.Semiconductor layout's design of embodiment can make partly to lead
Volume elements part is altogether dispensed in any STI edge effects, such as bimodal subcritical drain current, breakdown voltage decline, difference STI layouts
Difference etc., and can successfully solve the problems, such as that conventional semiconductors element can suffer from STI edge effects.Furthermore due to reality
The active component of example is applied that the presence of mode is not overlapped and extended between such as traditional diffusion zone DIF and polysilicon gate, because
The setting spacing (pitch) of this active component is further reduced.In addition, the result of simulated experiment also demonstrates embodiment
The semiconductor element leakage current amplification that can reach the insulation of good field and can not arouse attention.
In conclusion although the present invention has been disclosed by way of example above, it is not intended to limit the present invention..Institute of the present invention
Belong in technical field and have usually intellectual, without departing from the spirit and scope of the present invention, when various changes and profit can be made
Decorations.Therefore, subject to protection scope of the present invention ought be defined depending on appended claims range.
Claims (9)
1. a kind of semiconductor element, including：
One substrate；
One first trap has one first conductive state and is extended downwardly from a surface of the substrate；
One diffusion zone adulterates the impurity of first conductive state and is extended downwardly from a surface of first trap；
Multiple active components are formed in the diffusion zone, and these active components are arranged apartly,
Wherein these active components are electrically insulated from by the diffusion zone, and one of these active components include：
One conductive guard bar structure is formed on the diffusion zone；With
One lightly doped region has one second conductive state, and the lightly doped region extends downwardly simultaneously from a surface of the diffusion zone
It is correspondingly located within the conduction guard bar structure, wherein the area of isolation between these adjacent active components is by this
These conductive guard bar structures of a little neighboring active elements are defined.
2. semiconductor element according to claim 1, wherein the conduction guard bar structure include：
One middle part (middle portion), the wherein middle part are the grids as the active component, and the middle part
There is a channel width (channel width, W ') along a first direction and there is a passage length along a second direction
(channel length, Lg)；
One first shield portion (first guarding portion) connects the side of the middle part to define and is located at the diffusion zone
A first area (first region), the wherein first area is by the first shield portion and the middle part around forming；With
One second shield portion (second guarding portion), it is opposite with the first shield portion and connect the another of the middle part
Side is located at a second area (second region) for the diffusion zone to define, and the wherein second area second is protected by this
Portion and the middle part around forming, wherein the first area and the second area be located in the lightly doped region, and this first
Region and the second area are the distances for being spaced the passage length.
3. semiconductor element according to claim 2, wherein one of these active components further include：
One first contact area (first contact region) has second conductive state and is formed in the conduction guardrail knot
In the first area of structure, and first contact area be with the first shield portion and the middle part apart；
One second contact area (second contact region) has second conductive state and is formed in the conduction guardrail knot
In the second area of structure, and second contact area be with the second shield portion and the middle part apart；With
One first contact (first contact) is formed in first contact area and one second contact (second
Contact) it is formed in second contact area.
4. semiconductor element according to claim 1, wherein when the semiconductor element is a low pressure (LV) element, it is adjacent
These active components between a spacing (space, S) be in the range of 0.18 μm to0.28 μm；When the semiconductor element
For a high pressure (HV) element when, the spacing (space, S) between these adjacent active components is in 0.8 μm of 1.2 μm of to
In the range of.
5. semiconductor element according to claim 1, wherein between these adjacent active components a spacing (space,
S it is no shallow trench isolation (Shallow trench isolation, STI) at).
6. an active component is formed in the diffusion zone with one first conductive state at a substrate, the active component packet
It includes：
One conductive guard bar structure (conductive guarding structure), including：
One middle part (middle portion)；
One first shield portion (first guarding portion) connects the side of the middle part to define and is located at the diffusion zone
A first area (first region), the wherein first area is by the first shield portion and the middle part around forming；With
One second shield portion (second guarding portion), it is opposite with the first shield portion and connect the another of the middle part
Side is located at a second area (second region) for the diffusion zone to define, and the wherein second area second is protected by this
Portion and the middle part, which surround, to be formed；
One first contact area (first contact region) has one second conductive state and is formed in the conduction guardrail knot
In the first area of structure, and first contact area be with the first shield portion and the middle part apart；With
One second contact area (second contact region) has second conductive state and is formed in the conduction guardrail knot
In the second area of structure, and second contact area be with the second shield portion and the middle part apart.
7. active component according to claim 6, the wherein middle part are the grids as the active component, and in this
Between portion along a first direction have a channel width (channel width, W ') and along a second direction have a channel
Length (channel length, Lg), and the first area and the second area are the distances for being spaced the passage length；And
The active component further includes：
One lightly doped region (light doping region) has second conductive state, and the lightly doped region is from the diffusion
One surface in region extends downwardly and is located within the corresponding conduction guard bar structure, and wherein first area and the second area is
In the lightly doped region；
One first contact (first contact) is formed in first contact area and one second contact (second
Contact it) is formed in second contact area,
The neighboring area (peripheral area) for wherein surrounding the active component is the expansion of heavy doping first conductive state
Dissipate region and without shallow trench isolation (Shallow trench isolation, STI).
8. active component according to claim 6, the wherein first area and the second area are each along a first direction
Respectively there is a width W2 along the first direction with a width W and the first shield portion and the second shield portion, and the active component
An effective channel width (effective channel width) be W+2 × W2.
9. active component according to claim 6 is a high pressure (HV) element, wherein the first shield portion and the second shield portion
Respectively there is a width W2, first contact area and second contact area respectively with the first shield portion and each phase in the second shield portion
Every a distance doffset, wherein 2.5 × W2≤doffset≤5×W2。
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| US7186622B2 (en) * | 2004-07-15 | 2007-03-06 | Infineon Technologies Ag | Formation of active area using semiconductor growth process without STI integration |
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