CN105655255A - 一种应变锗器件的制备方法 - Google Patents
一种应变锗器件的制备方法 Download PDFInfo
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- 229910052732 germanium Inorganic materials 0.000 title claims abstract description 38
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 title claims abstract description 36
- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 20
- 238000002347 injection Methods 0.000 claims abstract description 11
- 239000007924 injection Substances 0.000 claims abstract description 11
- 230000006698 induction Effects 0.000 claims abstract description 10
- 238000000137 annealing Methods 0.000 claims abstract description 9
- 238000005468 ion implantation Methods 0.000 claims description 15
- 238000002513 implantation Methods 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000002425 crystallisation Methods 0.000 abstract description 4
- 230000008025 crystallization Effects 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000000348 solid-phase epitaxy Methods 0.000 abstract 2
- 238000005280 amorphization Methods 0.000 abstract 1
- 239000000203 mixture Substances 0.000 abstract 1
- 239000007787 solid Substances 0.000 description 10
- 238000000407 epitaxy Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 4
- 230000001939 inductive effect Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明公开了一种应变锗器件的制备方法,属于半导体器件制造工艺领域。该制备方法通过离子注入对源漏区域表面进行预非晶化,并在源漏区域中注入张应变诱导元素,然后对衬底进行退火,使非晶区域固相外延再结晶。本发明采用固相外延方法可以抑制应变诱导原子的扩散,使其集中分布在表面,从而提高源漏区域中张应变诱导元素的组分,使沟道中的应力增加,并且与现有工艺兼容,可以用于应变锗MOS器件的工艺基础。
Description
技术领域
本发明涉及一种应变锗器件的制备方法,属于半导体器件制造工艺领域。
背景技术
随着器件尺寸不断缩小,硅基器件中载流子迁移率退化问题日益严重,需要探索新材料、新结构以及新工艺来提高器件性能。锗材料由于具备较高的载流子迁移率而受到广泛关注。为了进一步提高锗基MOS器件沟道中载流子的迁移率,可以在源漏区域采用与锗晶格常数不同的材料,从而在沟道中引入应力。在锗基NMOS器件中,通过在源漏区域注入晶格常数小于锗的元素,可以在沟道中引入单轴张应力,从而提高沟道中电子的迁移率。
但传统离子注入方法在沟道中引入的应变大小,受杂质在锗中固溶度的限制,尤其是碳,在锗中固溶度极低,在退火过程中容易发生析出,因而获得的替位式碳原子含量较低,引入的应变也较小,从而影响了器件性能的提升。
发明内容
为了解决以上问题,本发明提出一种应变锗器件的制备方法,该方法可提高源漏区域中张应变诱导元素的组分,使沟道中的应力增加,并且与现有工艺兼容,可以用于应变锗MOS器件的工艺基础。
本发明的具体技术方案如下:
1.一种应变锗器件的制备方法,其具体包括如下步骤:
1)选用锗基衬底,衬底表面形成栅极结构;
2)对源漏区域进行第一次离子注入,形成非晶层;
3)对源漏区域进行第二次离子注入,引入张应变诱导元素,第二次注入深度小于第一次离子注入形成的非晶层厚度;
4)在源漏掺杂之前或之后对锗基衬底进行退火,使非晶区域转化为单晶;
5)进行后续工艺,完成MOS器件的制备。
针对NMOS制备,所述锗基衬底为P型,衬底可以为锗衬底、硅基外延锗衬底或锗覆盖绝缘衬底,但不局限于上述材料,也可以是任何表面含有锗外延层的衬底。
所述栅极结构包含栅介质和栅电极。
所述第一次离子注入,注入元素为Ge元素,注入剂量为1×1013cm-2~1×1016cm-2,注入能量应根据所需非晶层厚度决定。
所述第二次离子注入,注入元素可以为C、Si等张应变诱导元素,注入剂量为1×1013cm-2~5×1016cm-2,注入能量与沟道中应变层厚度相关,注入深度应小于第一次离子注入形成的非晶层厚度。
其中,退火温度为300~700℃,退火时间应根据非晶层厚度以及固相外延的结晶速率决定。
本发明优点如下:
本发明首先通过离子注入对源漏区域表面进行预非晶化,并在源漏区域中注入张应变诱导元素,然后对衬底进行退火,使非晶区域固相外延再结晶。固相外延方法可以抑制应变诱导原子的扩散,使其集中分布在表面,从而提高源漏区域中张应变诱导元素的组分,使沟道中的应力增加。
本发明通过结合离子注入与固相外延的方法工艺简单,易于操作,可以与现有CMOS工艺兼容。
附图说明
图1~图5为采用本发明提出的应变锗器件的制备方法具体实施例的流程图。
其中:1—锗衬底;2—栅介质;3—栅电极;4—非晶层;5—C注入区域;6-GeC合金;7—源漏;8—侧墙;9—金属互连线;10—隔离。
具体实施方式
该方法通过结合离子注入与固相外延的方法,首先通过离子注入对锗基衬底进行非晶化,然后注入应变诱导元素,最终对衬底进行退火,从而实现固相外延,使非晶区域转化为单晶。该方法可以提高应变诱导元素的组分,从而使沟道中的应力增加,并且该方法工艺简单,易于操作,可以与现有CMOS工艺兼容。
以锗衬底为例,本发明提出的应变锗器件制备方法如下:
步骤1.提供锗衬底1,锗衬底1表面形成有栅极结构,栅极结构包括栅介质2和栅电极3,如图1所示。
步骤2.对源漏区域进行第一次离子注入,如图2所示,注入元素为Ge,注入剂量为1×1014cm-2,注入能量为40keV,形成非晶层4,非晶层4厚度约为40nm。
步骤3.对源漏区域进行第二次离子注入,注入元素为C,注入剂量为1×1015cm-2,注入能量为7keV,形成C注入区域5,C注入深度约为30nm,如图3所示。
步骤4.对锗衬底1进行退火,退火温度为500℃,退火时间为300s,完成GeC合金6的固相外延,如图4所示。
步骤5.进行后续工艺,完成锗基张应变NMOS晶体管的制备,形成源漏7、侧墙8、金属互连线9及其与器件层之间的隔离10,如图5所示。
本发明对锗衬底进行退火可以在源漏掺杂之前或之后进行,退火时间应根据非晶层厚度以及固相外延的结晶速率决定。
上面描述的实施例并非用于限定本发明,任何本领域的技术人员,在不脱离本发明的精神和范围内,都可利用上述方法和技术内容对本发明技术方案作出许多可能的修改和润饰。因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何等同变化或修饰,均仍属于本发明技术方案的涵盖范围。
Claims (5)
1.一种应变锗器件的制备方法,其特征在于,具体包括如下步骤:
1)选用锗基衬底,衬底表面形成栅极结构,栅极结构两侧形成有侧墙;
2)对源漏区域进行第一次离子注入,形成非晶层;
3)对源漏区域进行第二次离子注入,引入张应变诱导元素,第二次注入深度小于第一次离子注入形成的非晶层厚度;
4)在源漏掺杂之前或之后对锗基衬底进行退火,使非晶区域转化为单晶;
5)进行后续工艺,完成MOS器件的制备。
2.如权利要求1所述的制备方法,其特征在于,所述锗基衬底为锗衬底、硅基外延锗衬底或锗覆盖绝缘衬底。
3.如权利要求1所述的制备方法,其特征在于,步骤2)中,所述第一次离子注入的注入元素为Ge元素,注入剂量为1×1013cm-2~1×1016cm-2。
4.如权利要求1所述的制备方法,其特征在于,步骤3)中,所述第二次离子注入,注入元素为C或Si,注入剂量为1×1013cm-2~5×1016cm-2。
5.如权利要求1所述的制备方法,其特征在于,步骤4)中,退火温度为300~700℃。
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CN108257917A (zh) * | 2016-12-28 | 2018-07-06 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09307101A (ja) * | 1996-05-15 | 1997-11-28 | Toyota Central Res & Dev Lab Inc | 半導体装置およびその製造方法 |
WO2007112432A3 (en) * | 2006-03-28 | 2009-03-26 | Ibm | Epitaxy of silicon-carbon substitutional solid solutions by ultra-fast annealing of amorphous material |
TW200945448A (en) * | 2008-04-21 | 2009-11-01 | United Microelectronics Corp | Semiconductor device and method for manufacturing the same |
CN101577229A (zh) * | 2008-05-06 | 2009-11-11 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
CN102931222A (zh) * | 2011-08-08 | 2013-02-13 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09307101A (ja) * | 1996-05-15 | 1997-11-28 | Toyota Central Res & Dev Lab Inc | 半導体装置およびその製造方法 |
WO2007112432A3 (en) * | 2006-03-28 | 2009-03-26 | Ibm | Epitaxy of silicon-carbon substitutional solid solutions by ultra-fast annealing of amorphous material |
TW200945448A (en) * | 2008-04-21 | 2009-11-01 | United Microelectronics Corp | Semiconductor device and method for manufacturing the same |
CN101577229A (zh) * | 2008-05-06 | 2009-11-11 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
CN102931222A (zh) * | 2011-08-08 | 2013-02-13 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN108257917A (zh) * | 2016-12-28 | 2018-07-06 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
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