CN105652182A - Circuit board fault positioning system and circuit board fault positioning method based on circuit network and graph search - Google Patents

Abstract

The invention discloses a circuit board fault positioning system based on a circuit network and graph search. The circuit board fault positioning system comprises the components of a testing node attribute acquiring module which is used for acquiring attribute information of a testing node, wherein the attribute information comprises circuit interface attribute and testing execution attribute; a routing file acquiring module which is used for acquiring a routing file that is used for describing a line relationship between the channel of a testing instrument and the testing node; and an optimal node selecting module which is used for screening a manual testing node according to fault sensitivity and a fault isolation parameter; a testing logic generating module which is used for generating the testing logic of the node in an optimal node set obtained through screening based on the testing node attribute information and the routing file; and a testing result output module which is used for testing the selected testing point based on the obtained testing logic and furthermore finishes fault positioning of the circuit board.

Description

A kind of based on circuit network and circuit card fault location system and the method for scheming search

Technical field

The invention belongs to circuit card test and diagnostic technical field, in particular to a kind of based on the circuit card localization of fault method of circuit network and figure search.

Background technology

Circuit card needs the data of centering intermediate node to carry out measuring collection when localization of fault, and carries out the judgement of circuit state according to measuring result and analyze the Test Strategy inferring next step; At present in circuit card localization of fault, depending on the corresponding test node information of artificial input and determine the testing sequence of node, workload is big, level of automation is not high and causes that the quantity of test node and distribution are optimized not, topology logicality is not strong.

In order to improve the efficiency that circuit card test and diagnostic TP develops, on the basis of existing TP development approach, it is proposed to develop based on the circuit card localization of fault method of circuit network and figure search then very necessary.

Summary of the invention

It is an object of the present invention to solve above-mentioned technical problem, the present invention provides a kind of based on circuit network and circuit card fault location system and the method for scheming search.

In order to realize above-mentioned purpose, the present invention provides a kind of based on the circuit card fault location system of circuit network and figure search, and described system comprises:

Test node attribute acquisition module, for obtaining the attribute information of test node, described attribute information comprises: circuit interface attribute and test execution attribute;

Route file acquisition module, for obtaining route file, the line relation of described route file for describing between the passage of testing tool and test node;

Optimum sensor selection problem module, for manual test node being screened according to fault susceptibility and fault isolation degree parameter, and then select some the optimum test node set of node composition, wherein, described fault isolation degree characterization test point is to the separating capacity of fault;

Test logic generation module, for screening the test logic of the optimum node set interior joint obtained, or based on the test logic of test node attribute information and the automatic test node of route file generated based on test node attribute information and route file generated; Wherein said test logic relation comprises: sequentially, select, circulation or redirect;

Test result output module, for the test point selected being tested based on the test logic obtained, and then the localization of fault of completing circuit plate.

Optionally, said system also comprises:

Configuration module, for inputting the testing attribute of the test node of the circuit board under test needing configuration, described testing attribute comprises: circuit interface attribute and test execution attribute;

Route file generating module, for the attribute information generation test node of the test node based on input and the route file of testing tool, wherein, the line relation of described route file for describing between the passage of testing tool and test node.

Optionally, said system also comprises:

Store and interface module, for store localization of fault result and for the interface with the testing and diagnosing knowledge based on intelligent algorithm;

Image management module, for completing the importing of the schematic diagram to institute's testing circuit board and PCB, editor, setup of attribute and preservation.

Further alternative, above-mentioned optimum sensor selection problem module comprises further:

First process submodule block, for calculating the difference degree factor of each test node to be selected, and sorts test node to be selected by order from big to small again according to the value obtaining the difference degree factor;

2nd process submodule block is empty for the optimum test node collection N* of initialize, and the set marking the test node to be selected after reordering is P={P0, P1,, Pi ... Pk}, the value of initialize parameter i is i=1 simultaneously, wherein the span of i is: i=1 ..., K, wherein, K is total number of node to be tested;

3rd process submodule block, for selecting node Pi from the set of test node to be selected, carries out fault classification calculating to the fault characteristic data set of this test node Pi;

And the calculation result according to all test sample books, calculate the fault isolation group of this test node PiWith fault isolation degree

Differentiate submodule block, for verifying the union isolation of the fault isolation group of set N* and test node PiWhether set up, if equation meets, then test node Pi is added into checking set N*, and drives and terminate submodule block; IfThen give up test node Pi and the value of parameters i is: i=i+1, restart the 3rd process submodule block and process; Otherwise, test Pi is added into checking set N*, opens the 3rd process submodule block;

Terminating submodule block, for judging that the optimum test node when selecting can distinguish all faults, then the screening process of optimum node set terminates.

Optionally, such scheme adopts the value obtaining the difference degree factor with the following method:

First, define the inter-object distance d of i-th test node jth class fault sample_ijFor:

Wherein, m, n=1,2 ..., N, m �� n; I=1,2 ..., K; J=1,2 ..., the implication of M, m and n is; N is sample number, and K is total number of node to be tested, and M is the total number of fault class, P_ij(m) and P_ijN () represents that i-th test point jth class fault is for the eigenwert of m and the n-th sample respectively;

The mean value Di of the inter-object distance of i-th test node M class is:

The mean value q of N number of sample of i-th test node jth class fault_ij:

The mean value D ' of the class spacing of M class of i-th test point_iFor:

Wherein, ��, ��=1,2 ..., M, �� �� ��; q_i��,q_i��Represent the mean value of �� of i-th test point and N number of sample of �� class respectively;

Then, based on above-mentioned parameter, the difference degree �� of definition test node i_iCalculation formula be:

��_i=(D '_i/D_i)��(min(R_bi)/max(R_wi))(5)

Wherein, min (R_bi) and max (R_wi) represent between the infima species of i-th test node sampled data discrete value in discrete value and maximum kind respectively.

Optionally, such scheme adopts the fault isolation degree obtaining test node Pi with the following method:

Candidate's test node after reordering is designated as P_i, M class fault pattern is designated as failure collection F={F₀,F₁,��,F_M-1, wherein F₀For non-failure conditions; Provide as follows:

1) if all fault samples are accurately identified under certain fault model F m in F, and be there is not the situation being misdiagnosed as Fm in any fault sample under all the other fault patterns, then specifies fault isolation group:It is a fault isolation group of test node Pi, and this failure collection only comprises an element Fm;

2) if the part fault sample in fault model F m is misdiagnosed as fault Fn, then remember that Fm and Fn belongs to a fault ambiguity group of test node Pi, and it be designated as:If the part sample in Fm is misdiagnosed as fault model F n and Fq, then remembers that Fm, Fn and Fq are a fault ambiguity group of test node Pi, it is designated asAnalogize successively;

Wherein m, n, q=0,1 in above definition ..., M-1; M �� n �� q;

Definition power set �� (F) represents fault set F={F0, F1 ..., FM-1}; AG^PiFor the set of all fault ambiguity group of test node Pi; IG^PiFor the set of all fault isolation groups of test node Pi;

Obtain according to above-mentioned definition:

Wherein, | | for getting element number in set, i.e. fault number;

Definition isolation, for test node Pi and M class fault pattern, the fault isolation degree of definition test node is:

Obviously,

K nearest neighbor algorithm is utilized to calculate the fault isolation degree of all test nodes.

In addition, present invention also offers a kind of based on the circuit card localization of fault method of circuit network and figure search, described method comprises:

Step 101) obtain test node attribute information, described testing attribute comprises: circuit interface attribute and test execution attribute;

Step 102) obtain route file, the line relation of described route file for describing between the passage of testing tool and test node;

Step 103) according to fault susceptibility and fault isolation degree parameter, manual test node is screened, and then select some the optimum test node set of node composition: wherein, described fault isolation degree characterization test point is to the separating capacity of fault;

Step 104) the test logic of optimum node set interior joint that obtains based on test node attribute information and the screening of route file generated, or based on the test logic of test node attribute information and the automatic test node of route file generated; Wherein said test logic comprises: described logic relation comprises: sequentially, select, circulation or redirect;

Step 105) based on the test logic obtained, test node is tested, and then the localization of fault of completing circuit plate.

Optionally, above-mentioned steps 101) also comprise before:

Input needs the testing attribute of the test node of the circuit board under test of configuration, and described testing attribute comprises: circuit interface attribute and test execution attribute;

Based on the attribute information generation test node of test node and the route file of testing tool of input, wherein, the line relation of described route file for describing between the passage of testing tool and test node.

Optionally, above-mentioned steps 103) comprise further:

Step 103-1) calculate the difference degree factor of each test node to be selected, and according to the value obtaining the difference degree factor by sequentially test node to be selected being sorted again from big to small;

Step 103-2) the optimum test node collection N* of initialize is empty, and the set marking the test node to be selected after reordering is P={P0, P1 ... Pk}, the value of initialize parameter i is i=1 simultaneously, and wherein the span of i is: i=1 ... K, wherein, K is total number of node to be tested;

Step 103-3) from the set of test node to be selected, select node Pi, the fault characteristic data set of this node Pi is carried out fault classification calculating;

And the calculation result according to all test sample books, calculate the fault isolation group of this test node PiWith fault isolation degree

Differentiate submodule block, for verifying the union isolation of the fault isolation group of set N* and test node PiWhether set up, if equation meets, then test node Pi is added into checking set N*, and proceeds to step 103-4); IfThen give up test node Pi and the value of parameters i is: i=i+1, proceeds to step 103-3); Otherwise, test Pi is added into checking set N*, proceeds to step 103-3);

Step 103-4) all faults can be distinguished when the optimum test node selected, then the screening process of optimum node set terminates.

Optionally, such scheme also adopts the value obtaining the difference degree factor with the following method:

Define the inter-object distance d of i-th test node jth class fault sample_ijFor:

Wherein, m, n=1,2 ..., N, m �� n; I=1,2 ..., K; J=1,2 ..., the implication of M, m and n for (m and n: be greater than 1 and for natural number); N is sample number, and K is the total number of test node, and M is the total number of fault class, P_ij(m),P_ijN () represents that i-th test point jth class fault is for the eigenwert of m and the n-th sample respectively;

The mean value Di of the inter-object distance of i-th test node M class is:

The mean value q of N number of sample of i-th test node jth class fault_ij:

The mean value D ' of the class spacing of M class of i-th test point_iFor:

Wherein, ��, ��=1,2 ..., M, �� �� ��; q_i��,q_i��Represent the mean value of �� of i-th test point and N number of sample of �� class respectively;

The difference degree �� of definition test node i_iFor:

��_i=(D '_i/D_i)��(min(R_bi)/max(R_wi))(5)

Wherein, min (R_bi) and max (R_wi) represent between the infima species of i-th test node sampled data discrete value in discrete value and maximum kind respectively.

Compared with prior art, the useful effect of the present invention is:

The present invention is on the basis that existing TP develops software, and emphasis improves ease for use and the development efficiency of TP exploitation. Mainly solve the problem of following each side: TP writes, debugs and test not directly perceived; It is big that TP writes workload; TP reusability is poor; TP amendment is comparatively loaded down with trivial details; TP off-line debug function is weak; Between TP and intelligence diagnosis algorithm mutually independently.

Accompanying drawing explanation

Fig. 1 is the schematic flow sheet of method provided by the invention;

Fig. 2 is the basic workflow diagram of technical solution of the present invention.

Embodiment

Below in conjunction with the drawings and specific embodiments, the present invention will be described in detail.

The present invention provides a kind of based on the circuit card fault location system of circuit network and figure search, and described system comprises:

Test node attribute acquisition module, for obtaining the attribute information of test node, described attribute information comprises: circuit interface attribute and test execution attribute;

Route file acquisition module, for obtaining route file, the line relation of described route file for describing between the passage of testing tool and test node;

Optimum sensor selection problem module, for manual test node being screened according to fault susceptibility and fault isolation degree parameter, and then select some the optimum test node set of node composition, wherein, described fault isolation degree characterization test point is to the separating capacity of fault;

Test logic generation module, for screening the test logic of the optimum node set interior joint obtained, or based on the test logic of test node attribute information and the automatic test node of route file generated based on test node attribute information and route file generated; Wherein said test logic comprises: described logic relation comprises: sequentially, select, circulation or redirect;

Test result output module, for the test point selected being tested based on the test logic obtained, and then the localization of fault of completing circuit plate.

Optionally, said system also comprises:

Configuration module, for inputting the testing attribute of the test node of the circuit board under test needing configuration, described testing attribute comprises: circuit interface attribute and test execution attribute;

Route file generating module, for the attribute information generation test node of the test node based on input and the route file of testing tool, wherein, the line relation of described route file for describing between the passage of testing tool and test node.

Optionally, said system also comprises:

Store and interface module, for store localization of fault result and for the interface with the testing and diagnosing knowledge based on intelligent algorithm;

Image management module, for completing the importing of the schematic diagram to institute's testing circuit board and PCB, editor, setup of attribute and preservation.

Further alternative, above-mentioned optimum sensor selection problem module comprises further:

First process submodule block, for calculating the difference degree factor of each test node to be selected, and sorts test node to be selected by order from big to small again according to the value obtaining the difference degree factor;

2nd process submodule block is empty for the optimum test node collection N* of initialize, and the set marking the test node to be selected after reordering is P={P0, P1,, Pi ... Pk}, the value of initialize parameter i is i=1 simultaneously, wherein the span of i is: i=1 ..., K, wherein, K is total number of node to be tested;

3rd process submodule block, for selecting node Pi from the set of test node to be selected, carries out fault classification calculating to the fault characteristic data set of this test node Pi;

And the calculation result according to all test sample books, calculate the fault isolation group of this test node PiWith fault isolation degree

Differentiate submodule block, for verifying the union isolation of the fault isolation group of set N* and test node PiWhether set up, if equation meets, then test node Pi is added into checking set N*, and drives and terminate submodule block; IfThen give up test node Pi and the value of parameters i is: i=i+1, restart the 3rd process submodule block and process; Otherwise, test Pi is added into checking set N*, opens the 3rd process submodule block;

Terminating submodule block, for judging that the optimum test node when selecting can distinguish all faults, then the screening process of optimum node set terminates.

Optionally, such scheme adopts the value obtaining the difference degree factor with the following method:

First, define the inter-object distance d of i-th test node jth class fault sample_ijFor:

Wherein, m, n=1,2 ..., N, m �� n; I=1,2 ..., K; J=1,2 ..., the implication of M, m and n is; N is sample number, and K is total number of node to be tested, and M is the total number of fault class, P_ij(m) and P_ijN () represents that i-th test point jth class fault is for the eigenwert of m and the n-th sample respectively;

The mean value Di of the inter-object distance of i-th test node M class is:

The mean value q of N number of sample of i-th test node jth class fault_ij:

The mean value D ' of the class spacing of M class of i-th test point_iFor:

Wherein, ��, ��=1,2 ..., M, �� �� ��; q_i��,q_i��Represent the mean value of �� of i-th test point and N number of sample of �� class respectively;

Then, based on above-mentioned parameter, the difference degree �� of definition test node i_iCalculation formula be:

��_i=(D '_i/D_i)��(min(R_bi)/max(R_wi))(5)

Wherein, min (R_bi) and max (R_wi) represent between the infima species of i-th test node sampled data discrete value in discrete value and maximum kind respectively.

Optionally, such scheme adopts the fault isolation degree obtaining test node Pi with the following method:

Candidate's test node after reordering is designated as P_i, M class fault pattern is designated as failure collection F={F₀,F₁,��,F_M-1, wherein F₀For non-failure conditions; Provide as follows:

1) if all fault samples are accurately identified under certain fault model F m in F, and be there is not the situation being misdiagnosed as Fm in any fault sample under all the other fault patterns, then specifies fault isolation group:It is a fault isolation group of test node Pi, and this failure collection only comprises an element Fm;

2) if the part fault sample in fault model F m is misdiagnosed as fault Fn, then remember that Fm and Fn belongs to a fault ambiguity group of test node Pi, and it be designated as:If the part sample in Fm is misdiagnosed as fault model F n and Fq, then remembers that Fm, Fn and Fq are a fault ambiguity group of test node Pi, it is designated asAnalogize successively;

Wherein m, n, q=0,1 in above definition ..., M-1; M �� n �� q;

Definition power set �� (F) represents fault set F={F0, F1 ..., FM-1}; AG^PiFor the set of all fault ambiguity group of test node Pi; IG^PiFor the set of all fault isolation groups of test node Pi;

Obtain according to above-mentioned definition:

Wherein, | | for getting element number in set, i.e. fault number;

Definition isolation, for test node Pi and M class fault pattern, the fault isolation degree of definition test node is:

Obviously,

K nearest neighbor algorithm is utilized to calculate the fault isolation degree of all test nodes.

In addition, present invention also offers a kind of based on the circuit card localization of fault method of circuit network and figure search, described method comprises:

Step 101) obtain test node attribute information, described testing attribute comprises: circuit interface attribute and test execution attribute;

Step 102) obtain route file, the line relation of described route file for describing between the passage of testing tool and test node;

Step 103) according to fault susceptibility and fault isolation degree parameter, manual test node is screened, and then select some the optimum test node set of node composition: wherein, described fault isolation degree characterization test point is to the separating capacity of fault;

Step 104) the test logic of optimum node set interior joint that obtains based on test node attribute information and the screening of route file generated, or based on the test logic of test node attribute information and the automatic test node of route file generated; Wherein said test logic comprises: described logic relation comprises: sequentially, select, circulation or redirect;

Step 105) based on the test logic obtained, test node is tested, and then the localization of fault of completing circuit plate.

Optionally, above-mentioned steps 101) also comprise before:

Input needs the testing attribute of the test node of the circuit board under test of configuration, and described testing attribute comprises: circuit interface attribute and test execution attribute;

Based on the attribute information generation test node of test node and the route file of testing tool of input, wherein, the line relation of described route file for describing between the passage of testing tool and test node.

Optionally, above-mentioned steps 103) comprise further:

Step 103-1) calculate the difference degree factor of each test node to be selected, and according to the value obtaining the difference degree factor by sequentially test node to be selected being sorted again from big to small;

Step 103-2) the optimum test node collection N* of initialize is empty, and the set marking the test node to be selected after reordering is P={P0, P1 ... Pk}, the value of initialize parameter i is i=1 simultaneously, and wherein the span of i is: i=1 ... K, wherein, K is total number of node to be tested;

Step 103-3) from the set of test node to be selected, select node Pi, the fault characteristic data set of this node Pi is carried out fault classification calculating;

And the calculation result according to all test sample books, calculate the fault isolation group of this test node PiWith fault isolation degree

Differentiate submodule block, for verifying the union isolation of the fault isolation group of set N* and test node PiWhether set up, if equation meets, then test node Pi is added into checking set N*, and proceeds to step 103-4); IfThen give up test node Pi and the value of parameters i is: i=i+1, proceeds to step 103-3); Otherwise, test Pi is added into checking set N*, proceeds to step 103-3);

Step 103-4) all faults can be distinguished when the optimum test node selected, then the screening process of optimum node set terminates.

Optionally, such scheme also adopts the value obtaining the difference degree factor with the following method:

Define the inter-object distance d of i-th test node jth class fault sample_ijFor:

Wherein, m, n=1,2 ..., N, m �� n; I=1,2 ..., K; J=1,2 ..., the implication of M, m and n for (m and n: be greater than 1 and for natural number); N is sample number, and K is the total number of test node, and M is the total number of fault class, P_ij(m),P_ijN () represents that i-th test point jth class fault is for the eigenwert of m and the n-th sample respectively;

The mean value Di of the inter-object distance of i-th test node M class is:

The mean value q of N number of sample of i-th test node jth class fault_ij:

The mean value D ' of the class spacing of M class of i-th test point_iFor:

Wherein, ��, ��=1,2 ..., M, �� �� ��; q_i��,q_i��Represent the mean value of �� of i-th test point and N number of sample of �� class respectively;

The difference degree �� of definition test node i_iFor:

��_i=(D '_i/D_i)��(min(R_bi)/max(R_wi))(5)

Wherein, min (R_bi) and max (R_wi) represent between the infima species of i-th test node sampled data discrete value in discrete value and maximum kind respectively.

Embodiment

The general frame of the development approach that the present invention studies comprises: realize testing attribute configuration, circuitous pattern management, test node configuration, test logic realization, virtual online debugging, on-line debugging perform, data preserve and the function such as data interface.

The specific implementation principle of the present invention is as shown in Figure 1:

The technical scheme of the present invention achieves test configurations, schematic circuit management, test procedure (testprogram, hereinafter referred to as: TP) exploitation with perform, virtual with on-line debugging etc. function, and possess and the interface of the testing and diagnosing knowledge based on intelligent algorithm. As shown in Figure 2, idiographic flow step comprises the basic procedure of method provided by the invention:

1, testing attribute configuration

Testing attribute configuration mainly comprises the content of three aspects: circuit interface setup of attribute, test execution attribute configuration and test execution INTERFACE DESIGN.

Foregoing circuit interface attributes is mainly used in describing the interface information of circuit, and the interface packet of circuit is containing the testability etc. of the junctor node of interface of circuit and the internal test nodes of the interface of circuit; If test node belongs to junctor node, then adopt test automatically, otherwise adopt manually test; And in Joint Enterprise link to can not carrying out relevant information prompting and forbid that probe pen testing attribute configures by test node.

The configuration of the main completing circuit test execution type of test execution attribute, for generating test logical paradigm; Test execution type mainly comprises the function test based on fault tree and diagnostic test, diagnoses the types such as reasoning based on the intelligent of diagnostic knowledge.

Test execution INTERFACE DESIGN mainly completes the configuration to UI interface during test execution, completes according to existing TP development approach, and when emphasis has been test, the node of test data, step and circuit card schematic diagram/PCB is mutual.

2, circuitous pattern management

Circuitous pattern management belongs to the subfunction of exploitation configuration management, and the management mainly completing the schematic diagram to institute's testing circuit board, PCB etc. is such as functions such as importing, editor, setup of attribute and preservations.

Development approach possesses the compatibility to main flow circuit design method output files such as Protel, AltiumDesigner, the schematic circuit realizing being generated by aforesaid method by importing to mode carries out two editors, such as functions such as the drafting of schematic diagram, the drafting of components and parts graphical symbol and movements.

Development approach possesses independent schematic circuit and draws function, it may be achieved the generation of test node and configuration, it is achieved to graphic element such as the attribute configuration function of components and parts, line etc.

3, test node configuration

Test node configuration belongs to the subfunction of exploitation configuration management, mainly completes the setting of attribute and the route file generated of test node and testing tool of the circuit node to needing test. The attribute of test node mainly comprises detecting information description, test signal attribute, the testing tool attribute of this test node and tests logic attribute etc. Wherein, test logic attribute and define the logic relation (one in sequentially, selection, circulation and redirect) of this node with other nodes.

Test route file is mainly used in the line relation described between the passage of testing tool and test node, can be used for follow-up test logic and generates. By, in the attribute configuration of automatically testing node, extracting corresponding testing tool and channel attributes, automatically generate the route file based on XML format.

4, logic realization is tested

Test logic realization function belongs to the subfunction of exploitation configuration management, it is achieved the configuration management of test logic and logic preview function. Our department divides and comprises the acquisition of node attribute configuration information, route file acquisition, optimum test node set generation, logic generation and TP practical function.

Node attribute configuration information obtains, main extraction detecting information description, test signal attribute etc.; Wherein, detecting information describes and is used in the TP generated the information of current test node to be described; Test signal attribute is used for the signal scope to obtaining in the actual test of TP and judges.

Route file acquisition: read in based on the route file that node attribute configuration generates, for the software description relation set up between testing tool and test node, it is achieved to the automatic test of junctor node.

Optimum test node set generates: in order to reduce the quantity of manual test node, be optimized for the manual test node except junctor node, builds optimum test node set:

On the basis considering the index such as fault susceptibility and fault isolation degree, the research optimization algorithm that more comprehensively test point fault-detecting ability aggregative weighted is evaluated, reach and make minimum spacing between different faults fuzzy set big, and closely spaced object in maximum kind between same fault set.

Fault difference degree defines:

Regard each fault pattern as fault class, of all categories can distinguish open be because fault class be positioned at different response regions. Feature samples under all kinds of fault patterns that certain test point is corresponding, if the average inter-object distance of same class is more little, the average class spacing of inhomogeneity is more big, then this test point is more strong to the distinction of fault. The sample that in sample, the big and maximum inter-object distance of infima species spacing is little, corresponding test point is to the discrimination of fault strong (also can be called fault sensitive), and namely fault difference degree is big.

Define the inter-object distance d of i-th test point jth class fault sample_ijFor

Wherein, m, n=1,2 ..., N, m �� n; I=1,2 ..., K; J=1,2 ..., M. N is sample number, and K is number of checkpoints, and M is fault class number, P_ij(m),P_ijN () represents i-th test point jth class fault m and the n-th sample characteristics value respectively.

The mean value Di of the inter-object distance of i-th test point M class is

The mean value q of i-th test point jth N number of sample of class fault_ij

The mean value D ' of the class spacing of i-th test point M class_iFor

��, ��=1,2 in formula ..., M, �� �� ��; q_i��,q_i��Represent �� of i-th test point and the mean value of the �� N number of sample of class respectively.

Definition test point i difference degree ��_iFor

�� i=(D '_i/D_i)��(min(R_bi)/max(R_wi))(5)

min(R_bi) and max (R_wi) represent between the infima species of i-th test point sampled data discrete value in discrete value and maximum kind respectively.

��_iSize reflect the complexity that M class fault classified by i-th test point, ��_iMore big expression i-th test point is more responsive to fault feature, and the ability of difference fault is more strong. According to test point Sensitivity Factor test point to be selected reordered and can ensure optimum test point preferentially selected test point set, avoid test point to select blindness, reduce subsequent algorithm calculated amount.

Fault isolation degree defines:

Fault isolation degree characterization test point, to the separating capacity of fault, is an important judgement condition of the selected optimum test point set of the test node after reordering.

Candidate's test node after reordering is designated as P_i=(i=1,2 ..., K), M class fault pattern is designated as failure collection F={F0, F1 ..., FM-1}, wherein F0 is non-failure conditions. Provide as follows:

1) if all fault samples are accurately identified under certain fault model F m in F, and to any fault sample under all the other fault patterns, there is not the situation being misdiagnosed as Fm, then specify:It is a fault isolation group of test point Pi, this set only comprises an element Fm;

2) if the part fault sample in fault model F m is misdiagnosed as fault Fn, then remember that Fm and Fn belongs to a fault ambiguity group of node Pi, and it be designated as:If the part sample in Fm is misdiagnosed as fault model F n, Fq, then remembers that Fm, Fn, Fq are a fault ambiguity group of node Pi, it is designated asAnalogize successively.

More than in definition, m, n, q=0,1 ..., M-1; M �� n �� q.

Definition power set �� (F) represents fault set F={F0, F1 ..., FM-1}; AG^PiFor the set of all fault ambiguity group of test point Pi; IG^PiFor the set of all fault isolation groups of test point Pi. Obtain according to above-mentioned definition:

Wherein, | | for getting element in set (i.e. fault) number.

Definition isolation. For test point Pi (i=1,2 ..., K) and M class fault pattern, define its test point fault isolation degree

Obviously,

Utilize K nearest neighbour (K-nearest-neighbor, KNN) that the fault isolation degree of all test point can be calculated.

Test node optimizes algorithm flow figure as shown in Figure 1, is specially:

A. calculate each test point difference degree factor to be selected, and by order from big to small, test point is sorted again according to its value;

B. initialize optimum test point set N* be empty, and mark reorder after the set treating preferred test node be P={P0, P1 ..., Pk}, initialize i=1, i=1 ..., K;

C. select test point Pi, utilize KNN that this test point fault characteristic data set carries out fault and sort out calculating. Calculation result according to all test sample books, calculates this test point fault isolation groupWith fault isolation degree

D. the union isolation of checking set N* and test point Pi fault isolation groupWhether set up, if equation meets, then Pi is added into N*, goes to e; IfGive up Pi (i=i+1), go to c; Otherwise, Pi is added into N*, goes to c;

E. test point can isolate all faults, and algorithm terminates.

By above-mentioned algorithm, fault degree of difference, fault isolation degree, test point detection cost can be combined, and combine fault and the factors such as probability occur, construct optimum test node set.

Test logic generates and TP realizes: in Joint Enterprise, configured by the test logic attribute of each node; By the test node after optimization according to the logic attribute configured and testing sequence, genesis sequence, selection, circulation or redirect logic, further, construct the logic tree of the test node set based on optimum; Software generates four logic of class software blocks for above-mentioned logic relation, based on logic tree, sets up TP.

Realize the configuration of test logic by the test node number in schematic diagram being dragged to test logic configuration region, and relevant test logic discrimination condition such as cycle index, jump target etc. is arranged.

5, virtual online debugging

Virtual online debug function mainly realizes online simulation debug function during ATE off-line state. When virtual online is debugged, TP running status is completely identical with on-line debugging; Development approach provide single step, continuously, interval, breakpoint, the executive mode such as annotation, possess the control modes such as operation, stopping, time-out; The functions such as runnable interface possesses schematic diagram/PCB test node flicker, detecting information reads, test logical order display; Input relevant information when running to testing tool by hand by commissioning staff or read the script information set in advance, complete the simulation to device information; Under time-out or stopping state, it may be achieved to the adjustment function of test logic, detecting information etc.

6, on-line debugging performs

On-line debugging performs with virtual online debug function basically identical, but it is based on existing TP development approach, it is achieved to the control of ATE; When response data gathers, node data is all stored according to certain form.

Through the TP repeatedly run, the configuration carrying out diagnostic knowledge generation can be divided in testing attribute configuration section, according to the conclusion repeatedly run, data, node information etc., whether automatic analysis possesses can generate diagnostic knowledge and call diagnostic knowledge module when condition possesses, complete the generation of relevant knowledge, when on-line debugging performs, testing and diagnosing can be completed according to relevant prompting.

Wherein the 5th step and the 6th step and virtual online debugging and on-line debugging perform these two steps is parallel.

7, data preserve and data interface

The data that development approach exports mainly comprise the TP data with existing TP development approach compatibility, circuit data, test data, exploitation configuration data, test logical data etc. Development approach provides the data interface compatible with existing TP development approach, diagnostic knowledge software module, main flow EDA environment etc., and can be used as multiple independent dynamic link storehouse and called by other softwares.

Certain type circuit card in equipping taking certain type, as example, is developed based on this development approach, and test node configuration wherein is carried out following concrete explanation:

Complete the setting of the attribute to the circuit node needing test in this circuit, mainly comprise following 4 points: 1, be described by the detecting information of test node; 2, test signal attribute is set; 3, testing tool attribute; 4, logic attribute is tested. It is described as follows:

1, this circuit is carried out detecting information description, comprise the connection relation of the node number to circuit interior joint and relevant components and parts, test purpose, testing tool and possible test result and be described respectively. Detecting information is divided into many groups for different test situations, selects in different situations;

2, test signal attribute is set, the reserved relevant interface based on signal testing. Based on instrument test, analytical signal attribute mainly comprises the signal attribute under this test point standard state, such as sine, parameter value is such as the tolerance of voltage, frequency, dutycycle etc. and each parameter, and sets the tolerance function of the type signal types such as TTL, CMOS, LVTTL.

3, the instrument of circuit interior joint test is carried out testing tool attribute setup, mainly comprise two category informations: excitation and acquisition instrument information and test route information.

4, test logic attribute and mainly complete the setting to the logic relation between test node and upper and lower node.

Finally should illustrating, example described herein is only for explaining the present invention, and the present invention does not limit concrete intelligent terminal type, business classification, and the conversion above content done also drops within protection scope of the present invention.

Claims (10)

1. the circuit card fault location system searched for based on circuit network and figure, it is characterised in that, described system comprises:

Test node attribute acquisition module, for obtaining the attribute information of test node, described attribute information comprises: circuit interface attribute and test execution attribute;

Route file acquisition module, for obtaining route file, the line relation of described route file for describing between the passage of testing tool and test node;

Optimum sensor selection problem module, for manual test node being screened according to fault susceptibility and fault isolation degree parameter, and then select some the optimum test node set of node composition, wherein, described fault isolation degree characterization test node is to the separating capacity of fault;

Test logic generation module, for screening the test logic of the optimum node set interior joint obtained, or based on the test logic of test node attribute information and the automatic test node of route file generated based on test node attribute information and route file generated; Wherein said test logic relation comprises: sequentially, select, circulation or redirect;

Test result output module, for the test point selected being tested based on the test logic obtained, and then the localization of fault of completing circuit plate.

2. according to claim 1 based on the circuit card fault location system of circuit network and figure search, it is characterised in that, described system also comprises:

Configuration module, for inputting the testing attribute of the test node of the circuit board under test needing configuration, described testing attribute comprises: circuit interface attribute and test execution attribute;

Route file generating module, for the attribute information generation test node of the test node based on input and the route file of testing tool, wherein, the line relation of described route file for describing between the passage of testing tool and test node.

3. according to claim 1 based on the circuit card fault location system of circuit network and figure search, it is characterised in that, described system also comprises:

Store and interface module, for store localization of fault result and for the interface with the testing and diagnosing knowledge based on intelligent algorithm;

Image management module, for completing the importing of the schematic diagram to institute's testing circuit board and PCB, editor, setup of attribute and preservation.

4. according to claim 1 based on the circuit card fault location system of circuit network and figure search, it is characterised in that, described optimum sensor selection problem module comprises further:

First process submodule block, for calculating the difference degree factor of each test node to be selected, and sorts test node to be selected by order from big to small again according to the value obtaining the difference degree factor;

2nd process submodule block is empty for the optimum test node collection N* of initialize, and the set marking the test node to be selected after reordering is P={P0, P1,, Pi ... Pk}, the value of initialize parameter i is i=1 simultaneously, wherein the span of i is: i=1 ..., K, wherein, K is total number of node to be tested;

3rd process submodule block, for selecting node Pi from the set of test node to be selected, carries out fault classification calculating to the fault characteristic data set of this test node Pi;

And the calculation result according to all test sample books, calculate the fault isolation group of this test node PiWith fault isolation degree

Differentiate submodule block, for verifying the union isolation of the fault isolation group of set N* and test node PiWhether set up, if equation meets, then test node Pi is added into checking set N*, and drives and terminate submodule block; IfThen give up test node Pi and the value of parameters i is: i=i+1, restart the 3rd process submodule block and process; Otherwise, test Pi is added into checking set N*, opens the 3rd process submodule block;

Terminating submodule block, for judging that the optimum test node when selecting can distinguish all faults, then the screening process of optimum node set terminates.

5. according to claim 4 based on the circuit card fault location system of circuit network and figure search, it is characterised in that, adopt the value obtaining the difference degree factor with the following method:

First, define the inter-object distance d of i-th test node jth class fault sample_ijFor:

$d_{ij}=\frac{1}{N(N-1)}{\mathrm{\Σ}}_{m,n=1}^N|P_{ij}\left(m\right)-P_{ij}\left(n\right)|$

Wherein, m, n=1,2 ..., N, m �� n; I=1,2 ..., K; J=1,2 ..., the implication of M, m and n is; N is sample number, and K is total number of node to be tested, and M is the total number of fault class, P_ij(m) and P_ijN () represents that i-th test point jth class fault is for the eigenwert of m and the n-th sample respectively;

The mean value Di of the inter-object distance of i-th test node M class is:

$D_i=\frac{1}{M}{\mathrm{\Σ}}_{j=1}^M{d}_{ij}---\left(2\right)$

The mean value q of N number of sample of i-th test node jth class fault_ij:

$q_{ij}=\frac{1}{N}{\mathrm{\Σ}}_{n=1}^N{P}_{ij}\left(n\right)---\left(3\right)$

The mean value D ' of the class spacing of M class of i-th test point_iFor:

$D_i^{\′}=\frac{1}{M(M-1)}{\mathrm{\Σ}}_{\mathrm{\μ},\mathrm{\ω}}^M\left|q_{i\mathrm{\μ}}-q_{i\mathrm{\ω}}\right|---\left(4\right)$

Wherein, ��, ��=1,2 ..., M, �� �� ��; q_i��,q_i��Represent the mean value of �� of i-th test point and N number of sample of �� class respectively;

Then, based on above-mentioned parameter, the difference degree �� of definition test node i_iCalculation formula be:

��_i=(D '_i/D_i)��(min(R_bi)/max(R_wi))(5)

Wherein, min (R_bi) and max (R_wi) represent between the infima species of i-th test node sampled data discrete value in discrete value and maximum kind respectively.

6. according to claim 4 based on the circuit card fault location system of circuit network and figure search, it is characterised in that, adopt the fault isolation degree obtaining test node Pi with the following method:

Candidate's test node after reordering is designated as P_i, M class fault pattern is designated as failure collection F={F₀,F₁,��,F_M-1, wherein F₀For non-failure conditions; Provide as follows:

1) if all fault samples are accurately identified under certain fault model F m in F, and be there is not the situation being misdiagnosed as Fm in any fault sample under all the other fault patterns, then specifies fault isolation group:It is a fault isolation group of test node Pi, and this failure collection only comprises an element Fm;

2) if the part fault sample in fault model F m is misdiagnosed as fault Fn, then remember that Fm and Fn belongs to a fault ambiguity group of test node Pi, and it be designated as:If the part sample in Fm is misdiagnosed as fault model F n and Fq, then remembers that Fm, Fn and Fq are a fault ambiguity group of test node Pi, it is designated as ${\mathrm{AG}}_{mnq}^{P_i}=\{F_m,F_n,F_q\};$ Analogize successively;

Wherein m, n, q=0,1 in above definition ..., M-1; M �� n �� q;

Definition power set �� (F) represents fault set F={F0, F1 ..., FM-1};For the set of all fault ambiguity group of test node Pi;For the set of all fault isolation groups of test node Pi;

Obtain according to above-mentioned definition:

$\left\{\begin{array}{c}{\mathrm{AG}}^{P_i}\⊆\mathrm{\ρ}\left(F\right)\\ {\mathrm{IG}}^{N_n}\⊆\mathrm{\ρ}\left(F\right)\\ \left|{\mathrm{AG}}^{P_i}\∪{\mathrm{IG}}^{P_i}\right|=\left|F\right|\\ \left|{\mathrm{AG}}^{P_i}\right|+\left|{\mathrm{IG}}^{P_i}\right|\≥\left|F\right|\end{array}\right.---\left(6\right)$

Wherein, | | for getting element number in set, i.e. fault number;

Definition isolation, for test node Pi and M class fault pattern, the fault isolation degree of definition test node is:

${\mathrm{IG}}^{P_i}:{\mathrm{ID}}^{P_i}=\left|{\mathrm{IG}}^{P_i}\right|---\left(7\right)$

Obviously, $1\≤{\mathrm{IG}}^{P_i}\≤M;$

K nearest neighbor algorithm is utilized to calculate the fault isolation degree of all test nodes.

7., based on a circuit card localization of fault method for circuit network and figure search, described method comprises:

Step 101) obtain test node attribute information, described testing attribute comprises: circuit interface attribute and test execution attribute;

Step 102) obtain route file, the line relation of described route file for describing between the passage of testing tool and test node;

Step 103) according to fault susceptibility and fault isolation degree parameter, manual test node is screened, and then select some the optimum test node set of node composition: wherein, described fault isolation degree characterization test point is to the separating capacity of fault;

Step 104) the test logic of optimum node set interior joint that obtains based on test node attribute information and the screening of route file generated, or based on the test logic of test node attribute information and the automatic test node of route file generated; Wherein said test logic comprises: described logic relation comprises: sequentially, select, circulation or redirect;

Step 105) based on the test logic obtained, test node is tested, and then the localization of fault of completing circuit plate.

8. according to claim 7 based on the circuit card localization of fault method of circuit network and figure search, it is characterised in that, described step 101) also comprise before:

Input needs the testing attribute of the test node of the circuit board under test of configuration, and described testing attribute comprises: circuit interface attribute and test execution attribute;

Based on the attribute information generation test node of test node and the route file of testing tool of input, wherein, the line relation of described route file for describing between the passage of testing tool and test node.

9. according to claim 7 based on the circuit card localization of fault method of circuit network and figure search, it is characterised in that, described step 103) comprise further:

Step 103-1) calculate the difference degree factor of each test node to be selected, and according to the value obtaining the difference degree factor by sequentially test node to be selected being sorted again from big to small;

Step 103-2) the optimum test node collection N* of initialize is empty, and the set marking the test node to be selected after reordering is P={P0, P1 ... Pk}, the value of initialize parameter i is i=1 simultaneously, and wherein the span of i is: i=1 ... K, wherein, K is total number of node to be tested;

Step 103-3) from the set of test node to be selected, select node Pi, the fault characteristic data set of this node Pi is carried out fault classification calculating;

And the calculation result according to all test sample books, calculate the fault isolation group of this test node PiWith fault isolation degree

Differentiate submodule block, for verifying the union isolation of the fault isolation group of set N* and test node PiWhether set up, if equation meets, then test node Pi is added into checking set N*, and proceeds to step 103-4); IfThen give up test node Pi and the value of parameters i is: i=i+1, proceeds to step 103-3); Otherwise, test Pi is added into checking set N*, proceeds to step 103-3);

Step 103-4) all faults can be distinguished when the optimum test node selected, then the screening process of optimum node set terminates.

10. according to claim 9 based on the circuit card localization of fault method of circuit network and figure search, it is characterised in that, adopt the value obtaining the difference degree factor with the following method:

Define the inter-object distance d of i-th test node jth class fault sample_ijFor:

$d_{ij}=\frac{1}{N(N-1)}{\mathrm{\Σ}}_{m,n=1}^N|P_{ij}\left(m\right)-P_{ij}\left(n\right)|---\left(1\right)$

Wherein, m, n=1,2 ..., N, m �� n; I=1,2 ..., K; J=1,2 ..., the implication of M, m and n for (m and n: be greater than 1 and for natural number); N is sample number, and K is the total number of test node, and M is the total number of fault class, P_ij(m),P_ijN () represents that i-th test point jth class fault is for the eigenwert of m and the n-th sample respectively;

The mean value Di of the inter-object distance of i-th test node M class is:

$D_i=\frac{1}{M}{\mathrm{\Σ}}_{j=1}^M{d}_{ij}---\left(2\right)$

The mean value q of N number of sample of i-th test node jth class fault_ij:

$q_{ij}=\frac{1}{N}{\mathrm{\Σ}}_{n=1}^N{P}_{ij}\left(n\right)---\left(3\right)$

The mean value D ' of the class spacing of M class of i-th test point_iFor:

$D_i^{\′}=\frac{1}{M(M-1)}{\mathrm{\Σ}}_{\mathrm{\μ},\mathrm{\ω}}^M\left|q_{i\mathrm{\μ}}-q_{i\mathrm{\ω}}\right|---\left(4\right)$

Wherein, ��, ��=1,2 ..., M, �� �� ��; q_i��,q_i��Represent the mean value of �� of i-th test point and N number of sample of �� class respectively;

The difference degree �� of definition test node i_iFor:

��_i=(D '_i/D_i)��(min(R_bi)/max(R_wi))(5)

Wherein, min (R_bi) and max (R_wi) represent between the infima species of i-th test node sampled data discrete value in discrete value and maximum kind respectively.