CN105645070A - Automatic control system of material charging machine - Google Patents

Abstract

The invention discloses an automatic control system of a material charging machine. The control system achieves automatic material charging through a single chip microcomputer AT89S52. In the numerous fields of modern science and technology, an automatic control technology plays a more and more important role. Besides, along with development of production and scientific technologies, the automation level is increasingly high. A certain parameter of a controlled object is automatically operated according to a preset rule through a control device adopted for automatic control. The automatic control system of the material charging machine achieves functions through the automatic control technology, so that the working efficiency is greatly improved and the whole process is fast and stable.

Description

Automatic charging equipment Controlling System

Automatic charging equipment Controlling System of the present invention uses AT89S52 single board computer to realize self-feeding Controlling System. In many fields of modern science and technology, it is more and more important that automatic control technology plays this, and, along with producing and scientific and technical development, automatization level is also more and more higher. Automatically control utilizes control device that certain parameter of controlled plant is run according to predetermined rule automatically. The automatic charging equipment Controlling System of this setting adopts automatic control technology to carry out practical function, so just substantially increases the efficiency of work, and whole process is not only fast but also steady.

Main technical indicator

(1) AT89S52 micro-chip is adopted to control stepper-motor as controller.

(2) show with charactron, adjust with button.

(3) reflection infrared sensor is used to carry out workpiece counting.

(4) stepping motor smooth speed governing can be realized, workpiece is counted.

(5) manual and automatic two kinds of operating mode are divided.

(6) state shell realizes time switch, quantitative switching automatically.

(7) L298N motor driver is used to be driven by stepper-motor.

AT89S52 is a kind of low-power consumption, high-performance CMOS 8 8-digit microcontroller, has 8K in-system programmable components flash storage. Atmel company high-density nonvolatile memory technology is used to manufacture, completely compatible with industry 80C51 product instruction and pin. On sheet, Flash allows program store in-system programmable components, is also suitable for conventional programming device. On a single chip, 8 dexterous bit CPUs and in-system programmable components Flash is had so that height is flexible, the solution of super efficient for numerous embedded Control application system provides for AT89S52. AT89S52 has following standard function: 8k bytes Flash, 256 byte RAM, 32 I/O mouth lines, guard the gate dog timer, 2 data pointers, three 16 timer/counters, one 6 vector, 2 grades of interruption structures, full duplex serial port, crystal oscillator and clock circuit in sheet. In addition, AT89S52 can be down to the operation of 0Hz static logic, supports that 2 kinds of software-selectable select energy-saving mode. Under idle pattern, CPU stops work, allows RAM, timer/counter, serial ports, interruption continuation work. Under power down protection mode, RAM content is saved, and vibrator is frozen, and all work of micro-chip stop, and interrupts until next or hardware reset.

This setting be according to charging technology requirement by monolithic processor controlled automatic feeding system, its principle of work is: counted by the workpiece in travelling belt, it is possible to start by set date motor or stop motor. Output can be set so that it is automatically stop. The transmission speed that can change travelling belt is to improve production efficiency. Using reflection infrared sensor to be counted by workpiece, production output in the unit time is calculated by one.

Realizing the self-feeding in producing with micro-chip, the external motor driver of palpus, my setting adopts the motor special driving chip L298N that on market, stable performance driving force is strong, substantially increases the service efficiency of motor like this. More improve the ability of control motor, reduce error relatively, reduce software programming complexity. according to the requirement of system setting function, tentatively determine to arrange system by master control module, sensor assembly, memory module, keyboard interface module, display module and motor drive module totally 6 modules form.

1. master control module: taking AT89S52 micro-chip as core.

2. sensor assembly: adopt reflection sensor JX-359-403W

3. memory module: adopt AT24C02. AT24C02 is the Low-Power CMOS serial EEPROM of American ATMEL, and it includes 256 �� 8 storage spaces, has the features such as operating voltage width (2.5��5.5V), erasable number of times many (being greater than 10000 times), writing speed fast (being less than 10ms).

4. keyboard interface module: this arranges common employing button 6, is connected with six I/O pins of micro-chip respectively, and function is respectively manual/auto switching, start/stop, acceleration, deceleration, start by set date stopping, the stopping of fixed output quota amount.

5. display module: display section shows production quantity by 6 numeral method 4 group. Two one group Displaying timer time.

6. motor drive module: use motor driver L298N and use TP521 photoelectricity coupling mechanism to carry out anti-interference isolation.

Exercise question source and problem meaning

In many fields of modern science and technology, it is more and more important that automatic control technology plays this, and, along with producing and scientific and technical development, automatization level is also more and more higher. Automatically control utilizes control device that certain parameter of controlled plant is run according to predetermined rule automatically. The automatic charging equipment Controlling System of the present invention adopts automatic control technology to carry out practical function, so just substantially increases the efficiency of work, and whole process is not only fast but also steady.

The principle of work of automatic charging equipment Controlling System and technical requirements

The present invention's is the charging system supporting with hopper formula drying machine by monolithic processor controlled automatic feeding system. According to charging technology requirement, its principle of work is: first closed by valve tube, starts motor, with rough vacuum air-flow, plastic resin particles is sent into valve tube, motor stalling, then particle is entered hopper, so circulate.

In the Controlling System of invention, an available electric machine control two reinforced production lines, are switched by directional valve. Two production lines both can run separately, it is possible to same to operate. If both same operate, after a production line conveying terminates, determining another production line discharge and terminate, so, motor not stall and directional valve commutation thus are another production line feeding. The efficiency of Controlling System and motor can be played like this, thus realize feed automatization.

The controller of Controlling System is made up of single chip computer89C51 and expansion circuit, micro-chip control rly., and Control alternating current contactor, is controlled again the motion of the topworkies such as motor by contactor. This Controlling System according to the needs of feeding process, can arrange conveying, the discharge, completely the parameter value such as material, empty material of two production lines, it is possible to the previous process parameter value of Load System.

The main technical details of system:

(1) with an electric machine control two production lines

(2) want full material state to be detected, and demonstrate conveying, discharge, completely expect the time

(3) time error: 0.1 second

(4) there is immunity from interference

The selection of micro-chip

Since the eighties in 20th century, the development of micro-chip is very rapid, and with regard to general single chip, the product that some famous computer producers have put on market in the world just has more than 50 series, hundreds of kinds. Manufacturer and the main type of 8 comparatively famous in the world at present micro-chips are as follows:

American I ntel company: MCS 51 series and enhancement type series thereof

Motorola company of the U.S.: 6801 series and 6805 series

Atmel company of the U.S.: the micro-chips such as 89C51

Zilog company of the U.S.: Z8 series and SUPER8

Fairchild company of the U.S.: F8 series and 3870 series

Rockwell company of the U.S.: 6500/1 series

American TI (De Kesasi instrument) company: TMS7000 series

NS(National Semiconductor) company: NS8070 series etc.

Although the kind of micro-chip is a lot, but use maximum MCS 51 series monolithics of Intel company and the 89C51 micro-chip of Atmel company of the U.S. in China

MCS 51 series monolithic comprises three basic models 8031,8051,8751

8031 inside comprise 8 bit CPUs, 128 byte RAM, 21 specific function registers (SFR), 48 bit parallel I/O mouths, 1 full duplex serial port, 2 16 timer/counters, but without program store in sheet, need to extend out EPROM chip. Cumbersome, will not adopt

8051 is that Embedded has 4KROM on the basis of 8031, as program store, is the little system that a program is no more than 4K byte. When program in ROM is company's making chip, firing on behalf of user, 8051 dispatched from the factory are all the micro-chips containing special purpose. So 8051 are applicable to be applied in program fixed, and in the big micro-chip product of batch. Also will not adopt.

8751 is on 8031 bases, adds the EPROM of 4K byte, it constitutes the little system that a program is less than 4KB. User can by program Solidification in EPROM, it is possible to update routine repeatedly. But its price is more expensive relative to 8031. 8031 extend out the just suitable for 8751 of a slice 4KBEPROM, and its great advantage is that price is low. Along with the development of large-scale integrated circuit technology, the peripheral interface circuit that can load in sheet can also be large-scale. Also will not adopt.

AT89C51 is the low voltage that American ATMEL is produced, high-performance CMOS 8 micro-chips, sheet include 4Kbytes can be repeatedly erasable read-only program memory (PEROM) and the random access data storage (ROM) of 128bytes, device adopts the high-density of ATMEL company, nonvolatile storage technologies to produce, compatibility standard MCS-51 order set, sheet built-in general-purpose 8 central processing units (CPU) and Flash storage unit. Powerful AT89C51 micro-chip can provide the application scenario of many high performance-price ratios, can flexible Application in various control field. This invention just adopts AT89C51.

The selection of thing level sensor

Thing position refers to that the liquid in storage vessel or the equipment of industrial product, powder strengthen the interface location between solid, gas, it is also possible to be the interface location formed owing to density does not wait between immiscible two kinds of liquid. It is divided into liquid level, material position, boundary's level sensor or transmitter according to concrete purposes. Material consumption amount or the parameter of output metering are not only in thing position, are also ensure to produce continuously the important parameter with device security. Particularly in modern industry, industrial scale is big, speed height, and often has high temperature, high pressure, severe corrosive or inflammable and explosive material, and supervision and automatic control for thing position are most important especially.

Level gauging can be used for calculating material reserves. For powder body, it has to be taken into account have space between particle, density and unit weight should be distinguished. Density refers to the quality of the material per unit volume not containing space, i.e. common mass density, if being multiplied by gravity acceleration g, just becomes gravimetric density r, referred to as severe. Unit weight is the weight v of the per unit volume comprising space, is also exactly apparent severe or macroscopic view severe, and it is less than the severe of particulate matter itself always, and its difference is decided by voidage. And voidage depends on and many factors. The such as consistent degree of particle shape, size, whether by external force compacting, whether live through vibration, with or without agglutinating value(of coal) etc., so not easily accurately converting between the volumetric reserve of powder material and quality reserves, this should be noted that.

Appearance formula thing level sensor

When utilizing material specific inductivity constant, the principle of interelectrode capacity direct ratio and thing position, can form capacitance object position sensor.

Structure according to motor can be divided in three by holding formula thing level sensor: (1) is suitable for and the insulativity material in conductive container, and container is vertical and cylindrical, wall is a pole, and inserting metal bar along axis is another pole, and the electric capacity C formed therebetween is proportional to thing position. Also can the flexible lead of suspension strap weight as motor. (2) be suitable for and non-metallic container, though or be metal vessel but non-vertical and cylindrical, material is insulativity. At this moment with insulating support set metal cylinder around the strong electrode of rod, cylinder upper and lower opening, or it is uniformly distributed multiple hole on the whole, make inside and outside thing position identical. Central authorities' pole and sleeve coaxial with it form two electrodes, and electric capacity and container shapes are unrelated therebetween, only depend on thing position. So this kind of electrode is only for liquid level, powder body is easily trapped between pole. (3) for electroconductibility material, play profile the same with (1), but central authorities' circular rod electrode is surrounded by insulating material, electric capacity determines by the specific inductivity of insulating material and thing position, unrelated with the specific inductivity of material, conductive material makes the distance between barrel and contre electrode shorten to the thickness of insulation layer, and the lifting of thing position is equivalent to electrode area and changes.

Capacitance object position sensor is without moving parts, unrelated with material density, but will be very big on measuring result impact when should note moisture content in material, and requires that the specific inductivity of material and dielectric constant of air difference are big, need to use high frequency circuit. So will not adopt.

Resistance type level sensing transducer

Resistance type level sensing transducer refers to the barrier force that mechanical movement is presented by material. Form of powdery particles material ratio fluent meterial mobility is poor, and mobile has obvious resistance, utilizes this feature can form various level sensing transducer.

(1) method explored by weight: install the stepper-motor controlled by pulse distributor at container top, slowly discharges the outstanding cable wire having weight when this motor rotates forward. After weight drops to and contacts with charge level, what cable wire was subject to makes a concerted effort to reduce suddenly, impels force transducer to send pulse. This pulse changes the state of gating circuit, stepper-motor is changed and turns to weight to promote, start pulse counting simultaneously. Treat that weight rises to top and touches travel switch, stepper-motor stop rotate, unison counter also stop count and show material position (material place value and container full height subtract duplicate removal hammer into shape stroke difference). Displayed value remains to after exploring next time always and refreshes as another value. The triggering signal starting to explore periodically can be supplied by timing circuit, it is also possible to starts artificially. When not exploring, weight remains on container top, in order to avoid weight is flowed or blow over and cover completely by material. Just in case weight is buried by thing position, the powerful pulling force produced during discharges material is it is possible to break cable wire warning measure and discharging filter grid.

But this kind of approach application logical circuit and digital technique, can continuously measured material place value and export digital quantity, be digital sensor, but its sampling is periodic, the time is discontinuous, and this invention will not adopt.

(2) oar or contour push-board process is revolved: this is a kind of position formula sensor, or weighing bit switch. Fill fractional horse-power motor at a certain height place of wall of container, its shaft extension enters in container, and end is with paddle blade. When blade does not contact material, under the no cargo conditions rotated freely, the electric current of electric motor is very little, once material position rises to and blade contact, rotary resistance increases, and even becomes stall state, and electric current significantly strengthens. Size according to electric current makes the contact action of rly., sends material position and reports to the police or position formula control signal. As motor shaft turns into to-and-fro movement through toggle, then piston or flat board can be driven to do push-and-pull action in a reservoir, contour push-board process. Revolve paddle method or contour push-board process differs and establishes a capital action of relay contact when being size by current of electric, it is also possible to utilize the transmission rig on clutch coupling or connecting rod, change the on off state of electric contact when blade or push pedal load increase. Electric motor used should be able under long-time stall state, or under slipping of clutch state, unlikely overheated and damage.

The stuff level switch that this kind of principle is formed, can only install on the wall, and mounting height depends on the material place value corresponding to action. Application is so not extensive, invents in proper order and will not adopt yet.

(3) tuning fork method: according to material, with or without resistance, the tuning fork in vibration being found out, whether material position arrives or exceed certain height, and send make-and-break signal, this kind of principle does not need significantly mechanical movement, and driving power is little, physical construction is simple, sensitive and reliable.

Tuning fork is made up of the metal that elasticity is good, itself has the natural frequency determined, the frequency such as additional alternating force is consistent with its natural frequency, then pitch body and be in resonance state. Owing to ambient air is faint to the damping of vibration, the energy waste of metal inside is little again, so only needing the vibration that small driving power just can remain stronger. After powder material touches fork body, in the friction of energy expenditure between material particles, forcing amplitude sharp-decay, tuning fork stops shaking.

In order to provide the motivating force of alternation to tuning fork, utilize amplification circuit that piezoelectric element is applied alternating electric field, produce mechanical force on fork body by inverse piezoelectric effect. With the detection vibration of the direct piezoelectric effect of other one group of piezoelectric element, it is faint alternate electrical signal vibration power. Again by electron-amplifier and shift circuit, the signal amplification of element that inspection is shaken. Through phase shift, it is applied to driving element and gets on, form closed loop oscillator. In this closed loop, existing mechanical energy also has electric energy, and fork body is one of them link, if being subject to material damping to be difficult to vibration, the amplitude of positive regeeration and phase place all will significantly change, and destroy oscillating condition, will stop to shake. As long as amplify circuit output termination with suitable device, be not difficult to obtain switch signal.

In order to protect piezoelectric element to damage and dust pollution from material, it is inner that the element that driving and inspection shaken is contained in fork body, through metallic membrane transmitting vibrations. If all filling fork body at the upper and lower of container, it is possible to realize the logic control of automatic feed or self-emptying, or the out-of-limit the signal is far passed in material position to watch-keeping cubicle. Pilot circuit in watch-keeping cubicle judges that whether material position is out-of-limit, and makes controlled input and output material equipment start-stop on request.

And when pitching the manufacture of body and assemble good, tuning fork also can be used for liquid measure and control. Not needing significantly mechanical movement when measuring, driving power is little, and physical construction is simple, sensitive and reliable. Tuning fork method resistance type level sensing transducer is selected in this invention.

The selection of memory expansion circuit

24C01 expands:

Each micro-chip in serial bus or integrated circuit modules, by a data line (SDA) and a clock lines (SCL), carry out addressing and information transmission according to communication stipulations. Each integrated circuit modules has only dummy address, both can be master control machine (energy control bus, and the initialize of a transmitting procedure can be completed and produce clocksignal and the device of transmission termination signal) or controlled machine (by the device of primary controller addressing), it can be the device in transmitter (in bus 1: the device sending information) or receptor (receive bus and control the device of breath) I2C bus, different operating state according to it, can be divided into master control transmitter, master control receptor, controlled transmitter, passive controlled receiver. Looking forward to invention control bus when multiple primary controller simultaneously and do not lose letter, this is multi-master competition. At this moment will arbitrating, arbitration is exactly the process carrying out ruling for this kind of situation. Only allowing its Bian primary controller to hold over bus, other exits rich supports by the arm device state. Arbitration process also being ensured, the information of bus is not lost. The clocksignal of all primary controllers participated in the competition must be carried out synchronous processing during multi-master competition. When information is transmitted, SCL is between high period, and the information on SDA must keep stablizing constant, and only SCL is between low period, and the information on SDA just allows to change. On SDA, each portion of information is corresponding with the time clock of SCL simultaneously. SCL does not have clocksignal, and stopping transmission being in waiting status by SDA information. This, because line "AND" logic, makes SCL vise bus when lower level. The output terminal realizing the line "AND" logic function total line interface of each I2C must be open-drain or open collector structure. SCL keeps between high period, and SDA changes this kind of state by high level to lower level and is defined as start signal. SCL keeps between high period, and SDA is changed to high level by lower level, and this kind of state is defined as termination signal. Each byte necessary 8 (first highest significant position transmits) of SDA transmission, each transmits byte must follow a response bits. The clocksignal corresponding to acknowledge signal is produced by primary controller, and transmitter discharges SDA in this clocksignal, makes it be in high level state, to receive the acknowledge signal sent by receptor at this. At this moment also necessary SCL is between this high period for receptor, and on SDA, output constant lower level letter gas is to complete the output of acknowledge signal. In whole transmitting procedure, the byte number of transmission be do not have conditional. After transfer for some time, receptor cannot continue to receive more data, and primary controller can terminate the transmission of data equally.

24C01 is a kind of 128 byte serial CMOSEEPROM, and it has following feature: 1. storage capacity is 128 bytes. 2. serial line interface can use common two I/O interfaces. 3. there is page and write pattern: every page of 4 bytes. 4. it is less than 10ms synchronizing cycle. It only uses a data line and a clock lines, adopts the 24C01 serial ports storer of ATMEL company, applies simple and convenient, but its programming is comparatively complicated.

2864A chip is expanded:

2864A is a kind of parallel EEPROM, and its feature is the same, but every page has 16 bytes, shown in the interface circuit of 2864A and 8051 micro-chips is invented as follows, the sheet of 2864A selects end to be connected with high address wire P2.7, and P2.7=0 just can choose 2864A, and this kind of linear selection system determines the corresponding multiple sets of address space of 2864A, i.e. 0000H ~ 1FFFH, 2000H ~ 3FFFH, 4000H ~ 5FFFH, 6000H ~ 7FFFH, this 8K byte memory can be used as data-carrier store and uses, but after falling electricity, data are not lost.

Four kinds of mode of operation of 2864A:

(1) maintaining mode: when for high level, 2864A enters low-power consumption and maintains state. Now, output line is high resistance state, and the electric current of chip drops to from 140mA and maintains electric current 60mA.

(2) read mode: when being high level with being lower level, inner data snubber is opened, and data serve bus, now, can carry out reading operation.

(3) mode is write: 2864A provides two kinds of data write modes: page write and byte write.

Page write: in order to improve writing speed, be provided with " page buffer " of 16 bytes in 2864A sheet, and whole memory array is divided into 512 pages, every page of 16 bytes. The differentiation of page can be determined by high 9 (A4 ~ A12) of address, and low four (A0 ~ A3) of address wire are in order to select one of address, 16 in page buffer unit. Two steps can be divided into realize the write operation of 2864A: the first step, writes page buffer data under software, and this portion is called that page loads, be the same with the operation of general static RAM write. 2nd step, after last byte (i.e. the 16th byte) is written to page buffer, 20ns starts automatically, and the content of page buffer is write in address unit corresponding in eeprom array, and this step becomes page and stores.

When writing mode, being lower level, at negative edge, address code A0 ~ A12 is by latches in sheet, and when positive rise, data are latched in sheet to also have a byte to load timer in limited time, as long as the time does not arrive, data can write page buffer randomly. In the process writing data continuously to page buffer, not worrying that timer can overflow in limited time, because whenever negative edge, timer is automatically reset and restarts timing in limited time. Timer requires that the operating time of write byte data must meet in limited time; < < 20 �� S are correctly complete the key to 2864A page write operation to 3 �� S like this. When one page loads complete, when no longer including signal, timer will overflow in limited time, so page storage operation starts immediately automatically. First the content choosing page being wiped, the data then write are delivered in eeprom array by page buffer.

Byte writes: the process of byte write and the process of page write are similar, and difference is only to write a byte, and timer just overflows in limited time.

(4) data query mode: data query refers to whether the page memory cycle detecting in write operation with software completes.

During page stores, as 2864A performs reading operation, what so read is the byte of last write, if the dump work of chip does not complete, then the most significant digit reading data is the radix-minus-one complement originally writing byte most significant digit. Accordingly, CPU can judge whether the programming of chip terminates. If the data read are identical with the data of write, representing that chip has completed programming, CPU can continue to load lower page of data to 2864A. And it is fairly simple to programme, so this invention adopts this scheme.

LED display circuit is selected

LED indicating meter is spliced into N position LED indicating meter by N number of LED displaying block. N number of LED displaying block has N to follow a route selection, difference according to display mode, the method for attachment of position route selection and section route selection is also different, the font of section selector control display character, and position route selection is the public end of each LED displaying block, it controls this LED and shows the bright, dark of position. LED indicating meter has static state display and Dynamic Announce two kinds of display modes.

LED static state display mode

When LED indicating meter works in static state display mode, everybody common cathode pole (or common-anode) links together and ground connection (or+5V); The section route selection (a ~ dp) of every exports with the latch of 8 respectively and is connected. So being called static state display. The display character of each LED is once determining, the output of respective latch will remain unchanged, until showing another character. Also just therefore like this, the brightness of static state display device is all higher. This kind of display mode interface programming is easy. The cost paid is that to take mouthful line more, if using I/O interface, then to be taken 48 I/O mouths, if using latch interface, then with 4 74LS373 chips. If indicating meter figure place increases, then static state display mode cannot adapt to especially, therefore when figure place showing is more, generally all adopts dynamic display types.

LED dynamic display types

When Multi-bit LED shows, in order to simplify hardware circuit, usually the section route selection of all positions is connected in parallel accordingly, has 8 I/O mouths control, form the multiplexed of section route selection. And everybody common-anode or common cathode pole are respectively by corresponding I/O line traffic control, it is achieved everybody timesharing gating. Its stage casing route selection takies 8 I/O mouths, and position route selection takies 4 I/O mouths. Owing to everybody section route selection is in parallel, the output of section code is all identical concerning every, and therefore, in the same moment, if the route selection of every position is all in strobe state, 4 LED are by character identical for display. The display character corresponding to one's own department or unit can be demonstrated to every LED, just must adopt scanning display mode, namely at a time, only allow the position route selection state of a certain position, and other everybody position route selections are in closing condition, meanwhile, section route selection exports the section code that corresponding positions to be shown byte. Determining the timed interval of LED different positions display, can not be too short, because photodiode is from being conducting to, luminescence has certain time delay, and ON time is too short, and the too weak people's eye of luminescence cannot be seen clearly. But can not be too long, because to be limited to critical flicker frequency after all, and this time is more long, taking the CPU time also more many, in addition, display position is increased, also taking a large amount of CPU time, therefore Dynamic Announce essence is the minimizing sacrifice CPU time exchanging element for.

So, owing to native system only relates to 2 display translation, just have employed and the LED static state display mode that 28 bit shift register tandems use.

Input through keyboard circuit

Matrix form keyboard interface:

Matrix form keyboard (also claims determinant keyboard) and is applicable to the more occasion of number of keys, and it is made up of line and row line, and button is positioned on the intersection point of ranks. The row-column configuration of one 3 �� 3 can form the keyboard that has 9 buttons. With reason, the row-column configuration of 4 �� 4 can form the keyboard of 16 keys, it is evident that in the occasion that number of keys is more, and matrix form keyboard, compared with independent keyboard, will save a lot of I/O mouth lines. Button is arranged on ranks line intersection point, and keyswitch two ends received respectively by ranks line. Line is received on+5V by pull-up resistor. When pressing without button at ordinary times, line is in high level state, and when there being button to press, the row line level being connected due to this journey line is determined by line level state. If row line level is lower level, then line level is lower level, if row line level is high level, then line level is high level. This is the key point identifying whether matrix keyboard button is pressed. Owing to ranks line in matrix keyboard is that multikey is public, each button all affects the level of these key place ranks. Therefore each button will affect each other mutually, so must be cooperated by ranks signal than doing suitable process, could determine the position of closed key.

Stand alone type keystroke interface:

Stand alone type button is exactly that each button is separate, and each button respectively accesses an input line, and the button working order in an input line can not affect the working order in other input lines. Therefore, can be easy to judge which button has been pressed by detecting the level state of input line. Stand alone type key circuit flexible configuration, software is simple. But each button needs to take an input aperture line, when number of keys is more, it is necessary to more input aperture line and circuit complex structure, so planting keyboard to be applicable to the occasion that button is less or operating speed is higher.

Owing to " starting 1 " key of total startup two production lines in this system is with " starting 2 " key, every minute and second selects key, set of time adds, set of time subtracts, show the switching key of production line state, set of time key, time-switching key. Only these 8 keys, fairly simple. So just adopting stand alone type keystroke interface circuit.

Main power circuit adopts AT89C51, owing to AT89C51 includes 4KB capacity, does not therefore need to extend out ROM in invention. Hardware circuit mainly contains LED display circuit, keyboard accepts circuit, Control circuit, EEPROM exterior storage device expansion circuit, and the composition such as the dog MAX813L that guards the gate.

Main power circuit adopts AT89C51, owing to AT89C51 includes 4KB capacity, does not therefore need to extend out ROM in invention. Hardware circuit mainly contains LED display circuit, keyboard accepts circuit, Control circuit, EEPROM exterior storage device expansion circuit, and the composition such as the dog MAX813L that guards the gate.

Host circuit core devices is introduced

AT89C51 is the low voltage that American ATMEL is produced, high-performance CMOS 8 micro-chips, sheet include 4Kbytes can be repeatedly erasable read-only program memory (PEROM) and the random access data storage (ROM) of 128bytes, device adopts the high-density of ATMEL company, nonvolatile storage technologies to produce, compatibility standard MCS-51 order set, sheet built-in general-purpose 8 central processing units (CPU) and Flash storage unit. Powerful AT89C51 micro-chip can provide the application scenario of many high performance-price ratios, can flexible Application in various control field.

AT89C51 salient features parameter

. completely compatible with MCS-51 product order set

.4K byte can weigh Flash erase/write sudden strain of a muscle speed storer

.1000 secondary erase-write cycles

. full static state operation: 0Hz---24MHz

. three grades of encipheror storeies

.128 �� 8 byte inner RAM

.32 individual programmable I/O mouth line

.2 individual 16 Timer/Counter

.6 individual interrupt source

. serial UART passage able to programme

. low power free time and power-down mode

AT89C51 functional performance is summarized

AT89C51 provides following standard function: 4K bytes Flash dodges speed storer, 128 byte inner RAM, 32 I/0 mouth lines, two 16 Timer/Counter, and one 5 vector two-stage interrupts structure, a full duplex serial communication port, vibrator and clock circuit in sheet. Meanwhile, AT89C51 can the static logic operation of near 0Hz, and support the power saving operation pattern of two kinds of software-selectable. Idle mode stops the work of CPU, but allows RAM, Timer/Counter, serial communication port and interrupt system continuation work. Power-down mode preserves the content in RAM, but vibrator stopping work and forbid other all component workings until next hardware resets.

.P0 mouth: P0 mouth is one group 8 the two-way I/O of open-drain type is also address/data bus multiplexing mouth. As the delivery port used time, the mode of every potential energy absorption current drives 8 TTL logic gates, port one writing can be used as high impedance input and use

When access external data storer or program store, this group mouth line timesharing conversion address (low 8) and multiplexed data bus, activate internal pull-up resistor during the visit.

When Flash programmes, P0 receives command byte, and when program verifies, output order byte, during verification, it is desired to external pull-up resistor.

.P1 mouth: P1 mouth is 8 two-way I/O mouths of a band internal pull-up resistor, the output buffer stage of P1 can drive (absorbing or outward current) 4 TTL logic gates. To port one writing, by the pull-up resistor of inside, port is forgotten about it high level, now can do input aperture. When doing input aperture use, because inside exists pull-up resistor, when certain pin is drawn low by outside signal, an electric current (IIL) can be exported.

During Flash programming and program verify, P1 receives low 8 bit address.

.P2 mouth: P2 mouth is 8 two-way I/O mouths with internal pull-up resistor, the output buffer stage of P2 can drive (absorbing or outward current) 4 TTL logic gates. To port one writing, by the pull-up resistor of inside, port is moved to high level, now can do input aperture, when doing input aperture use, because inside exists pull-up resistor, when certain pin is drawn low by outside signal, an electric current (IIL) can be exported.

When accessing external data memory (such as the performing MOVEDPTR instruction) of external program memory or 16 bit address. P2 mouth sends high 8 bit address data. When accessing external data memory (such as the performing MOVXRI instruction) of 8 bit address, the content (being also the content of the total R2 register of specific function register (SFR) Qu) on P2 mouth line, does not change during the visit whole.

When Flash programming or verification, P2 also receives high bit address and other control signals.

.P3 mouth: P3 mouth is one group of 8 two-way I/O mouth with internal pull-up resistor, P3 mouth exports buffer stage can drive (absorbing or outward current) 4 TTL logic gates. When P3 mouth is write " 1 ", they are drawn high by internal pull-up resistor and can be used as input port. When making input terminus, drawn the low P3 mouth will with pull-up resistor outward current (IIL) by outside.

P3 mouth is except as, except general I/O mouth line, prior purposes is its 2nd function, as shown in the table:

Port pin the 2nd function

P3.0RXD(serial input mouth)

P3.1TXD(Serial output mouth)

0 is interrupted) outside P3.2(

1 is interrupted) outside P3,3(

P3.4T0(Timer/Counter 0)

P3.5T1(Timer/Counter 1)

P3.6(external data memory write gate)

P3.7(external data memory reads gating)

P3 mouth also receives some for the control signal of Flash programming flash memory and program verification.

.RST: reset input. When oscillator operation, there are two machine cycle above high level by monolithic processor resetting in RST pin.

: when accessing external program memory or data-carrier store .ALE/ ALE(address is latched and is allowed) export low 8 bit bytes that pulse is used for latch address. Even if not access external memory. ALE still an oscillation frequency clock 1/6 export fixing positive pulse signal, therefore it can external output clock or for timing object. But it is to be noted that an ALE pulse will be skipped whenever access external data storer.

During flash storage being programmed, this pin is also for inputting programming pulse ().

As being necessary, by the position, D0 position to the 8EH unit in specific function register (SFR) district, can forbid that ALE operates. Behind this position, position, only a MOVX and MOVC instruction ALE just can be activated, and in addition, this pin can be drawn high by faint, when micro-chip performs outside program, should arrange ALE invalid.

.: program stores the read strobe signal allowing () output to be external program memory, when AT89C51 is by external program memory instruction fetch (or data), each machine cycle twice is effective, namely two pulses are exported, during this period, when access external data storer, this twice effective signal does not occur.

.EA/VPP: outside access allows, and makes CPU only access external program memory (address is 0000H--FFFFH), and EA end must keep lower level (ground connection). If it is to be noted that encrypted bits LB1 is programmed, during reset, EA end state can be latched in inside.

If EA end is high level (connecing Vcc end), CPU then performs inside can latch EA end state.

When flash storage is programmed, this pin adds that the programming of+12V allows power supply Vpp, and this must be this device certainly is use 12V program voltage Vpp.

.XTAL1: vibrator sign reversing amplifier and the input terminus of internal clock generator.

.XTAL2: the output terminal of vibrator 3 amplifier.

3.2.3 clock oscillation device

Having one in AT89C51 for forming the high gain sign reversing amplifier of internal oscillator, pin XTAL and XTAL2 is input terminus and the output terminal of this amplifier respectively. This amplifier forms self-oscillator together with quartz crystal or Ceramic Resonator outside as the sheet of feedback element:

External quartz crystal (or ceramic resonator) and electric capacity C1, C2 are connected in the feedback loop of amplifier to form oscillatory circuit in parallel. Although external capacitor C1, C2 are not had very strict requirement, but the height of the size of capacitance meeting minimal effect oscillation frequency, the stability of oscillator operation, the difficulty or ease program of starting of oscillation and temperature stability, if use quartz crystal, electric capacity is then recommended to use 30pF10pF, and as used ceramic resonator suggestion to select 40pF10F.

User can also adopt outside clock, adopts the circuit of clock such as invention. In this case, external clock pulse receives XTAL1 end, i.e. the input terminus of internal clock generator, and XTAL2 is then unsettled.

Due to outside clocksignal by after 2 minutes triggering device as internal clock signal, so the dutycycle of outside clocksignal is not had particular requirement, but the AT89C51 that minimum high level lasting time and maximum low duration should meet product technology condition has province's power mode of two kinds of available software programmings, they are idle patterns and fall an operating mode. These two kinds of modes be control special register PCON(and Energy control register) in PD(PCON.1) and IDL(PCON.0) position realize. PD is power-down mode, as PD=1, activates power down operations pattern, and micro-chip pattern, namely PD and IOL is 1 simultaneously, then first activate power-down mode.

At vacant working mode state, CPU keeps the peripheral hardware in sleep state and all to keep state of activation, and this kind of mode is produced by software. Now, the content of ram in slice and all specific function registers remains unchanged. Idle pattern can reset by the interrupt request of any permission or hardware and terminate.

The method terminating vacant working pattern has two kinds, and any event being allowed to interrupt of the first is activated, IDL(PCON.0) removed by hardware, at once terminate vacant working pattern. First program can respond interruption, enters interrupt service routine, executes interrupt service routine and follows RETI(closely and interrupt returning) after instruction, next instruction to be performed is exactly make micro-chip enter idle that instruction of pattern instruction below.

It two is that resetted by hardware also can by vacant working mode ends. It should be noted that, when there being hardware reset to terminate vacant working pattern, CPU normally continues steering routine from activating next instruction of idle that instruction of pattern, complete internal reset operation, hardware reset pulse to be kept two machine cycles (24 clock period) effective, in this case, internalized prohibition CPU accesses ram in slice, and allows to access other port. In order to avoid port being produced unexpected write, after activating that instruction of idle pattern instruction should not be one to the write instruction of port or exterior storage device.

Power-down mode

Falling under dot pattern, vibrator stopping work, the instruction entering power-down mode is the instruction that the last item is performed, and the content of ram in slice and specific function register is frozen before terminating power-down mode. The unique method exiting power-down mode is that hardware resets, after reset by redefining whole specific function register but do not change the content in RAM, before VCC returns to normal level, reset should be invalid, and must keep certain time so that vibration is thought highly of starts also steady operation.

Model program storer ALE/PSENP0P1P2P3

Idle mode internal 11 Data Data Data Data

The outside 11 floating data address data of idle pattern

The inner 00 Data Data Data Data of power-down mode

The outside 00 floating Data Data data of power-down mode

Free time and power-down mode external pin state

The encryption of program store

AT89C51 can use and be programmed (P) by 3 encrypted bits LB1, LB2, LB3 on chip or do not programme (U) obtains the function shown in following table:

Encrypted bits protection function table

Program encrypted bits protect types

LB1LB2LB3

1UUU does not have program protection function

2

P

U

U forbids performing the content of MOVC instruction fetch internal program memory from external program memory

3PPU except on boast of one's bit of contribution except energy, also forbid that program verifies

4PPP, except above function, forbids outside execution simultaneously

When encrypted bits LB1 is programmed, between reset period, the logic level of EA end is sampled and latches, if micro-chip never resets after powering on, the initial value then latched is a randomized number, and till this randomized number can be saved in real reset, for making monolithic function normal operation, the logic level that the EA level being latched must be current with this pin is consistent always. In addition, encrypted bits can only be removed by the method that full wafer is wiped.

Flash dodges the programming of speed storer

There is the FlashPEROM of 4K byte AT89C51 micro-chip inside, has been in erase status (content of all storage unit is FFH) when this Flash storage array dispatches from the factory, and it can be programmed by user at any time. Programming interface can receive the permission programming signal of high-voltage (+12V) or low voltage (Vcc). Low voltage program pattern is suitable for user's In-circuit programming system, and high-voltage programming mode can be compatible with unversal EPROM programming device.

In AT89C51 micro-chip, some belongs to low voltage program mode, and some is then high-voltage programming mode. User can obtain this information from the model chip and the signature bytes read in chip. The program store array of AT89C51 adopts byte write mode to programme, a write byte every time, the PEROM program store in whole chip will write a non-empty words joint, it is necessary to use the mode of erasing by clear for the content of whole storer.

Programmed method

Before programming, first set address, data and control signal, the address of programming unit is added in the P2.0 P2.3 (11 bit address scopes are 0000H 0FFFH) of P1 mouth and P2 mouth, and data input from P0 mouth, the level of pin P2.6, P2.7 and P3.6, P3.7, PSEN is lower level, and RST keeps high level, and EA/Vpp pin is the input terminus of programming power supply, add program voltage on request, ALE/PROG pin input programming pulse (negative pulse). During programming, can adopting the clock oscillation device of 4 20MHz, AT89C51 programmed method is as follows:

1. in address wire, add the address signal wanting programming unit.

2. add the data byte to be write on the data line.

3. activate corresponding control signal.

4., when high-voltage programming mode, general/EA/Vpp end adds+12V program voltage.

5. often pair of Flash storage array writes a byte or often writes a program encrypted bits, adds an ALE/PROG programming pulse.

Change the address of programming unit and the data of write, repeat 15 steps, until all files programming terminates.

Each word write cycle is self timing, is usually about 1.5ms

Data query

AT89C51 micro-chip data query mode detects one and writes whether the cycle terminates, write in the cycle at one, as that byte of last write need to be read, the most significant digit (P0.7) of the data then read originally write the highest radix-minus-one complement of byte, and after the cycle of writing completes, effective data just appear on all output terminals, now, what can enter next byte writes the cycle, and the cycle of writing can carry out data query after starting at any time.

Ready/Busy: the progress of byte programming by RDY/BSY monitor signal output, during programming, ALE become high level " H " afterwards P3.4 end level drawn low, represent and programming state. After having programmed. P3.4 turns into high level and represents ready state.

Program verification and chip erase

If encrypted bits LB1, LB2 do not programme, then code data is read back the former data write by address and data line. Adopt lower invention circuit. The address of program store is inputted by the P2.0-P2.3 of P1 and P2 mouth, and data have P0 mouth to read, and the control signal of P2.6, P2.7 and P3.6, P3.7 keeps lower level, ALE and RST keeps high level. During verification, P0 mouth must connect the pull-up resistor of about 10K.

Encrypted bits not directly verifies, and the verification of encrypted bits is by verifying the School Affairs write state of storer.

Utilize the correct combination of control signal and keep the low level pulse width of ALE/ pin 10ms PEROM array (4k byte) and three encrypted bits full wafers to be wiped, any non-dummy cell is write " 1 " by array of code in sheet erase operation, and this step need to carry out before programming again.

Signature bytes and programming interface in read tablet

Having 3 signature bytes in AT89C51 micro-chip, address is 030H, 031H and 032H. For stating the manufacturer of this device, model and program voltage. The process of reading signature bytes and the normal verification of unit 030H, 031H and 032H are similar, only P3.6, P3.7 need to be kept lower level, and return of value meaning is as follows:

(030H)=1EH states that product is manufactured by ATMEL formula.

(031H)=51H is claimed as AT89C51 micro-chip.

(032H)=FFH is claimed as 12V program voltage.

(032H)=05H is claimed as 5V program voltage.

Programming interface: adopt control signal correct combination can to Flash dodge speed store battle array split in each code byte write and storer full wafer erasing, write cycles be self timing, after initialize, it completes being automatically timed to operation.

The limit parameter of AT89C51:

Limit parameter: working temperature ...-55 DEG C to+125 DEG C

Storage temperature ...-65 DEG C to+150 DEG C

Arbitrary pin voltage to ground ...-1.0Vto+7.0V

Most high working voltage ... 6.6V

Direct current outward current ... 15.0mA

Display circuit

In scm application system, if needing content only some letter of numerals sum of display, it may also be useful to LED charactron is that one is selected preferably. LED numeral method is clear, with low cost, flexible configuration, simple with interface microcontroller. LED charactron is by photodiode as the digital type display device showing field, wherein seven photodiode corresponding a��g tips of the brushstyle of a writing or painting formation " day " fonts respectively, and another photodiode Dp is as radix point. Therefore this kind of LED indicating meter is called seven segment digital tubes or eight segment numeral pipes.

LED charactron can be divided into common cathode type and the big class of common anode type two by the mode of connection in circuit, common anode type is connected together by the positive pole of each section of photodiode, as public end COM, public end COM connects high level, and each pen section of a��g, Dp connects control end by current limliting resistance. During certain section control end lower level, this section luminescence, not luminous during high level. Control a few sections of tip of the brushstyle of a writing or painting luminescences, just can demonstrate certain digital or character. Common cathode type is connected together by the negative pole of each section of photodiode, as public end COM ground connection, luminous when certain section connects high level by current limliting resistance.

Running in automatic charging equipment Controlling System is to be shown conveying, discharge, full material, empty material time, and the photodiode of free switching key and which bar production line of mark represents, the figure place of display is few, so just adopting the mode of static state display. When LED indicating meter works in static state display mode, everybody common cathode pole (or common-anode) links together and ground connection (or+5V); The section route selection (a ~ dp) of every exports with the latch of 8 respectively and is connected. So being called static state display. The display character of each LED is once determining, the output of respective latch will remain unchanged, until showing another character. Also just therefore like this, the brightness of static state display device is all higher. This kind of display mode interface programming is easy. If using I/O interface, then to be taken 48 I/O mouths, if using latch interface, then with 4 74LS373 chips. If indicating meter figure place increases, then static state display mode just cannot adapt to.

In invention, LED display circuit adopts 74LS377 driving mechanism and MC14511B decoder control LED charactron.

74LS377 chip is introduced

.D0��D7:8 signal input terminus.

.Q0��Q7:8 signal output terminal.

.CLK: clock signal input terminal.

.: latch and allow signal. When=0, the upper saltus step of CLK end squeezes into 8 latch by the data of 8 D input.

74LS377 truth table

CLKDQ

1XXQ0

0��11

0��00

X0XQ0

MC14511B chip is introduced

.A��D: four signal input terminus.

.a��g: seven signal output terminal.

.LT, BI: ground connection.

.LE: connect power supply.

LED interface circuit

LED display circuit adopts 74LS377 driving mechanism and MC14511B decoder control LED charactron. Two LED show the number of seconds of a production line working process. Two panels MC14511B is decoded into decimal system control LED display the Gao Siwei of P0 mouth and low four.

Control circuit

In field of electrical control or product, every occasion needing logic control, nearly all needs to use rly., applies, even each department of national economy from household electrical appliance to industrial or agricultural, be without being loseed. Rly. is a kind of change utilizing various physical quantity, electricity or non-electric charge quantity signalling are converted into electromagnetic force (having contact type) or make output state generation Spline smoothing (without contact type), thus impelled a kind of controlling elements of other device in same circuit or another circuit or device action by its contact or sudden change amount. Difference according to the physical quantity transformed; the rly. of various not congenerous can be formed; for various pilot circuit carries out signal transmission, amplification, conversion, interlocking etc.; thus control the device in main power circuit and auxiliary circuit or equipment carries out work by predetermined operation program, it is achieved the object of control and protection automatically. The excitation amount being converted or apply to be called in the electricity of rly. or non-electricity rly., when rly. is energized, reaches predetermined working position from a zero position, and the switching action of completing circuit, it is called the performance characteristics of rly., comprises adhesive. Not adhesive, keeps and release state. When input changes to the adhesive value higher than it or during lower than its releasing value, operation of relay, for having its contact closure of contact type rly. or disconnection, for rising to export without contact type rly., Spline smoothing occurs, provide certain logic variable with this.

Automatic charging equipment is that plastic pellet is delivered to a valve tube, and when carrying, valve tube closes closed, and during discharge, valve tube needs to open, and particle is delivered to discharge funnel. The present invention needs 2 Control alternating current contactors altogether, and one connects the electric motor driving and producing. Another is the directional valve of control operative orientation. Through considering to adopt the alternating-current relay of 4123 electrodeless 12V DC control 24V, and light coupled device P521 and MCU is utilized to separate. The P1 initial value of 89C51 is 0FFH, so adding one, a 74LS04 phase inverter makes rly. initially not produce to close, it may also be useful to MC1413 is passive drive device, and IN4007 forms the afterflow diode of rly..

Keyboard and display circuit

Keyboard can realize inputting data to micro-chip, transmitting the functions such as order in scm application system, is the main means of Human disturbance micro-chip. The present invention adopts 8255A to be I/O expansion.

Keyboard interface

The interface SCM system of non-coding keyboard and micro-chip keyboard used has coding keyboard and two kinds, non-coding keyboard.

Coding keyboard itself, except button, also comprises the hardware circuit producing key code, as long as pressing a certain key, just can produce the code of this key, being commonly referred to as key code, simultaneously, moreover it is possible to produce a pulse signal, to notify that CPU receives (input) key code. The use of this kind of keyboard is more convenient, does not also need to write a lot of program, but the hardware used is more complicated, uses also few in microcomputer control system.

Non-coding keyboard is the line-column matrix become by some key arrangement. The effect of button, just simply realizes switching on and off of contact, but a set of corresponding program must be had to coordinate with it, just can produce corresponding key code. Non-coding keyboard does not almost need what hardware circuit additional, at present, uses commonplace in microcomputer control system.

Use non-coding key to need the identification solving button with software, prevent from shaking and the work such as generation of key code.

Being provided with the non-coding keyboard that 6 row �� 5 arrange, wherein have 16 for numerical key 0��F, remaining is operating key, in order to issue various control command. The line of keyboard meets six line PC5��PC0 of 8155C mouth, and the row line of keyboard then connects 5 lines of 8155B mouth. When pressing without any key, the signal on all keyboard row lines is all high level. When there being button to press, just there will be the identification of key, prevent a series of problems such as shake and OK button code.

Recognition by pressing keys has various method, and this system is " line scanning " method only:

(1) determine whether to have button to press. CPU exports, by parallel mouth, the line that 000000 arrives keyboard, then detects the row line signal of keyboard. If not having key to press, then it is 11111. If there being any one button to press, then there is a certain bar row line to be 0, being also exactly when PB4��PB0 is not 11111, just indicate that key is pressed.

(2) the row, column position of button is determined by " line scanning ". So-called line scanning is exactly input 0 signal to every bar line successively, and all the other each provisional capitals input 1, and detects every time column signal corresponding when scanning. Invention 2 first exports 111110(PC5��PC0 at C mouth exactly), then it is 111101, until being finally 011111, and the B mouth corresponding to detecting every time inputs.

When only having key to press on certain row, this line inputs other behaviors 1 of 0(), on row export, 0 signal just can be detected. Do not have button to press if being input as in this line of 0, then the column signal received still is 1 entirely. Therefore, as long as writing down column signal is not that C mouth when 1 exports and the input of B mouth entirely, just can determine with the position of button. Pressing if being in the key that the 3rd row the 1st arranges in invention 2, then must be row output signal be 110111, the column signal detected be 11101. Corresponding to other row signal, column signal is all 11111. Like this, line scanning is passed through, so that it may to determine the row, column coordinate of button.

(3) determine whether to have multikey to press simultaneously. Sometimes more than one of the key once pressed, this is generally owing to mishandle causes, and is that being commonly referred to of should not occurring alters key. When this kind of situation occurs, so that it may can have and can obtain column signal more than once not for complete 1, at this moment just it is not easy to judge which key presses real needs. In order to process this kind of situation can take two kinds of ways: just one be line scanning must be sweep to last a line to terminate, instead of detect that column signal does not just terminate for when complete 1, to find to alter key; Two is in the event of altering key, and the simplest treating method is exactly that current line scanning does not include, then comes one time, is namely as the criterion with that key finally decontroled. In fact, owing to the speed of scanning is very fast, the situation really finding two keys simultaneously to press is little.

(4) key shake is eliminated. General button has the problem of shake when pressing, and namely the reed of key has slight spring when pressing, and just can reliably need to contact through an of short duration time. If carry out scanning it is possible to draw incorrect result when reed is shaken. Therefore, to be considered the problem of stabilization in a program. The simplest way is when having detected that key is pressed, and waits that (delay) for some time carries out " line scanning " again, and time of lag is 10��20ms. This solves by call subroutine, when there being display sub-routine in system, calls several display sub-routines and also can reach the object eliminating shake simultaneously.

8255A chip is introduced

Automatic feeding system has 8 buttons: " starting 1 " key and " starting 2 " key, the every minute and second that start two production lines select key, set of time plus/minus key, display production line state switching key, set of time key, time-switching key, owing to the parallel mouth of micro-chip is limited. Native system adopts 8255A to expand parallel mouth.

(1) internal structure of .8255A

The internal structure of 8255A is made up of following a few part:

A. there are 38 bit parallel I/O mouths the inside of Parallel I/O port A, B, C8255A: A mouth, B mouth, C mouth. 3 I/O mouths can be chosen as input aperture or delivery port by programming, but different on structure and function.

A mouth: containing 8 bit data output latch/snubbers and 8 input latches.

B mouth: containing 8 bit data output latch/snubbers and one 8 input latches (not latching).

C mouth: containing 8 bit data output latch/snubbers and one 8 input latches (not latching).

When data transmission does not need contact signal, these 3 ports can be used as input aperture or delivery port. When A mouth B mouth needs contact signal, C mouth can as the contact signal wire of A mouth and B mouth.

Three ports of b. work method control circuit: 8255A make to be divided into A, B two groups in use. A group comprises 8, A mouth and high 4: the B group of C mouth comprises 8, B mouth and C mouth is low 4. The pilot circuit of two groups has control register respectively, determines the mode of operation of two groups according to the control word of write, it is possible to C mouth each position " 1 " or clear " 0 ".

C. data bus snubber: data bus snubber is two-way 8 digit buffers of tri-state, is 8255A and the interface of single-chip data bus, and the D0��D7 of 8255A directly can be connected with the P0.0��P0.7 of AT89C51 micro-chip. The transmission of the input and output of data, control word and status information, is all undertaken by data bus snubber.

D. read/write control logic: the effect of 8255A read/write control logic accepts there is OFF signal the address from CPU and control bus, is transformed into various control command and delivers to data snubber and the pilot circuit of A group and B group, controls the operation of A, B, C3 port. 8255A has 40 pins, is generally biserial and directly inserts DIP encapsulation, three port lines that 40 pins can be divided into the data line being connected with CPU, address and control signal and be connected with peripherals.

.D0��D7: two-way three-state data bus.

: reset signal .RESET input, high level is effective. After reset, clear 0, the A mouth of control register, B mouth, C mouth are set to input mode.

.: sheet selects signal, input, Low level effective.

.: read signal, input, Low level effective. Time effective, CPU is allowed to be read data or status information by 8255AD0��D7.

.: write signal, input, Low level effective. Time effective, allow

: port control signal .A1A0 input. 2 can form four kinds of states, respectively addressing A mouth, B mouth, C mouth and control register

.PA0��PA7:A mouth data line, two-way.

.PB0��PB7:B mouth data line, two-way.

.PC0��PC7:C mouth data/signal wire, two-way. When 8255A works in mode 0, PC0��PC7 is divided into two groups of (often organizing 4) Parallel I/O data lines; When working in mode 1 or mode 2 as 8255A, PC0��PC7 is A mouth, B mouth provides contact signal.

A1A0 with, together with signal, it may be determined that the operational stage of 8255A, as shown in invent:

8255A function operates

A1A0

Operation

0

0

10

1

00

0

01

1

10

0

0A mouth �� data bus

B mouth �� data bus

C mouth �� data bus

Input operation

0

0

1

10

1

0

11

1

1

10

0

0

00

0

0

0 data bus �� A mouth

Data bus �� B mouth

Data bus �� C mouth

Data bus �� control mouth

Output operates

x

1

xx

1

xX

0

1x

1

11

0

0 data bus is high resistance state

Illegal state

Data bus is high resistance state

Forbid operation

8255A and AT89C51 interface circuit.

When connecting keyboard circuit and adopt 8255A to be expansion I/O mouth, a 74LS373 is added in centre, 74LS373 is the 8D latch of a tri-state door, it can expand input aperture as the one of AT89C51 outside, the principle of work of excuse circuit is after peripheral hardware is good data encasement, send the G end that a control signal is added to 373, namely end is latched, input data are latched in 373, synchronous signal is added to the interrupt request end of AT89C51 micro-chip, micro-chip response is interrupted, program below performing in interrupt service routine:

MOVDPTR, #0BFFFH

MOVXA, DPTR

Perform above Article 2 instruction time, P2.6=0, effectively, by or door after be added to 373 end, i.e. the tristate gate control end of 373, makes tri-state door unimpeded, and the data of latch are read in totalizer A.

Exterior storage device expansion circuit

There is the conveying of two production lines, discharge, full material, empty material in automatic charging equipment, totally 8 significant datas arranged need read/write, and can provide point protection, so just needing outer wealthy program store. Program store generally adopts from reading storer, because this kind of storer closes at power supply has no progeny, still can preserve program, and upon power-up of the system, CPU can take out these instructions and be re-executed. Read-only storage is called for short ROM. Information in ROM once after write, just can not arbitrarily change, particularly can not write new content in the process of program operation, therefore be referred to as read-only storage.

In ROM, written information is called ROM programming. Mode according to programming is different, and ROM is divided into following several:

(1) mask ROM programmes in the fabrication process. Because programming realizes with mask technique, therefore it is called mask ROM. This kind of chip-stored structure is simple, integrated level height, but due to mask technique owing to cost is higher, is therefore suitable only for production in enormous quantities.

(2) ROM(PROM able to programme)

It is do not have any program information that PROM chip dispatches from the factory, and is write with independent programmer by user, but PROM can only write once, after write content, just can not modify.

(3) EPROM

EPROM is with electrical signal programming, with the read-only storage chip of ultraviolet erasing. Interposition on chip shell is equipped with a circular window, penetrates just erasable original information by this window irradiation ultraviolet radiation.

(4) E2PROM

This is the programming of one electrical signal, and with the ROM chip of electrical signal erasing, what difference read-write operation and RAM memory to E2PROM almost do not have yet, and just the speed of write is slow, but can preserve information after power-off.

This invention adopts the expansion mode extending out E2PROM. E2PROM is that electro erasible programmable is from reading storer, its outstanding advantage is can Online Erasing and rewriting, need not could must wipe thorough with uviolizing as ERPOM, newer E2PROM product can automatically complete erasing when writing, and no longer need special programming power supply, it is possible to directly use+5V the power supply of SCM system.

Conventional E2PROM chip has 2816/1816A, 2817/2817A, 2864A. What the present invention adopted is by the expansion mode of 2864A.

2864A has four kinds of mode of operation:

(1) mode is maintained

When for high level, 2864A enters low consumption and maintains mode. Now, output line is high resistance state, and the electric current of chip is down to from 140mA and is maintained electric current 60mA.

(2) read mode

When being high level with being lower level, inner data snubber is opened, and data serve bus, now, can carry out reading operation.

(3) mode is write

2864A provides two kinds of data modes: byte write and page write

Page write: " page buffer " being provided with 16 bytes in 2864A sheet, and whole memory array is divided into 512 pages, every page of 16 bytes. Page differentiation can determine by high 9 of address, address wire low 4 in order to select one of address, 16 in page buffer unit. When writing mode, being lower level, at negative edge, address code A0��A12 is by latches in sheet, and when rising, data are latched. Also having a byte to load timer in limited time in sheet, as long as the time does not arrive, data can write page buffer randomly. In the process writing data continuously to page buffer, not worrying the benefit of timer meeting in limited time, because whenever negative edge, timer is automatically reset and restarts timing in limited time.

Byte writes: the process of byte write and the process of page write are similar, and difference only writes a byte, and timer just overflows in limited time.

(4) data query mode

Data query refers to whether the page memory cycle detecting in write operation with software completes.

During page stores, as 2864A performs reading operation, what so read is the byte of last write, if the dump work of chip does not complete, then the most significant digit reading data is the radix-minus-one complement originally writing byte most significant digit. Accordingly, whether the programming that CPU can judge terminates. If the data read are identical with the data of write, representing that chip has completed programming, CPU can continue to load lower page of data to 2864A.

When 2864A and interface microcontroller, the sheet of 2864A selects end to be connected with high address wire P2.7, and P2.7=0 just can choose 2864A, this kind of linear selection system determines 2864A corresponding multiple sets of address space, that is: 0000H��1FFFFH, 2000H��3FFFH, 4000H��5FFFH, 6000H��7FFFH. This 8K byte memory can be used as data-carrier store and uses, but after falling electricity, data are not lost. 2864A and AT89C51 interface circuit is such as invention: micro-chip is due to the restriction by number of pins, and data line and address wire are multiplexings, holds concurrently by P0 mouth and uses. In order to they are separated, so that with the correct connection of the extended chip outside single chip microcomputer, it is necessary to increase address latch in micro-chip outside. This present invention uses 74LS373. 74LS373 is a kind of 8D latch with tri-state door,

The function of its pin is as follows:

D7��D0:8 bit data input line

Q7��Q0:8 bit data output line

G: data input latch gating signal, high level is effective. When this signal is high level time, outside data are strobed into Internal latches, and during negative saltus step, latches data is in latch.

: data export and allow signal, Low level effective. When this signal is low level time, tri-state door is opened, and in latch, data output to DOL Data Output Line. When this signal is high level time, output line is high resistance state.

Guard the gate dog MAX813L circuit

Nearly all micro-chip all needs reset circuit, to the basic demand of reset circuit is: the energy reliable reset when micro-chip powers on, and can prevent program from disorderly flying to cause the data in EPROM to be modified when lower electricity; In addition, SCM system is operationally, due to the impact of the various factorss such as interference, likely occur that deadlock phenomenon causes the SCM system cannot normal operation, in order to overcome this phenomenon, except the dog timer of guarding the gate (some micro-chip is without dog timer of guarding the gate) making full use of micro-chip itself, also need additional dog circuit of guarding the gate; In addition, some SCM system also requires to be preserved by significant data falling electricity moment monolithic function, and because falling the generation of electricity, root is random often, and thus this type of SCM system needs power supply supervisory circuit, can inform micro-chip when falling electricity just generation. The MAX813L that MAXIM company releases can just meet these requirements.

MAX813L has biserial directly to insert and paster two kinds of packing forms, and its biserial is directly inserted as shown in inventing, pin function is as follows:

The 1. pin be hand-reset input, Low level effective; 2., 2. pin is respectively VDD-to-VSS; The 4. pin be power failure input; The 5. pin be that power failure exports; The 6. pin be dog input of guarding the gate, the 7. pin export for resetting, the 8. pin be that dog of guarding the gate exports.

The performance characteristics of MAX813L:

The internal structure frame invention of MAX813L is as shown in inventing, having following salient features feature: have following salient features feature by invention this chip known:

(1) reset output. System electrification, fall electricity and when service voltage reduces, the 7. pin produce to reset and export, typical case's value of reseting pulse width is 200ms, and high level is effective, and typical case's value of reset threshold is 4.65V.

(2) dog circuit of guarding the gate exports. If not triggering this circuit (namely the 6. pin no pulse input) in 1.6s, then the 8. pin export a low level signal.

(3) hand-reset input, Low level effective, namely the 1. pin input a lower level, then the 7. pin produce to reset and export.

(4) 1.25V threshold detector, the 4. pin be input, the 5. pin for exporting. When 4. pin voltage is lower than 1.25V, 5. pin export a low level signal.

The typical application circuit of MAX813L:

The typical application circuit of MAX813L is as shown in inventing. In invention micro-chip for the of AT89C51, MAX813L 1. pin with 8. pin be connected. 7. pin connect the resetting pin (the of AT89C51 9. pin) of micro-chip; 6. pin be connected with the P1.4 of micro-chip. In software inventions, the continuous output pulse signal of P1.4, if entering endless loop because of certain reason micro-chip, then P1.4 no pulse exports. So after 1.6s the of MAX813L 8. pin export lower level, this lower level is added to the 1. pin, makes MAX813L produce to reset and export, micro-chip is effectively resetted, breaks away from the predicament of endless loop. In addition, when voltage of supply is lower than threshold value 4.65V, MAX813L also produces to reset and exports, micro-chip is made to be in reset mode, do not perform any instruction, until voltage of supply recovers normal, can effectively prevent because of voltage of supply lower time micro-chip produce the action of mistake.

Power failure input PFI monitors the direct supply of non-voltage stabilizing by a resitstance voltage divider. When PFI is lower than 1.25V, power failure output pin the 5. pin PF0 become low, AT89C51 can be caused to interrupt, carry out power failure process, or significant data is preserved. Direct supply voltage-divider being received non-voltage stabilizing is in order to earlier to power failure alarm.

MAX813L is that the band that a volume is little, low in energy consumption, cost performance is high is guarded the gate the reset chip of dog and power supply monitoring function; Its uses simple, convenient, and the reset signal that it provides is high level, because of but be applied to the desirable chip that reset signal is the SCM system of high level occasion.

Program invention comprises master routine, interrupt routine, fault handling program, has used two timers and interrupt in system: timer 0 makes P1.7 produce pulse signal every 1.2s; Timer 1 produces the timing of 1s, and LED display is successively decreased. Fault handling program makes PC pointer jump back to the corresponding program section of original starting; Master routine completes the initialize of internal RAM data field, 8255 initialize, and wants to answer programsegment according to jumping to by key signals.

Claims (8)

1. falling under dot pattern, vibrator stopping work, the instruction entering power-down mode is the instruction that the last item is performed, and the content of ram in slice and specific function register is frozen before terminating power-down mode; The unique method exiting power-down mode is that hardware resets, after reset by redefining whole specific function register but do not change the content in RAM, before VCC returns to normal level, reset should be invalid, and must keep certain time so that vibration is thought highly of starts also steady operation;

Model program storer ALE/PSENP0P1P2P3

Idle mode internal 11 Data Data Data Data

The outside 11 floating data address data of idle pattern

The inner 00 Data Data Data Data of power-down mode

The outside 00 floating Data Data data of power-down mode

Free time and power-down mode external pin state

The encryption of program store

AT89C51 can use and be programmed (P) by 3 encrypted bits LB1, LB2, LB3 on chip or do not programme (U) obtains the function shown in following table:

Encrypted bits protection function table

Program encrypted bits protect types

LB1LB2LB3

1UUU does not have program protection function

2

P

U

U forbids performing the content of MOVC instruction fetch internal program memory from external program memory

3PPU except on boast of one's bit of contribution except energy, also forbid that program verifies

4PPP, except above function, forbids outside execution simultaneously

When encrypted bits LB1 is programmed, between reset period, the logic level of EA end is sampled and latches, if micro-chip never resets after powering on, the initial value then latched is a randomized number, and till this randomized number can be saved in real reset, for making monolithic function normal operation, the logic level that the EA level being latched must be current with this pin is consistent always; In addition, encrypted bits can only be removed by the method that full wafer is wiped;

Flash dodges the programming of speed storer

There is the FlashPEROM of 4K byte AT89C51 micro-chip inside, has been in erase status (content of all storage unit is FFH) when this Flash storage array dispatches from the factory, and it can be programmed by user at any time; Programming interface can receive the permission programming signal of high-voltage (+12V) or low voltage (Vcc); Low voltage program pattern is suitable for user's In-circuit programming system, and high-voltage programming mode can be compatible with unversal EPROM programming device;

In AT89C51 micro-chip, some belongs to low voltage program mode, and some is then high-voltage programming mode; User can obtain this information from the model chip and the signature bytes read in chip; The program store array of AT89C51 adopts byte write mode to programme, a write byte every time, the PEROM program store in whole chip will write a non-empty words joint, it is necessary to use the mode of erasing by clear for the content of whole storer;

Programmed method

Before programming, first set address, data and control signal, the address of programming unit is added in the P2.0 P2.3 (11 bit address scopes are 0000H 0FFFH) of P1 mouth and P2 mouth, and data input from P0 mouth, the level of pin P2.6, P2.7 and P3.6, P3.7, PSEN is lower level, and RST keeps high level, and EA/Vpp pin is the input terminus of programming power supply, add program voltage on request, ALE/PROG pin input programming pulse (negative pulse); During programming, can adopting the clock oscillation device of 4 20MHz, AT89C51 programmed method is as follows:

1. in address wire, add the address signal wanting programming unit;

2. add the data byte to be write on the data line;

3. activate corresponding control signal;

4., when high-voltage programming mode, general/EA/Vpp end adds+12V program voltage;

5. often pair of Flash storage array writes a byte or often writes a program encrypted bits, adds an ALE/PROG programming pulse;

Change the address of programming unit and the data of write, repeat 15 steps, until all files programming terminates;

Each word write cycle is self timing, is usually about 1.5ms

Data query

AT89C51 micro-chip data query mode detects one and writes whether the cycle terminates, write in the cycle at one, as that byte of last write need to be read, the most significant digit (P0.7) of the data then read originally write the highest radix-minus-one complement of byte, and after the cycle of writing completes, effective data just appear on all output terminals, now, what can enter next byte writes the cycle, and the cycle of writing can carry out data query after starting at any time.

2.Ready/Busy: the progress of byte programming by RDY/BSY monitor signal output, during programming, ALE become high level " H " afterwards P3.4 end level drawn low, represent and programming state; After having programmed; P3.4 turns into high level and represents ready state;

Program verification and chip erase

If encrypted bits LB1, LB2 do not programme, then code data is read back the former data write by address and data line; Adopt lower invention circuit; The address of program store is inputted by the P2.0-P2.3 of P1 and P2 mouth, and data have P0 mouth to read, and the control signal of P2.6, P2.7 and P3.6, P3.7 keeps lower level, ALE and RST keeps high level; During verification, P0 mouth must connect the pull-up resistor of about 10K;

Encrypted bits not directly verifies, and the verification of encrypted bits is by verifying the School Affairs write state of storer;

Utilize the correct combination of control signal and keep the low level pulse width of ALE/ pin 10ms PEROM array (4k byte) and three encrypted bits full wafers to be wiped, any non-dummy cell is write " 1 " by array of code in sheet erase operation, and this step need to carry out before programming again;

Signature bytes and programming interface in read tablet

Having 3 signature bytes in AT89C51 micro-chip, address is 030H, 031H and 032H; For stating the manufacturer of this device, model and program voltage; The process of reading signature bytes and the normal verification of unit 030H, 031H and 032H are similar, only P3.6, P3.7 need to be kept lower level, and return of value meaning is as follows:

(030H)=1EH states that product is manufactured by ATMEL formula;

(031H)=51H is claimed as AT89C51 micro-chip;

(032H)=FFH is claimed as 12V program voltage;

(032H)=05H is claimed as 5V program voltage;

Programming interface: adopt control signal correct combination can to Flash dodge speed store battle array split in each code byte write and storer full wafer erasing, write cycles be self timing, after initialize, it completes being automatically timed to operation;

The limit parameter of AT89C51:

Limit parameter: working temperature ...-55 DEG C to+125 DEG C

Storage temperature ...-65 DEG C to+150 DEG C

Arbitrary pin voltage to ground ...-1.0Vto+7.0V

Most high working voltage ... 6.6V

Direct current outward current ... 15.0mA

Display circuit

In scm application system, if needing content only some letter of numerals sum of display, it may also be useful to LED charactron is that one is selected preferably; LED numeral method is clear, with low cost, flexible configuration, simple with interface microcontroller; LED charactron is by photodiode as the digital type display device showing field, wherein seven photodiode corresponding a��g tips of the brushstyle of a writing or painting formation " day " fonts respectively, and another photodiode Dp is as radix point; Therefore this kind of LED indicating meter is called seven segment digital tubes or eight segment numeral pipes.

3.LED charactron can be divided into common cathode type and the big class of common anode type two by the mode of connection in circuit, common anode type is connected together by the positive pole of each section of photodiode, as public end COM, public end COM connects high level, and each pen section of a��g, Dp connects control end by current limliting resistance; During certain section control end lower level, this section luminescence, not luminous during high level; Control a few sections of tip of the brushstyle of a writing or painting luminescences, just can demonstrate certain digital or character; Common cathode type is connected together by the negative pole of each section of photodiode, as public end COM ground connection, luminous when certain section connects high level by current limliting resistance;

Running in automatic charging equipment Controlling System is to be shown conveying, discharge, full material, empty material time, and the photodiode of free switching key and which bar production line of mark represents, the figure place of display is few, so just adopting the mode of static state display; When LED indicating meter works in static state display mode, everybody common cathode pole (or common-anode) links together and ground connection (or+5V); The section route selection (a ~ dp) of every exports with the latch of 8 respectively and is connected; So being called static state display; The display character of each LED is once determining, the output of respective latch will remain unchanged, until showing another character; Also just therefore like this, the brightness of static state display device is all higher; This kind of display mode interface programming is easy; If using I/O interface, then to be taken 48 I/O mouths, if using latch interface, then with 4 74LS373 chips; If indicating meter figure place increases, then static state display mode just cannot adapt to;

In invention, LED display circuit adopts 74LS377 driving mechanism and MC14511B decoder control LED charactron;

74LS377 chip is introduced

.D0��D7:8 signal input terminus;

.Q0��Q7:8 signal output terminal;

.CLK: clock signal input terminal;

.: latch and allow signal; When=0, the upper saltus step of CLK end squeezes into 8 latch by the data of 8 D input;

74LS377 truth table

CLKDQ

1XXQ0

0��11

0��00

X0XQ0

MC14511B chip is introduced

.A��D: four signal input terminus;

.a��g: seven signal output terminal;

.LT, BI: ground connection;

.LE: connect power supply;

LED interface circuit

LED display circuit adopts 74LS377 driving mechanism and MC14511B decoder control LED charactron; Two LED show the number of seconds of a production line working process; Two panels MC14511B is decoded into decimal system control LED display the Gao Siwei of P0 mouth and low four;

Control circuit

In field of electrical control or product, every occasion needing logic control, nearly all needs to use rly., applies, even each department of national economy from household electrical appliance to industrial or agricultural, be without being loseed; Rly. is a kind of change utilizing various physical quantity, electricity or non-electric charge quantity signalling are converted into electromagnetic force (having contact type) or make output state generation Spline smoothing (without contact type), thus impelled a kind of controlling elements of other device in same circuit or another circuit or device action by its contact or sudden change amount; Difference according to the physical quantity transformed, the rly. of various not congenerous can be formed, for various pilot circuit carries out signal transmission, amplification, conversion, interlocking etc., thus control the device in main power circuit and auxiliary circuit or equipment carries out work by predetermined operation program, it is achieved the object of control and protection automatically; The excitation amount being converted or apply to be called in the electricity of rly. or non-electricity rly., when rly. is energized, reaches predetermined working position from a zero position, and the switching action of completing circuit, it is called the performance characteristics of rly., comprises adhesive; Not adhesive, keeps and release state; When input changes to the adhesive value higher than it or during lower than its releasing value, operation of relay, for having its contact closure of contact type rly. or disconnection, for rising to export without contact type rly., Spline smoothing occurs, provide certain logic variable with this;

Automatic charging equipment is that plastic pellet is delivered to a valve tube, and when carrying, valve tube closes closed, and during discharge, valve tube needs to open, and particle is delivered to discharge funnel; The present invention needs 2 Control alternating current contactors altogether, and one connects the electric motor driving and producing; Another is the directional valve of control operative orientation; Through considering to adopt the alternating-current relay of 4123 electrodeless 12V DC control 24V, and light coupled device P521 and MCU is utilized to separate; The P1 initial value of 89C51 is 0FFH, so adding one, a 74LS04 phase inverter makes rly. initially not produce to close, it may also be useful to MC1413 is passive drive device, and IN4007 forms the afterflow diode of rly.;

Keyboard and display circuit

Keyboard can realize inputting data to micro-chip, transmitting the functions such as order in scm application system, is the main means of Human disturbance micro-chip; The present invention adopts 8255A to be I/O expansion.

4. keyboard interface

The interface SCM system of non-coding keyboard and micro-chip keyboard used has coding keyboard and two kinds, non-coding keyboard;

Coding keyboard itself, except button, also comprises the hardware circuit producing key code, as long as pressing a certain key, just can produce the code of this key, being commonly referred to as key code, simultaneously, moreover it is possible to produce a pulse signal, to notify that CPU receives (input) key code; The use of this kind of keyboard is more convenient, does not also need to write a lot of program, but the hardware used is more complicated, uses also few in microcomputer control system;

Non-coding keyboard is the line-column matrix become by some key arrangement; The effect of button, just simply realizes switching on and off of contact, but a set of corresponding program must be had to coordinate with it, just can produce corresponding key code; Non-coding keyboard does not almost need what hardware circuit additional, at present, uses commonplace in microcomputer control system;

Use non-coding key to need the identification solving button with software, prevent from shaking and the work such as generation of key code;

Being provided with the non-coding keyboard that 6 row �� 5 arrange, wherein have 16 for numerical key 0��F, remaining is operating key, in order to issue various control command; The line of keyboard meets six line PC5��PC0 of 8155C mouth, and the row line of keyboard then connects 5 lines of 8155B mouth; When pressing without any key, the signal on all keyboard row lines is all high level; When there being button to press, just there will be the identification of key, prevent a series of problems such as shake and OK button code;

Recognition by pressing keys has various method, and this system is " line scanning " method only:

(1) determine whether to have button to press; CPU exports, by parallel mouth, the line that 000000 arrives keyboard, then detects the row line signal of keyboard; If not having key to press, then it is 11111; If there being any one button to press, then there is a certain bar row line to be 0, being also exactly when PB4��PB0 is not 11111, just indicate that key is pressed;

(2) the row, column position of button is determined by " line scanning "; So-called line scanning is exactly input 0 signal to every bar line successively, and all the other each provisional capitals input 1, and detects every time column signal corresponding when scanning; Invention 2 first exports 111110(PC5��PC0 at C mouth exactly), then it is 111101, until being finally 011111, and the B mouth corresponding to detecting every time inputs;

When only having key to press on certain row, this line inputs other behaviors 1 of 0(), on row export, 0 signal just can be detected; Do not have button to press if being input as in this line of 0, then the column signal received still is 1 entirely; Therefore, as long as writing down column signal is not that C mouth when 1 exports and the input of B mouth entirely, just can determine with the position of button; Pressing if being in the key that the 3rd row the 1st arranges in invention 2, then must be row output signal be 110111, the column signal detected be 11101; Corresponding to other row signal, column signal is all 11111; Like this, line scanning is passed through, so that it may to determine the row, column coordinate of button;

(3) determine whether to have multikey to press simultaneously; Sometimes more than one of the key once pressed, this is generally owing to mishandle causes, and is that being commonly referred to of should not occurring alters key; When this kind of situation occurs, so that it may can have and can obtain column signal more than once not for complete 1, at this moment just it is not easy to judge which key presses real needs; In order to process this kind of situation can take two kinds of ways: just one be line scanning must be sweep to last a line to terminate, instead of detect that column signal does not just terminate for when complete 1, to find to alter key; Two is in the event of altering key, and the simplest treating method is exactly that current line scanning does not include, then comes one time, is namely as the criterion with that key finally decontroled; In fact, owing to the speed of scanning is very fast, the situation really finding two keys simultaneously to press is little;

(4) key shake is eliminated; General button has the problem of shake when pressing, and namely the reed of key has slight spring when pressing, and just can reliably need to contact through an of short duration time; If carry out scanning it is possible to draw incorrect result when reed is shaken; Therefore, to be considered the problem of stabilization in a program; The simplest way is when having detected that key is pressed, and waits that (delay) for some time carries out " line scanning " again, and time of lag is 10��20ms; This solves by call subroutine, when there being display sub-routine in system, calls several display sub-routines and also can reach the object eliminating shake simultaneously;

8255A chip is introduced

Automatic feeding system has 8 buttons: " starting 1 " key and " starting 2 " key, the every minute and second that start two production lines select key, set of time plus/minus key, display production line state switching key, set of time key, time-switching key, owing to the parallel mouth of micro-chip is limited; Native system adopts 8255A to expand parallel mouth.

5.(1) the internal structure of .8255A

The internal structure of 8255A is made up of following a few part:

A. there are 38 bit parallel I/O mouths the inside of Parallel I/O port A, B, C8255A: A mouth, B mouth, C mouth; 3 I/O mouths can be chosen as input aperture or delivery port by programming, but different on structure and function;

A mouth: containing 8 bit data output latch/snubbers and 8 input latches;

B mouth: containing 8 bit data output latch/snubbers and one 8 input latches (not latching);

C mouth: containing 8 bit data output latch/snubbers and one 8 input latches (not latching);

When data transmission does not need contact signal, these 3 ports can be used as input aperture or delivery port; When A mouth B mouth needs contact signal, C mouth can as the contact signal wire of A mouth and B mouth;

Three ports of b. work method control circuit: 8255A make to be divided into A, B two groups in use; A group comprises 8, A mouth and high 4: the B group of C mouth comprises 8, B mouth and C mouth is low 4; The pilot circuit of two groups has control register respectively, determines the mode of operation of two groups according to the control word of write, it is possible to C mouth each position " 1 " or clear " 0 ";

C. data bus snubber: data bus snubber is two-way 8 digit buffers of tri-state, is 8255A and the interface of single-chip data bus, and the D0��D7 of 8255A directly can be connected with the P0.0��P0.7 of AT89C51 micro-chip; The transmission of the input and output of data, control word and status information, is all undertaken by data bus snubber;

D. read/write control logic: the effect of 8255A read/write control logic accepts there is OFF signal the address from CPU and control bus, is transformed into various control command and delivers to data snubber and the pilot circuit of A group and B group, controls the operation of A, B, C3 port; 8255A has 40 pins, is generally biserial and directly inserts DIP encapsulation, three port lines that 40 pins can be divided into the data line being connected with CPU, address and control signal and be connected with peripherals;

.D0��D7: two-way three-state data bus;

.RESET: reset signal, input, high level is effective; After reset, clear 0, the A mouth of control register, B mouth, C mouth are set to input mode;

.: sheet selects signal, input, Low level effective;

.: read signal, input, Low level effective; Time effective, CPU is allowed to be read data or status information by 8255AD0��D7;

.: write signal, input, Low level effective; Time effective, allow

: port control signal .A1A0 input; 2 can form four kinds of states, respectively addressing A mouth, B mouth, C mouth and control register

.PA0��PA7:A mouth data line, two-way;

.PB0��PB7:B mouth data line, two-way;

.PC0��PC7:C mouth data/signal wire, two-way; When 8255A works in mode 0, PC0��PC7 is divided into two groups of (often organizing 4) Parallel I/O data lines; When working in mode 1 or mode 2 as 8255A, PC0��PC7 is A mouth, B mouth provides contact signal;

A1A0 with, together with signal, it may be determined that the operational stage of 8255A, as shown in invent:

8255A function operates

A1A0

Operation

0

0

10

1

00

0

01

1

10

0

0A mouth �� data bus

B mouth �� data bus

C mouth �� data bus

Input operation

0

0

1

10

1

0

11

1

1

10

0

0

00

0

0

0 data bus �� A mouth

Data bus �� B mouth

Data bus �� C mouth

Data bus �� control mouth

Output operates

x

1

xx

1

xX

0

1x

1

11

0

0 data bus is high resistance state

Illegal state

Data bus is high resistance state

Forbid operation

8255A and AT89C51 interface circuit.

6. when connecting keyboard circuit and adopt 8255A to be expansion I/O mouth, a 74LS373 is added in centre, 74LS373 is the 8D latch of a tri-state door, it can expand input aperture as the one of AT89C51 outside, the principle of work of excuse circuit is after peripheral hardware is good data encasement, send the G end that a control signal is added to 373, namely end is latched, input data are latched in 373, synchronous signal is added to the interrupt request end of AT89C51 micro-chip, micro-chip response is interrupted, program below performing in interrupt service routine:

MOVDPTR, #0BFFFH

MOVXA, DPTR

Perform above Article 2 instruction time, P2.6=0, effectively, by or door after be added to 373 end, i.e. the tristate gate control end of 373, makes tri-state door unimpeded, and the data of latch are read in totalizer A;

Exterior storage device expansion circuit

There is the conveying of two production lines, discharge, full material, empty material in automatic charging equipment, totally 8 significant datas arranged need read/write, and can provide point protection, so just needing outer wealthy program store; Program store generally adopts from reading storer, because this kind of storer closes at power supply has no progeny, still can preserve program, and upon power-up of the system, CPU can take out these instructions and be re-executed; Read-only storage is called for short ROM; Information in ROM once after write, just can not arbitrarily change, particularly can not write new content in the process of program operation, therefore be referred to as read-only storage;

In ROM, written information is called ROM programming; Mode according to programming is different, and ROM is divided into following several:

(1) mask ROM programmes in the fabrication process; Because programming realizes with mask technique, therefore it is called mask ROM; This kind of chip-stored structure is simple, integrated level height, but due to mask technique owing to cost is higher, is therefore suitable only for production in enormous quantities;

(2) ROM(PROM able to programme)

It is do not have any program information that PROM chip dispatches from the factory, and is write with independent programmer by user, but PROM can only write once, after write content, just can not modify;

(3) EPROM

EPROM is with electrical signal programming, with the read-only storage chip of ultraviolet erasing; Interposition on chip shell is equipped with a circular window, penetrates just erasable original information by this window irradiation ultraviolet radiation;

(4) E2PROM

This is the programming of one electrical signal, and with the ROM chip of electrical signal erasing, what difference read-write operation and RAM memory to E2PROM almost do not have yet, and just the speed of write is slow, but can preserve information after power-off;

This invention adopts the expansion mode extending out E2PROM; E2PROM is that electro erasible programmable is from reading storer, its outstanding advantage is can Online Erasing and rewriting, need not could must wipe thorough with uviolizing as ERPOM, newer E2PROM product can automatically complete erasing when writing, and no longer need special programming power supply, it is possible to directly use+5V the power supply of SCM system;

Conventional E2PROM chip has 2816/1816A, 2817/2817A, 2864A; What the present invention adopted is by the expansion mode of 2864A.

7.2864A has four kinds of mode of operation:

(1) mode is maintained

When for high level, 2864A enters low consumption and maintains mode; Now, output line is high resistance state, and the electric current of chip is down to from 140mA and is maintained electric current 60mA;

(2) read mode

When being high level with being lower level, inner data snubber is opened, and data serve bus, now, can carry out reading operation;

(3) mode is write

2864A provides two kinds of data modes: byte write and page write

Page write: " page buffer " being provided with 16 bytes in 2864A sheet, and whole memory array is divided into 512 pages, every page of 16 bytes; Page differentiation can determine by high 9 of address, address wire low 4 in order to select one of address, 16 in page buffer unit; When writing mode, being lower level, at negative edge, address code A0��A12 is by latches in sheet, and when rising, data are latched; Also having a byte to load timer in limited time in sheet, as long as the time does not arrive, data can write page buffer randomly; In the process writing data continuously to page buffer, not worrying the benefit of timer meeting in limited time, because whenever negative edge, timer is automatically reset and restarts timing in limited time;

Byte writes: the process of byte write and the process of page write are similar, and difference only writes a byte, and timer just overflows in limited time;

(4) data query mode

Data query refers to whether the page memory cycle detecting in write operation with software completes;

During page stores, as 2864A performs reading operation, what so read is the byte of last write, if the dump work of chip does not complete, then the most significant digit reading data is the radix-minus-one complement originally writing byte most significant digit; Accordingly, whether the programming that CPU can judge terminates; If the data read are identical with the data of write, representing that chip has completed programming, CPU can continue to load lower page of data to 2864A;

When 2864A and interface microcontroller, the sheet of 2864A selects end to be connected with high address wire P2.7, and P2.7=0 just can choose 2864A, this kind of linear selection system determines 2864A corresponding multiple sets of address space, that is: 0000H��1FFFFH, 2000H��3FFFH, 4000H��5FFFH, 6000H��7FFFH; This 8K byte memory can be used as data-carrier store and uses, but after falling electricity, data are not lost; 2864A and AT89C51 interface circuit is such as invention: micro-chip is due to the restriction by number of pins, and data line and address wire are multiplexings, holds concurrently by P0 mouth and uses; In order to they are separated, so that with the correct connection of the extended chip outside single chip microcomputer, it is necessary to increase address latch in micro-chip outside; This present invention uses 74LS373; 74LS373 is a kind of 8D latch with tri-state door,

The function of its pin is as follows:

D7��D0:8 bit data input line

Q7��Q0:8 bit data output line

G: data input latch gating signal, high level is effective; When this signal is high level time, outside data are strobed into Internal latches, and during negative saltus step, latches data is in latch;

: data export and allow signal, Low level effective; When this signal is low level time, tri-state door is opened, and in latch, data output to DOL Data Output Line; When this signal is high level time, output line is high resistance state.

8. guard the gate dog MAX813L circuit

Nearly all micro-chip all needs reset circuit, to the basic demand of reset circuit is: the energy reliable reset when micro-chip powers on, and can prevent program from disorderly flying to cause the data in EPROM to be modified when lower electricity; In addition, SCM system is operationally, due to the impact of the various factorss such as interference, likely occur that deadlock phenomenon causes the SCM system cannot normal operation, in order to overcome this phenomenon, except the dog timer of guarding the gate (some micro-chip is without dog timer of guarding the gate) making full use of micro-chip itself, also need additional dog circuit of guarding the gate; In addition, some SCM system also requires to be preserved by significant data falling electricity moment monolithic function, and because falling the generation of electricity, root is random often, and thus this type of SCM system needs power supply supervisory circuit, can inform micro-chip when falling electricity just generation; The MAX813L that MAXIM company releases can just meet these requirements;

MAX813L has biserial directly to insert and paster two kinds of packing forms, and its biserial is directly inserted as shown in inventing, pin function is as follows:

The 1. pin be hand-reset input, Low level effective; 2., 2. pin is respectively VDD-to-VSS; The 4. pin be power failure input; The 5. pin be that power failure exports; The 6. pin be dog input of guarding the gate, the 7. pin export for resetting, the 8. pin export for dog of guarding the gate;

The performance characteristics of MAX813L:

The internal structure frame invention of MAX813L is as shown in inventing, having following salient features feature: have following salient features feature by invention this chip known:

(1) reset output; System electrification, fall electricity and when service voltage reduces, the 7. pin produce to reset and export, typical case's value of reseting pulse width is 200ms, and high level is effective, and typical case's value of reset threshold is 4.65V;

(2) dog circuit of guarding the gate exports; If not triggering this circuit (namely the 6. pin no pulse input) in 1.6s, then the 8. pin export a low level signal;

(3) hand-reset input, Low level effective, namely the 1. pin input a lower level, then the 7. pin produce to reset and export;

(4) 1.25V threshold detector, the 4. pin be input, the 5. pin for exporting; When 4. pin voltage is lower than 1.25V, 5. pin export a low level signal;

The typical application circuit of MAX813L:

The typical application circuit of MAX813L is as shown in inventing; In invention micro-chip for the of AT89C51, MAX813L 1. pin with 8. pin be connected; 7. pin connect the resetting pin (the of AT89C51 9. pin) of micro-chip; 6. pin be connected with the P1.4 of micro-chip; In software inventions, the continuous output pulse signal of P1.4, if entering endless loop because of certain reason micro-chip, then P1.4 no pulse exports; So after 1.6s the of MAX813L 8. pin export lower level, this lower level is added to the 1. pin, makes MAX813L produce to reset and export, micro-chip is effectively resetted, breaks away from the predicament of endless loop; In addition, when voltage of supply is lower than threshold value 4.65V, MAX813L also produces to reset and exports, micro-chip is made to be in reset mode, do not perform any instruction, until voltage of supply recovers normal, can effectively prevent because of voltage of supply lower time micro-chip produce the action of mistake;

Power failure input PFI monitors the direct supply of non-voltage stabilizing by a resitstance voltage divider; When PFI is lower than 1.25V, power failure output pin the 5. pin PF0 become low, AT89C51 can be caused to interrupt, carry out power failure process, or significant data is preserved; Direct supply voltage-divider being received non-voltage stabilizing is in order to earlier to power failure alarm;

MAX813L is that the band that a volume is little, low in energy consumption, cost performance is high is guarded the gate the reset chip of dog and power supply monitoring function; Its uses simple, convenient, and the reset signal that it provides is high level, because of but be applied to the desirable chip that reset signal is the SCM system of high level occasion;

Program invention comprises master routine, interrupt routine, fault handling program, has used two timers and interrupt in system: timer 0 makes P1.7 produce pulse signal every 1.2s; Timer 1 produces the timing of 1s, and LED display is successively decreased; Fault handling program makes PC pointer jump back to the corresponding program section of original starting; Master routine completes the initialize of internal RAM data field, 8255 initialize, and wants to answer programsegment according to jumping to by key signals.