CN105633027A - Fan-out wafer level chip packaging structure and manufacturing method thereof - Google Patents

Fan-out wafer level chip packaging structure and manufacturing method thereof Download PDF

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Publication number
CN105633027A
CN105633027A CN201410617786.1A CN201410617786A CN105633027A CN 105633027 A CN105633027 A CN 105633027A CN 201410617786 A CN201410617786 A CN 201410617786A CN 105633027 A CN105633027 A CN 105633027A
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China
Prior art keywords
chip
power transistor
electrically connected
demarcation strip
encapsulating structure
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Granted
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CN201410617786.1A
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Chinese (zh)
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CN105633027B (en
Inventor
谢智正
许修文
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Wuxi Super Gem Semiconductor Co Ltd
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Wuxi Super Gem Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/24247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

Disclosed are a fan-out wafer level chip packaging structure and a manufacturing method thereof. The manufacturing method thereof comprises the steps of providing a carrier plate having a peelable adhesive layer; attaching a plurality of chips onto the peelable adhesive layer; coating joint glue to the back of each chip; providing a conductive cover covering all the chips which are spaced apart from one another by a plurality of partition plates in the conductive cover; injecting a mold sealing colloid into the conductive cover and performing a curing production process to form a molded body; separating the molded body from the carrier plate, and forming a circuit connecting layer to the active surfaces of the chips so as to connect the chips; and afterwards, performing a cutting step to dividing the molded body into a plurality of packaging structures. In the manufacturing method of the chip packaging structure, the conductive cover is used for covering the chips, then the mold sealing colloid is injected into gaps between the chips and the conductive cover for curing, the size of the packaging structures can be controlled, and therefore, the molded body is no longer required to be thinned.

Description

Fan-out wafer level chip-packaging structure and manufacture method thereof
Technical field
The present invention relates to a kind of semiconductor packages manufacturing process, particularly relate to a kind of fan-out wafer level chip-packaging structure and manufacture method thereof.
Background technology
Along with portable and Wearable electronic product development, exploitation have high-effect, volume is little, at high speed, high-quality and polyfunctional product become trend. In order to make the overall dimensions of consumer electronic product towards miniaturization, crystal wafer chip dimension encapsulation (WaferLevelChipScalePackage, WLCSP) manufacturing process become when carrying out chip package through frequently with technological means.
The maximum difference of crystal wafer chip dimension encapsulation manufacturing process and previous technology is in that, crystal wafer chip dimension encapsulation manufacturing process is directly to be packaged manufacturing process on wafer, and in the lump IC chip (IC chip) is completed encapsulation, but not after elder generation's cutting crystal wafer, more individually IC chip is assembled. After carrying out crystal wafer chip dimension encapsulation manufacturing process, the size of finished product is completely equivalent or less times greater than chip size. But, crystal wafer chip dimension encapsulation manufacturing process but limits the transmutability of configuration (layout) fan-out (Fan-Out). Therefore, industry also develops fan-out wafer level encapsulation (Fan-OutWLP) manufacturing process now, to provide more various and elastic routing patterns, makes circuit board surface adhesion operation relatively simple, improves yield.
In the patent No. it is: in the U. S. application of US7759163, open a kind of semiconductor module manufacture method. First more than two semiconductor chips being positioned on carrier are provided, then cover moulding material to form molding body. Then, need thinning molding body until exposing semiconductor chip, then semiconductor chip is detached from the carrier. But, it is shaped moulding bodies and carries out thinning again, it is easy to leave cull in semiconductor chip surface. Further, if the height of semiconductor chip is inconsistent, when thinning molding body, it is possible to semiconductor chip surface is caused damage. It addition, utilize drilling technique to output passage in moulding bodies, being then filled with conductive material, guide the backplate of semiconductor chip to active surface, manufacturing process is too complicated.
Summary of the invention
The technical problem to be solved is in that, a kind of fan-out wafer level chip-packaging structure and manufacture method thereof are provided for the deficiencies in the prior art, it encapsulates the chip being inverted on loading plate by means of conductive cover, can remove from and follow-up moulding bodies carry out thinning manufacturing process. Additionally, in encapsulating structure provided by the invention, multiple chips can coordinate circuit articulamentum to be electrically connected by means of conductive cover.
The technical problem to be solved is achieved by the following technical solution:
The manufacture method of a kind of chip-packaging structure, comprises the following steps; First, it is provided that a loading plate, loading plate has loading end, and loading end is formed peelable glue-line; Arranging multiple chip on this peelable glue-line, each of which chip has an active surface and a back side, and the active surface of these chips is attached on peelable glue-line; Coating engages glue in the back side of chip; Thering is provided conductive cover, conductive cover has base plate and the multiple demarcation strips being positioned on base plate, and these demarcation strips form multiple accommodating area; Attaching conductive cover on loading end to cover these chips, wherein these chips lay respectively in accommodating area and spaced with demarcation strip; Then, molding colloid is injected in conductive cover, to fill the gap between demarcation strip and chip; Perform a solidification manufacturing process, to form moulding bodies; Splitting die plastomer and loading plate, wherein the active surface of each chip is positioned at the first surface of moulding bodies; Form the connection layer first surface in moulding bodies to connect these chips; Afterwards, performing a cutting step, so that moulding bodies to be separated into multiple encapsulating structure, wherein each encapsulating structure has the line layer being cut the conduction rack formed by conductive cover with being formed by the cutting of connection layer.
The present invention provides a kind of encapsulating structure, it is adaptable to a voltage conversion circuit, including a conduction rack, one first power transistor, one second power transistor and a line layer; Conduction rack has bottom with the first demarcation strip to form the first accommodating area and the second accommodating area, first demarcation strip is between the first accommodating area and the second accommodating area, and bottom is divided into the first conduction region and second conduction region of mutually insulated, wherein the first demarcation strip and the second conduction region are electrically connected; First power transistor packages is in the first accommodating area, and the drain electrode of the first power transistor is electrically connected to the first conduction region; Second power transistor packages is in the second accommodating area, and the drain electrode of the second power transistor is electrically connected to the second conduction region; Line layer is electrically connected the first active surface of the first power transistor and the second active surface of the second power transistor, wherein the second active surface copline of the end face of the first demarcation strip, the first active surface of the first power transistor and the second power transistor, the source electrode of the first power transistor is electrically connected to the drain electrode of the second power transistor via the first demarcation strip and the second conduction region.
The present invention also provides for a kind of encapsulating structure, suitable in a voltage conversion circuit, described encapsulating structure includes: a conduction rack, have bottom one with one first demarcation strip to form one first accommodating area and one second accommodating area, this first demarcation strip is between this first accommodating area and this second accommodating area, being divided into one first conduction region and one second conduction region of mutually insulated bottom this, wherein this first demarcation strip is electrically connected with this second conduction region; One first power transistor, is packaged in this first accommodating area, and the drain electrode of this first power transistor is electrically connected to this first conduction region; One control chip, is packaged in this first accommodating area, and this control chip is electrically insulated from this first conduction region; One second power transistor, is packaged in this second accommodating area, and the drain electrode of this first power transistor is electrically connected to this second conduction region; And a line layer, it is formed on this control chip, one first active surface of this first power transistor and one second active surface of this second power transistor to be electrically connected this control chip, this first power transistor and this second power transistor; Wherein, the end face of this first demarcation strip, this first power transistor the second active surface copline of the first active surface and this second power transistor, this first demarcation strip is between this first power transistor and this second power transistor, and the source electrode of this first power transistor is electrically connected to the drain electrode of this second power transistor via this first demarcation strip and this second conduction region.
In the manufacture method of the chip-packaging structure provided in the embodiment of the present invention, after utilizing conductive cover to cover chip, again molding colloid injected the gap between chip and conductive cover and solidify, the size of encapsulating structure can be controlled, therefore need not again moulding bodies be carried out thinning. It addition, when moulding bodies is performed cutting step, different encapsulating structures can be formed from depth of cut by means of changing the position cut.
In order to be able to be further understood that inventive feature and technology contents, refer to the detailed description below in connection with the present invention and accompanying drawing, but accompanying drawing only provides reference and use is described, be not used for the present invention is any limitation as.
Accompanying drawing explanation
Fig. 1 is the flow chart of the manufacture method of the fan-out wafer level chip-packaging structure of the embodiment of the present invention;
Fig. 2 is the partial cutaway schematic of the loading plate of the embodiment of the present invention;
Fig. 3 A is the chip-packaging structure of embodiment of the present invention schematic top plan view in the step S101 of Fig. 1;
Fig. 3 B is Fig. 3 A generalized section along H-H hatching;
Fig. 4 is the encapsulating structure of embodiment of the present invention partial cutaway schematic in the step of Fig. 1;
Fig. 5 A is the encapsulating structure of embodiment of the present invention schematic top plan view in the step of Fig. 1;
Fig. 5 B is Fig. 5 A generalized section along I-I hatching;
Fig. 5 C is the encapsulating structure of embodiment of the present invention partial cutaway schematic in the step of Fig. 1;
Fig. 6 is the encapsulating structure of embodiment of the present invention partial cutaway schematic in the step of Fig. 1;
Fig. 7 is the encapsulating structure of embodiment of the present invention partial cutaway schematic in the step of Fig. 1;
Fig. 8 is the partial cutaway schematic in the encapsulating structure of embodiment of the present invention step before forming connection layer;
Fig. 9 is the partial cutaway schematic in the encapsulating structure of embodiment of the present invention step before forming connection layer;
Figure 10 is the encapsulating structure of embodiment of the present invention partial cutaway schematic in the step forming connection layer;
Figure 11 is the encapsulating structure of embodiment of the present invention partial cutaway schematic in the step forming connection layer;
Figure 12 A is the encapsulating structure of embodiment of the present invention schematic top plan view in the step of Fig. 1;
Figure 12 B is that the chip-packaging structure of embodiment of the present invention part section before the step S109 of Fig. 1 cuts is intended to;
Figure 13 is the generalized section after the step S109 cutting of Fig. 1 of the encapsulating structure of a present invention wherein embodiment;
Figure 14 A is the schematic diagram that the encapsulating structure of the embodiment of the present invention is applied in circuit;
Figure 14 B is the schematic top plan view of the encapsulating structure of the embodiment of the present invention;
Figure 15 A is the schematic diagram that the encapsulating structure of another embodiment of the present invention is applied in circuit;
Figure 15 B is the schematic top plan view of the encapsulating structure of another embodiment of the present invention;
Figure 16 A is the schematic diagram that the encapsulating structure of the embodiment of the present invention is applied in circuit;
Figure 16 B is the schematic top plan view of the encapsulating structure of the embodiment of the present invention;
Figure 17 A is the encapsulating structure of another embodiment of the present invention schematic top plan view in the step of Fig. 1;
Figure 17 B is the schematic top plan view of the encapsulating structure of another embodiment of the present invention;
Figure 18 A is the encapsulating structure of further embodiment of this invention schematic top plan view in the step of Fig. 1;
Figure 18 B is the schematic top plan view of the encapsulating structure of further embodiment of this invention.
[description of reference numerals]
Loading plate 1
Loading end 1a
Peelable glue-line 2
First chip 3
First active surface 3a
Second active surface 4a
First back side 3b
Second back side 4b
Second chip 4,41
3rd chip 42
Control chip 30
Engage glue 5
Conductive cover 6
Base plate 60
Hole for injecting glue 600
First surface 60a
Second surface 60b
First conduction region 60c
Second conduction region 60d
Cutting mark 601
Cutting groove 602
Insulation tank 603
Demarcation strip 61
End face 610
First demarcation strip 61a
Second demarcation strip 61b
3rd demarcation strip 61c
Accommodating area 620
First accommodating area 620a
Second accommodating area 620b
Frame 62
Molding colloid 7
First molding body 7a
Second molding body 7b
Moulding bodies M1
First encapsulating structure M1 '
Encapsulating structure M2, M3, M4, M5
Substrate 8
Patterning protective layer 9
Opening 9a��9f
Projection underlying metal pad 10a��10f
Conductor layer 11
Weld pad 12a��12f, 42a
First line of cut 20a, 21a, 22a
Second line of cut 20b, 21b, 22b
Process step S100��S109
Detailed description of the invention
The following is by means of specific instantiation so that the embodiment of " fan-out wafer level chip-packaging structure and manufacture method thereof " described in the present invention to be described, those of ordinary skill in the art the content described in this specification can will readily appreciate that advantages of the present invention and effect. The present invention also can be implemented by means of other different specific embodiments or be applied, and the every details in this specification also based on different viewpoints and application, can carry out various modification and amendment under without departing from the spirit. It addition, the accompanying drawing of the present invention is only simple declaration, not describe according to actual size, that is unreacted goes out the actual size constituted of being correlated with, and hereby give notice that. Following embodiment will be explained in further detail the correlation technique content of the present invention, but described content be not used to the technology category of the restriction present invention.
Referring to Fig. 1, it is the flow chart of manufacture method of fan-out wafer level chip-packaging structure of one embodiment of the invention. The manufacture method of the fan-out wafer level chip-packaging structure that the embodiment of the present invention provides can be applicable to the encapsulation of chip.
In the step s 100, it is provided that a loading plate. Loading plate has a loading end, and loading end is formed peelable glue-line. In step S101, arranging multiple chip on peelable glue-line, each of which chip has active surface and the back side, and the active surface of these chips is attached on peelable glue-line. In step s 102, coating engages glue in the back side of each chip. In step s 103, it is provided that conductive cover, conductive cover has base plate and the multiple demarcation strips being positioned on base plate, and these demarcation strips form multiple accommodating area.
In step S104, attaching conductive cover on loading end to cover all chips, wherein these chips are to lay respectively in accommodating area, and spaced with these demarcation strips. In step S105, inject molding colloid in conductive cover, to fill the gap between these demarcation strip and chips. In step s 106, perform to solidify manufacturing process, form a moulding bodies. In step s 107, splitting die plastomer and loading plate, wherein the active surface of each chip is in the upper surface of moulding bodies.
Step S108 forms connection layer in the upper surface of moulding bodies, to connect these chips and outside line. In step S109, performing cutting step, so that moulding bodies to be separated into multiple encapsulating structure, wherein each encapsulating structure has the line layer being cut the conduction rack formed by conductive cover with being formed by the cutting of connection layer.
Hereinafter will further illustrate the details of each step in Fig. 1 with example. Please coordinate with reference to Fig. 2, the partial cutaway schematic of the loading plate of its display embodiment of the present invention. Described loading plate 1 has a loading end 1a, and described loading end 1a is formed a peelable glue-line 2.
The material constituting loading plate 1 can be conduction or the material of insulation, for instance the materials such as metal, metal alloy, plastics or quartz glass. It addition, peelable glue-line 2 can be laminated on loading plate 1. In one embodiment, peelable glue-line 2 is two-sided all to have sticking adhesive tape. In embodiments of the present invention, the shape of loading plate 1 can be consistent with wafer with size, for instance is 6 inches, 8 inches or 12 inches. In other embodiments, loading plate 1 be shaped as square.
Please coordinate with reference to Fig. 3 A, the encapsulating structure of display embodiment of the present invention schematic top plan view in the step S101 of Fig. 1. In the present embodiment, it is in advance multiple identical or different chip is reconfigured. It is to say, these chips according to the needs of practical application, and can be fixed in the multiple precalculated positions on peelable glue-line 2 respectively.
These chips can be identical or different semiconductor elements, for instance is power transistor, integrated circuit component or diode etc. Power transistor is such as rectilinear power transistor, insulation lock bipolar transistor (InsulatedGateBipolarTransistor, IGBT) or bottom source transverse direction double diffusion metal-oxide half field effect transistor (bottom-sourcelateraldiffusionMOSFET). Each chip has active surface and the back side, and these chips are to be attached on peelable glue-line 2 with active surface.
In the present embodiment, one first chip 3 and one second chip 4 adjacent in multiple chips, illustrate. Refer to Fig. 3 B, show Fig. 3 A generalized section along H-H hatching. First chip 3 has one first active surface 3a and first back side 3b contrary for active surface 3a with first. Being can be seen that by Fig. 3 B, the first chip 3 is to arrange towards peelable glue-line 2 with the first active surface 3a. Second chip 4 has the second active surface 4a and the second back side 4b too, and is attached on peelable glue-line 2 with active surface 4a.
In one example, first chip 3 and the second chip 4 respectively the first power transistor and the second power transistor, and first grid (not shown) and the source electrode (not shown) of chip 3 be formed at the first active surface 3a, and the (not shown) that drains is the first back side 3b forming the first chip 3. Similarly, the grid (not shown) of the second chip 4 and source electrode (not shown) are formed at the second active surface 4a, and the (not shown) that drains is the second back side 4b forming the second chip 4.
Refer to Fig. 4, the chip-packaging structure of its display embodiment of the present invention partial cutaway schematic in the step S102 of Fig. 1. In the diagram, engage glue 5 and be applied to the back side of each chip. In one embodiment, it is the mode utilizing some glue or half tone coating, the appropriate glue 5 that engages is positioned over the back side of each chip. Engaging glue 5 and can need selection conducting resinl or insulating cement according to what the kind of chip and circuit designed, wherein conducting resinl is such as elargol, the grafting material of the tool electric conductivity such as tin cream or copper cream. Insulating cement can be the high thermal paste of insulation.
In the fig. 4 embodiment, the first chip 3 and the second chip 4 are rectilinear power transistor, and the joint glue 5 therefore coating the back side 3b of the first chip 3 and the back side 4b of the second chip 4 is conducting resinl. But in other embodiments, when chip is control chip, joint glue is insulating cement.
Refer to Fig. 5 A and Fig. 5 B, wherein Fig. 5 A shows the encapsulating structure schematic top plan view at the step S103 of Fig. 1 of the embodiment of the present invention, and Fig. 5 B shows Fig. 5 A generalized section along I-I hatching. The material constituting conductive cover 6 can be copper, iron-nickel alloy or other alloys. In the present embodiment, the material constituting conductive cover 6 is copper alloy, and the thickness of conductive cover is between 25 to 100 ��m. Additionally, conductive cover can be made by technological means such as etching, punching press or impressings, the present invention is not limited thereto.
In Fig. 5 A embodiment, conductive cover 6 has base plate 60, frame 62 and a multiple demarcation strip 61, and wherein frame 62 and base plate 60 define an accommodation space, and multiple demarcation strip 61 is in order to separate accommodation space as multiple accommodating areas 620 being interconnected.
The shape of base plate 60 can coordinate the region of the shape of loading plate 1 or chip configuration and rounded, square or other geometries, and the present invention is not limited thereto. Specifically, base plate 60 has an a first surface 60a and second surface 60b relative with first surface 60a, and wherein first surface 60a is the back side of conductive cover 6. In one embodiment, conductive cover 6 has a hole for injecting glue 600 being formed on base plate 60. Illustrate, in the present embodiment, being formed on base plate 60 of hole for injecting glue 600, but in other embodiments, hole for injecting glue 600 can also be opened on frame 62, and the embodiment of the present invention is not limited thereto.
It addition, in the present embodiment, on the first surface 60a of base plate 60 can corresponding accommodating area 620 and be pre-formed multiple cutting marks 601 (marked in figure be example) and multiple cutting groove 602 (marked in figure is example). Multiple cutting marks 601 stagger with the position of demarcation strip 61 with the position of multiple cutting grooves 602. In the present embodiment, cutting mark 601 is a breach, to define in follow-up cutting step, will form the position of insulation tank. Cutting groove 602 is then in order to define the border of each encapsulating structure. The effect of cutting mark 601 and cutting groove 602 will be described in detail later in this article. In one embodiment, the width of cutting groove 602 is about 50 ��m.
Frame 62 protrudes from the second surface 60b of base plate 60, and is located on the neighboring area of base plate 60. It addition, frame 62 defined with base plate 60 go out accommodation space can hold all chips. Multiple demarcation strips 61 protrude from the second surface 60b of base plate 60, to be separated by accommodation space as multiple accommodating areas 620 being interconnected. These accommodating areas 620 are respectively in order to accommodating multiple chips, and the big I of accommodating area 620 is designed according to the size of chip.
In one embodiment, multiple demarcation strips 61 are to be distributed on base plate 60 in array, and the spacing size between two adjacent separator plates can slightly larger than the width of chip, and the height of frame and each demarcation strip 61 is more than the thickness of chip.
In the embodiment of Fig. 5 B, it is illustrate for the first demarcation strip 61a, the second demarcation strip 61b and the three demarcation strip 61c. Specifically, first demarcation strip 61a, the second demarcation strip 61b, defining one first accommodating area 620a and one second accommodating area 620b between the 3rd demarcation strip 61c and base plate 60, wherein the first demarcation strip 61a is between the first accommodating area 620a and the second accommodating area 620b.
It addition, continue referring to Fig. 5 A and Fig. 5 C, wherein Fig. 5 C shows the chip-packaging structure of embodiment of the present invention partial cutaway schematic in the step S104 of Fig. 1. In step S104, attach conductive cover 6 on loading end 1a to cover all chips. Showing in Fig. 5 C, when attaching conductive cover 6 and covering on loading end 1a, the first chip 3 and the second chip 4 lay respectively in the first accommodating area 620a and the second accommodating area 620b. It is to say, the first demarcation strip 61a is between the first chip 3 and the second chip 4.
Additionally, in one embodiment, when attaching conductive cover 6 is on loading end 1a, the end face 610 of frame 62 and each demarcation strip 61 also attaches on peelable glue-line 2, so that end face 610 copline of the second active surface 4a of the first active surface 3a of the first chip 3 and the second chip 4 and demarcation strip 61. It addition, the accommodation space of conductive cover 6 is only connected with the external world by hole for injecting glue 600.
First chip 3 is attached at conductive cover 6 by means of the joint glue 5 of the first back side 3b. In the present embodiment, if the first chip 3 is rectilinear power transistor, engaging glue 5 is conducting resinl, makes the drain electrode of the first chip 3 can be electrically connected with conductive cover 6 by means of engaging glue 5. Similarly, the drain electrode of the second chip 4 is electrically connected with conductive cover 6 also by joint glue 5. In other embodiments, when chip is control chip, engaging glue 5 is insulating cement, makes chip and conductive cover 6 be electrically insulated from each other.
Then, refer to Fig. 6, the chip-packaging structure of its display embodiment of the present invention partial cutaway schematic in step S105 and the S106 of Fig. 1. In step S105, inject a molding colloid 7 in conductive cover 6, to fill the gap between these demarcation strip and chips. Molding colloid 7 can be any suitable thermoplasticity or thermosets, for instance is the resins such as epoxy-based material, silica gel or photoresist. In one embodiment, the chip that the technology such as molding or injection molding can be used to make molding colloid 7 cover in each accommodating area 620 is embossed.
In the present embodiment, before injecting molding colloid 7, first pass through the hole for injecting glue 600 of base plate 60 to accommodation space evacuation, inject molding colloid 7 again through hole for injecting glue 600. In the present embodiment, molding colloid 7 is liquid-state silicon gel.
Illustrating, accommodation space is internal to be contributed to molding colloid 7 is sucked and flowed in each accommodating area 620 in vacuum state, and can reduce pore generation. In one embodiment, in the process injecting molding colloid 7, can continuously or intermittently rotate loading plate 1, to drive conductive cover 6 to rotate, it helps molding colloid 7 is inserted in each accommodating area 620 quickly.
Then, in step s 106, a solidification manufacturing process is performed, to form a moulding bodies. In embodiments of the present invention, it is by mean of a heating manufacturing process to be solidified by molding colloid 7. In the embodiment in fig 6, molding colloid 7 is inserted in the first accommodating area 620a and the second accommodating area 620b and the first chip 3 and the second chip 4 is coated with completely, and forms the first molding body 7a and the second molding body 7b in the first accommodating area 620a through overcuring.
Refer to Fig. 7, the chip-packaging structure of its display embodiment of the present invention partial cutaway schematic in the step S107 of Fig. 1. In step s 107, splitting die plastomer M1 and loading plate 1.
First active surface 3a of the first chip 3 and the second active surface 4a of the second chip 4, and the end face 610 of the first demarcation strip 61a, the second demarcation strip 61b and the three demarcation strip 61c is positioned at the first surface (Fig. 7 conductive cover 6 side down) of moulding bodies M1. It addition, in the present embodiment, the second surface (Fig. 7 conductive cover 6 side upward) of moulding bodies M1 is the first surface 60a of the base plate 60 of conductive cover 6. In Fig. 7 and show moulding bodies M1 is separated by loading plate 1. The upper surface of the moulding bodies M1 formed through above-mentioned manufacturing process has more smooth structure, the first active surface 3a copline of such as the first demarcation strip 61a and the first chip 3, and moulding bodies M1 less easily produces warpage issues, thinning manufacturing process also need not be carried out.
In step S108, form the connection layer first surface in moulding bodies to connect multiple chip. In one embodiment; before forming connection layer; can first the first surface of moulding bodies M1 (namely be transmitted upward by moulding bodies upset as shown in Figure 8; and the second surface of moulding bodies M1 is turned down) be positioned on substrate 8; the second surface making moulding bodies M1 is combined with substrate 8, and optionally forms protective layer in the first surface of moulding bodies M1. Refer to Fig. 8 to Fig. 9, show the partial cutaway schematic in the chip-packaging structure of the embodiment of the present invention each step before forming connection layer respectively. In the step of Fig. 8, moulding bodies M1 is arranged on substrate 8, and the second surface of moulding bodies M1 is directed towards substrate 8 and arranges. Substrate 8 is mainly in order to carry moulding bodies M1, it is possible to being glass substrate, plastic base or other any materials, the embodiment of the present invention is not limiting as.
Continue referring to Fig. 9. In fig .9, form patterning protective layer 9 and cover the first surface of moulding bodies M1. Patterning protective layer 9 can protect the active surface of chip in subsequent fabrication process not contaminated with formulate the position of connection layer and size. It addition, patterning protective layer 9 has multiple opening 9a��9f, to expose grid and the source electrode of the first chip 3 and the second chip 4, and the end face 610 of the first demarcation strip 61a and the second demarcation strip 61b.
The means forming patterning protective layer 9 can by any known technological means, for instance form patterning protective layer by manufacturing process such as deposition, lithographic and etchings. In one embodiment, patterning protective layer 9 is dielectric layer, it is possible to be phosphorosilicate glass (phosphosilicateglass), polyimides (polyimide) or nitride (nitride). But, in other embodiments, if the active surface of chip has had passivation layer or protective layer, then the step of Fig. 9 can be omitted.
In one embodiment, connection layer can include multiple projection underlying metal pad, conductor layer and multiple weld pad. Refer to Figure 10 to Figure 11, show the chip-packaging structure of the embodiment of the present invention partial cutaway schematic in each step forming connection layer respectively.
Refer to Figure 10, form multiple projection underlying metal pad 10a��10f in each opening 9a��9f. These projections underlying metal pad 10a��10f contacts grid and source electrode, the end face 610 of the first demarcation strip 61a and the grid of the second chip 4 and the source electrode of end face 610, first chip 3 of the second demarcation strip 61b respectively. It addition, form a conductor layer 11 on patterning protective layer 9, connect projection underlying metal pad 10c and projection underlying metal pad 10d.
Illustrating, projection underlying metal pad 10c is electrically coupled to the source electrode of the first chip 3, and another projection underlying metal pad 10d is the drain electrode being electrically connected the second chip 4. It is to say, when forming conductor layer 11 and being connected between projection underlying metal pad 10c and 10d, the source electrode of the first chip 3 and the drain electrode of the second chip 4 can be made to be electrically connected.
Then, refer to Figure 11, on each projection underlying metal pad 10a��10f, form a weld pad 12a��12f respectively, using the contact as connection outside line. Specifically, in the embodiment in figure 11, it is positioned at the weld pad 12a on the end face 610 of the second demarcation strip 61b and can be electrically connected to the drain electrode of the first chip 3 by means of the second demarcation strip 61b and base plate 60. Therefore, weld pad 12a can input (VIN) weld pad as voltage. It addition, the weld pad 12b laid respectively on the grid of the first chip 3 and be positioned at the weld pad 12e on the grid of the second chip 4, can respectively as upper gate pad and lower gate pad.
As it was previously stated, the drain electrode of the source electrode of the first chip 3 and the second chip 4 is electrically connected by conductor layer the 11, first demarcation strip 61a and base plate 60. Therefore, being positioned at the weld pad 12c on the source electrode of the first chip 3 and weld pad 12d on the end face 610 of the first demarcation strip 61a all can as switching node weld pad.
It addition, the weld pad 12f being positioned on the source electrode of the second chip 4 can as ground pad. In the present embodiment, the second chip 4 has multiple source electrode. In this case, multiple source electrodes of the second chip 4 can form multiple weld pad 12f respectively, and these weld pads 12f is all as ground pad.
In the above-described embodiment, assume that the first chip 3 and the second chip 4 illustrate for rectilinear power transistor. When chip is other semiconductor elements, according to the mode needing change wiring of application circuit, and different connection layers can be formed on active surface. Therefore, in the present invention, the enforcement aspect of connection layer it is not limiting as.
After the making completing connection layer, substrate 8 is removed by moulding bodies M1 second surface. At this point it is possible to chip is tested, and with manufacturing process such as laser labels.
Then, refer to Figure 12 A and Figure 12 B, wherein Figure 12 A shows the chip-packaging structure of embodiment of the present invention schematic top plan view in the step S109 of Fig. 1, and Figure 12 B shows that the chip-packaging structure of embodiment of the present invention part section before the step S109 of Fig. 1 cuts is intended to. Refer to the generalized section after Figure 13, the step S109 at Fig. 1 of the encapsulating structure of a display present invention wherein embodiment cut.
In step S109, perform a cutting step, so that moulding bodies M1 is separated into multiple encapsulating structure. Each encapsulating structure has the line layer being cut the conduction rack formed by conductive cover 6 with being formed by the cutting of connection layer. When performing cutting step, it is cut by the second surface of moulding bodies M1. When performing cutting step, it is possible to by means of mechanical type cutter (such as diamond cutter) or utilize the wet etching to complete.
In embodiments of the present invention, it is possible to according to chip by function mode in circuit, change position and the degree of depth of cutting, to form different encapsulating structures. In the embodiment of Figure 12 A, after moulding bodies M1 is cut, the first chip 3 and the second chip 4 are encapsulated in one first encapsulating structure M1 ' jointly, as shown in figure 13.
As previously mentioned, in embodiments of the present invention, the mark of cutting mark 601 and 602 two kinds of different depths of cut of cutting groove has been formed as shown in figure 12 on the base plate 60 of conductive cover 6, so that in cutting step, along cutting mark 601, moulding bodies M1 can be carried out shallow cutting step (the first line of cut 20a such as Figure 12 A), and carry out cutting through step (the second line of cut 20b such as Figure 12 A) along cutting groove 602.
Specifically, refer to Figure 12 A, when performing cutting step, according to the position of cutting mark 601, shallow cutting step can be performed along the first line of cut 20a by the second surface of moulding bodies M1. In shallow cutting step, it is only that the base plate 60 of the conductive cover 6 connected between the first chip 3 and the second chip 4 is cut, so that the drain electrode of the drain electrode of the first chip 3 and the second chip 4 electrically isolates, and does not cut the first molding body 7a. Further, after performing shallow cutting step, the back side at the first encapsulating structure M1 ' is formed at least one insulation tank 603, as shown in figure 13.
It addition, in cutting step, more include the position according to cutting groove 602, perform one along the second line of cut 20b and cut through step, to form multiple encapsulating structure being separated from each other. Cut through step to include and cutting along the second line of cut 20b along the second line of cut 20b in X-direction in X-direction.
In the present embodiment, the first encapsulating structure M1 ' of Figure 13 is applicable to voltage conversion circuit, including the first conduction rack, first chip the 3, second chip 4 and first line layer.
Specifically, the first conduction rack at least has bottom and the first demarcation strip 61a, and wherein base plate 60 is after above-mentioned cutting step, and base plate 60 is cut and forms bottom. The first conduction region 60c and the second conduction region 60d is included in the bottom of Figure 13. Second conduction region 60d and the first demarcation strip 61a is collectively forming first accommodating area 620a (Figure 13 right-hand component, with reference to 5B figure correspondence position), and first conduction region 60c and the second demarcation strip 61b be collectively forming the first accommodating area 620a (Figure 13 left-hand component, with reference to 5B figure correspondence position). In other words, the first demarcation strip 61a is between the first accommodating area 620a and the second accommodating area 620b.
After above-mentioned shallow cutting step, base plate 60 is cut and forms bottom, and bottom is separated the first conduction region 60c and the second conduction region 60d into mutually insulated by insulation tank 603. It is to say, insulation tank 603 is between the first conduction region 60c and one second conduction region 60d. But, the first above-mentioned demarcation strip 61a is still electrically connected with the second conduction region 60d.
First chip 3 is packaged in the first accommodating area 620a by the first molding body 7a, and the drain electrode of the first chip 3 is by mean of conducting resinl and is electrically connected at the first conduction region 60c. Second chip 4 is then packaged in the second accommodating area 620b by the second molding body 7b, and the drain electrode of the second chip 4 is electrically connected to the second conduction region 60d by means of conducting resinl. In first encapsulating structure M1 ' of the embodiment of the present invention, more include one second demarcation strip 61b. Second demarcation strip 61b is formed at the side of the first conduction rack, and is collectively forming the first accommodating area 620a with the first demarcation strip 61a.
First line layer is formed on the active surface 3a of the first chip 3 and active surface 4a of the second chip 4, to be electrically connected the first chip 3 and the second chip 4. Specifically, as it has been described above, first line layer may be included in the multiple projection underlying metal pad 10a��10f, conductor layer 11 and the multiple weld pad 12a��12f that are formed in Figure 10 to Figure 11. Namely first line layer cuts the line layer formed for the connection layer above the first active surface 3a of the first chip 3 and the second active surface 4a of the second chip 4. Such as Figure 12 B, after cutting through along the second line of cut 20b, connection layer forms line layer above Figure 13.
It addition, these weld pads 12a��12f at least has a voltage input weld pad, gate pad, once gate pad, at least one switching node weld pad and at least one ground pad on one. Voltage input weld pad is electrically connected at the drain electrode of the first chip 3 by the second demarcation strip 61b and the first conduction region 60c, such as weld pad 12a. Upper gate pad is electrically connected to the grid of this first chip 3, such as weld pad 12b. Lower gate pad is electrically connected to the grid of the second chip 4, such as weld pad 12e. Switching node weld pad is electrically connected to the source electrode of the first chip 3 and the drain electrode of the second chip 4, such as weld pad 12c and 12d. Ground pad is then electrically connected the source electrode of the second chip 4, such as weld pad 12f. In the present embodiment, the second chip 4 is to have two ground pads.
In the above-described embodiment, the first chip 3 is jointly coordinate at same circuit with the second chip 4, for instance operating in voltage conversion circuit, therefore, the first chip 3 and the second chip 4 are jointly to be encapsulated in the first encapsulating structure M1 '. In other embodiments, two adjacent the first chips 3 and the second chip 4 can also individually operate in circuit. In this case, can, in cutting step, cut open to form each independent encapsulating structure by the first chip 3 and the second chip 4.
Refer to Figure 14 A and Figure 14 B. Figure 14 A shows that the encapsulating structure of the embodiment of the present invention is applied to the schematic diagram in circuit. Figure 14 B shows the schematic top plan view of the encapsulating structure of the embodiment of the present invention. Being can be seen that by Figure 14 A and Figure 14 B, each weld pad of the first encapsulating structure M1 ' in Figure 14 B can directly as the contact of external circuit. For example, the VIN pin controlling element (not shown) can be electrically connected to weld pad 12a, GH pin can be electrically connected to weld pad 12b, SW pin can be electrically connected to that weld pad 12c, GL pin can be electrically connected to weld pad 12d and GND pin can be electrically connected to weld pad 12f.
It is to say, the encapsulating structure made by manufacture method of the fan-out wafer level chip-packaging structure of the application embodiment of the present invention, establish the electric connection between chip by means of conduction rack and line layer. Therefore, the encapsulating structure of the embodiment of the present invention is actually the semi-finished product of component, and may be directly applied in circuit.
Refer to Figure 15 A and Figure 15 B. Figure 15 A shows that the encapsulating structure of another embodiment of the present invention is applied to the schematic diagram in circuit. Figure 15 B shows the schematic top plan view of the encapsulating structure of another embodiment of the present invention.
The another kind of voltage conversion circuit of Figure 15 A display. Voltage conversion circuit compared to Figure 14 A, in the circuit diagram of Figure 15 A, having used three power transistors, one of them is the power transistor (high-sideMOSFET) of high side, and the power transistor that two other is downside (low-sideMOSFET).
In the present embodiment, can form, with depth of cut, the encapsulating structure M2 being applied in Figure 15 A by means of suitable design cutting position. Encapsulating structure M2 has first chip 3 and two the second chips 41, two of which the second chip 41 is all arranged in the second accommodating area 620b (with reference to Fig. 5 B correspondence position), and the drain electrode of two the second chips 41 is all electrically connected (with reference to Figure 13) with the second conduction region 60d. In the present embodiment, cutting step is performed identical with previous embodiment with the cutting mode forming encapsulating structure M2.
It addition, in encapsulating structure except the first chip 3 and the second chip 41, can more include one the 3rd chip 42, wherein the first chip 3 and the second chip 41 are active member, and the 3rd chip 42 is passive device, for instance diode, show below Figure 16 A and Figure 16 B.
Specifically, refer to Figure 16 A and Figure 16 B. Figure 16 A shows that the encapsulating structure of another embodiment of the present invention is applied to the schematic diagram in circuit. Figure 16 B shows the schematic top plan view of the encapsulating structure of another embodiment of the present invention. In the voltage conversion circuit shown in Figure 16 A, except application high side power transistor with low side power transistor, the power transistor of a downside diode in parallel.
In encapsulating structure M3 shown in Figure 16 B except the first chip 3 and the second chip 41, more include one the 3rd chip 42, wherein the first chip 3 is packaged in the first accommodating area 620a, and the second chip 41 and the 3rd chip 42 are packaged in the second accommodating area 620b. In the present embodiment, the first chip 3 and the second chip 41 are all power transistor, and the 3rd chip 42 is diode. Additionally, first chip the 3, second chip 4 and the 3rd chip 42 can be electrically connected according to the circuit diagram shown in Figure 16 A with line layer by lead frame. In the present embodiment, cutting step is performed identical with previous embodiment with the cutting mode forming encapsulating structure M2.
In other embodiments, another encapsulating structure can be formed by means of change cutting position with depth of cut. Refer to Figure 17 A and Figure 17 B. Figure 17 A shows the encapsulating structure of another embodiment of the present invention schematic top plan view in cutting step. Figure 17 B shows the schematic top plan view of the encapsulating structure of another embodiment of the present invention.
In the embodiment of Figure 12 A, perform shallow cutting step along the first line of cut 20a only in the Y direction. In the embodiment of Figure 17 A, when performing cutting step, except performing shallow cutting step along the first line of cut 21a in the Y direction, also in X side, perform shallow cutting step along the first line of cut 21a. It addition, all perform to cut through step to form multiple encapsulating structure M4 along the second line of cut 21b in X-direction with Y-direction. Refer to Figure 17 B, the encapsulating structure M4 after cutting include two adjacent but be positioned at the first chip 3 of different accommodating area, and two adjacent but be positioned at the second chip 4 of different accommodating area.
In an alternative embodiment of the invention, the control chip in circuit, high side power transistor and low side power transistor can be converted the voltage into be mutually encapsulated in an encapsulating structure. Refer to Figure 18 A and Figure 18 B. Figure 18 A shows the encapsulating structure of further embodiment of this invention schematic top plan view in cutting step. Figure 18 B shows the schematic top plan view of the encapsulating structure of further embodiment of this invention.
Encapsulating structure M5 includes control chip the 30, first chip 3 and the second chip 4. Wherein control chip 30 can be electrically connected to the control end of the first chip 3 and the second chip 4 by means of lead frame and line layer. In the present embodiment, control chip 30 is neighbouring from the first chip 3 but is positioned in different accommodating areas, and the second chip 4 then correspondence is positioned in two accommodating areas.
As shown in Figure 18 A, when performing cutting step, only perform shallow cutting step along the first line of cut 22a in the Y direction, electrically to completely cut off the drain electrode of the first chip 3 and the second chip 4. It addition, all perform to cut through step to form multiple encapsulating structure M5 along the second line of cut 21b in X-direction with Y-direction.
In sum, beneficial effects of the present invention can be in that, in the manufacture method of the chip-packaging structure provided in the embodiment of the present invention, after utilizing conductive cover to cover chip, again molding colloid injected the gap between chip and conductive cover and solidify, the size thinning of encapsulating structure can be made, and moulding bodies need not be ground. It addition, when moulding bodies is performed cutting step, different encapsulating structures can be formed from depth of cut by means of changing the position cut.
It addition, the encapsulating structure that the embodiment of the present invention provides, on electrode, directly form the weld pad that may be directly connected to circuit board, dead resistance and stray inductance can be reduced. When the package module of the present embodiment is applied in component, can lift elements running efficiency. The encapsulating structure of the embodiment of the present invention also has conduction rack, it is possible to provide preferably radiating effect.
The foregoing is only the preferably possible embodiments of the present invention, the non-claims therefore limiting to the present invention, therefore the equivalence techniques change that all utilizations description of the present invention and accompanying drawing content are done, be both contained in the claims of the present invention.

Claims (16)

1. the manufacture method of a fan-out wafer level chip-packaging structure, it is characterised in that the manufacture method of described fan-out wafer level chip-packaging structure includes:
One loading plate is provided, there is a loading end, this loading end is formed a peelable glue-line;
Arranging multiple chip on this peelable glue-line, each of which chip has an active surface and a back side, and the multiple described active surface of multiple described chips is attached on this peelable glue-line;
Coating engages glue in the back side of multiple described chips;
Thering is provided a conductive cover, have a base plate and the multiple demarcation strips being positioned on this base plate, multiple described demarcation strips form multiple accommodating area;
Attaching this conductive cover on this loading end to cover multiple described chip, plurality of described chip lays respectively in multiple described accommodating area and spaced with multiple described demarcation strips;
Inject a molding colloid in this conductive cover, to fill the gap between multiple described demarcation strip and multiple described chip;
Perform a solidification manufacturing process, to form a moulding bodies;
Separating this moulding bodies and this loading plate, the active surface of each of which chip is positioned at a first surface of this moulding bodies;
Form a connection layer this first surface in this moulding bodies to connect multiple described chip; And
Performing a cutting step, so that this moulding bodies to be separated into multiple encapsulating structure, each of which encapsulating structure has the conduction rack formed by the cutting of this conductive cover and the line layer formed by the cutting of this connection layer.
2. the manufacture method of fan-out wafer level chip-packaging structure as claimed in claim 1, it is characterized in that, one first encapsulating structure of multiple described encapsulating structures includes one first chip and one second chip, one first conduction rack and a first line layer, this first conduction rack has one first demarcation strip, between this first chip and this second chip, this first chip is electrically connected with this first line layer by this first conduction rack with this second chip.
3. the manufacture method of fan-out wafer level chip-packaging structure as claimed in claim 2, it is characterized in that, this first chip is one first power transistor, this second chip is one second power transistor, this first line layer has gate pad on, gate pad once, one switching node weld pad and at least one ground pad, wherein on this, gate pad is electrically connected to the grid of this first power transistor, this lower gate pad is electrically connected to the grid of this second power transistor, this switching node weld pad is electrically connected to the source electrode of this first power transistor and the drain electrode of this second power transistor by this first conduction rack.
4. the manufacture method of fan-out wafer level chip-packaging structure as claimed in claim 1, it is characterized in that, this conductive cover has a frame, the height of multiple described demarcation strips and this frame is more than the thickness of multiple described chips, and in this conductive cover of attaching to the step of this loading end, the end face of this frame and this demarcation strip is pasted on this peelable glue-line.
5. the manufacture method of fan-out wafer level chip-packaging structure as claimed in claim 1, it is characterised in that the back side of this conductive cover has multiple cutting groove to define the border of multiple described encapsulating structure.
6. the manufacture method of fan-out wafer level chip-packaging structure as claimed in claim 1, it is characterised in that the back side of this conductive cover includes multiple cutting mark, and this cutting step more includes:
Cutting this base plate of this conductive cover to form at least one insulation tank in the back side of encapsulating structure each described according to this cutting mark, this at least one insulation tank makes this conduction rack be divided at least two conduction region.
7. the manufacture method of fan-out wafer level chip-packaging structure as claimed in claim 2, it is characterized in that, this first encapsulating structure also includes one the 3rd chip, wherein this first chip and this second chip are active member, 3rd chip is passive device, and this first chip, this second chip are electrically connected with each other by this first conduction rack and this first line layer with the 3rd chip.
8. the manufacture method of fan-out wafer level chip-packaging structure as claimed in claim 7, it is characterised in that this first chip and this second chip are power transistor, and the 3rd chip is diode.
9. the manufacture method of fan-out wafer level chip-packaging structure as claimed in claim 2, it is characterized in that, this first encapsulating structure also includes a control chip, is electrically connected to the control end of this first chip and this second chip by this first conduction rack and this first line layer.
10. the manufacture method of fan-out wafer level chip-packaging structure as claimed in claim 9, it is characterised in that the joint glue of the back side of this control chip bonding and this first conduction rack is insulating cement.
11. an encapsulating structure a, it is adaptable to voltage conversion circuit, it is characterised in that described encapsulating structure includes:
One conduction rack, have bottom one with one first demarcation strip to form one first accommodating area and one second accommodating area, this first demarcation strip is between this first accommodating area and this second accommodating area, being divided into one first conduction region and one second conduction region of mutually insulated bottom this, wherein this first demarcation strip is electrically connected with this second conduction region;
One first power transistor, is packaged in this first accommodating area, and the drain electrode of this first power transistor is electrically connected to this first conduction region;
One second power transistor, is packaged in this second accommodating area, and the drain electrode of this second power transistor is electrically connected to this second conduction region; And
One line layer, is electrically connected the first active surface of this first power transistor and the second active surface of this second power transistor;
Wherein, the end face of this first demarcation strip, this first power transistor the second active surface copline of the first active surface and this second power transistor, the source electrode of this first power transistor is electrically connected to the drain electrode of this second power transistor via this first demarcation strip and this second conduction region.
12. encapsulating structure as claimed in claim 11, it is characterized in that, this line layer has gate pad on, once gate pad, a switching node weld pad and at least one ground pad, wherein on this, gate pad is electrically connected to the grid of this first power transistor, this lower gate pad is electrically connected to the grid of this second power transistor, and this switching node weld pad is electrically connected to the source electrode of this first power transistor and the drain electrode of this second power transistor by this first demarcation strip and this second conduction region.
13. encapsulating structure as claimed in claim 11, it is characterised in that be formed with an insulation tank bottom this, between the first conduction region and one second conduction region.
14. encapsulating structure as claimed in claim 11, it is characterised in that also include one second demarcation strip, be positioned at the side of this conduction rack, wherein this second demarcation strip and this first demarcation strip form this first accommodating area.
15. encapsulating structure as claimed in claim 11, it is characterised in that this first conduction region is connected to the back side of this first power transistor via a conducting resinl, and this second conduction region is connected to the back side of this second power transistor via this conducting resinl.
16. an encapsulating structure a, it is adaptable to voltage conversion circuit, it is characterised in that described encapsulating structure includes:
One conduction rack, have bottom one with one first demarcation strip to form one first accommodating area and one second accommodating area, this first demarcation strip is between this first accommodating area and this second accommodating area, being divided into one first conduction region and one second conduction region of mutually insulated bottom this, wherein this first demarcation strip is electrically connected with this second conduction region;
One first power transistor, is packaged in this first accommodating area, and the drain electrode of this first power transistor is electrically connected to this first conduction region;
One control chip, is packaged in this first accommodating area, and this control chip is electrically insulated from this first conduction region;
One second power transistor, is packaged in this second accommodating area, and the drain electrode of this first power transistor is electrically connected to this second conduction region; And
One line layer, is formed on this control chip, one first active surface of this first power transistor and one second active surface of this second power transistor to be electrically connected this control chip, this first power transistor and this second power transistor;
Wherein, the end face of this first demarcation strip, this first power transistor the second active surface copline of the first active surface and this second power transistor, this first demarcation strip is between this first power transistor and this second power transistor, and the source electrode of this first power transistor is electrically connected to the drain electrode of this second power transistor via this first demarcation strip and this second conduction region.
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