CN105632910B - Gate conductor layer and manufacturing method thereof - Google Patents
Gate conductor layer and manufacturing method thereof Download PDFInfo
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- CN105632910B CN105632910B CN201510147801.5A CN201510147801A CN105632910B CN 105632910 B CN105632910 B CN 105632910B CN 201510147801 A CN201510147801 A CN 201510147801A CN 105632910 B CN105632910 B CN 105632910B
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- 239000004020 conductor Substances 0.000 title claims abstract description 80
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000843 powder Substances 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000005224 laser annealing Methods 0.000 claims abstract description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 239000002390 adhesive tape Substances 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 13
- 238000000151 deposition Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000000059 patterning Methods 0.000 description 3
- 239000011148 porous material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 229910005542 GaSb Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
Abstract
The present disclosure provides a gate conductor layer and a method of manufacturing the same. An example method may include: filling conductive material powder into the groove defined by the gate side wall; and carrying out laser annealing on the filled conductive material powder to form a conductive material layer, wherein the conductive material layer forms the gate conductor layer.
Description
Technical Field
The present invention relates to a semiconductor manufacturing process, and more particularly, to a gate conductor layer and a method of manufacturing the same.
Background
With the continuous shrinkage of semiconductor devices, the gate-last process is beginning to be widely used. In the gate last process, a sacrificial gate stack is first formed, and device fabrication, such as source/drain implantation, is performed on the basis of the sacrificial gate stack. The sacrificial gate stack is then removed and the trench left inside the gate sidewall due to the removal of the sacrificial gate stack is filled with a real gate stack, such as a high-K/metal gate stack. However, as the size of semiconductor devices is further reduced, it is difficult to fill smaller and smaller trenches.
Disclosure of Invention
In view of the above, the present disclosure provides a method of manufacturing a gate conductor layer.
According to an aspect of the present disclosure, there is provided a method of manufacturing a gate conductor layer, including: filling conductive material powder into the groove defined by the gate side wall; and carrying out laser annealing on the filled conductive material powder to form a conductive material layer, wherein the conductive material layer forms the gate conductor layer.
According to another aspect of the present disclosure, a gate conductor layer is provided that includes a conductive material that is substantially free of voids and pores. For example, the conductive material may include a conductive material that recrystallizes after melting.
According to an embodiment of the present disclosure, the gate conductor layer may be formed by filling conductive material powder and performing laser annealing. Since the filling of the powder is easier than the filling of the metal film, the gate conductor layer can be manufactured relatively easily. Furthermore, a more compact, void and pore free filling effect can be provided.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:
fig. 1-6 are schematic diagrams illustrating some stages in a process for fabricating a gate conductor layer according to an embodiment of the disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
According to an embodiment of the present disclosure, there is provided a method of manufacturing a gate conductor layer. The method may include filling conductive material powder into a trench defined by the gate sidewall, and performing laser annealing on the filled conductive material powder. The laser may melt/melt the powder and form a dense layer of conductive material, which may form a gate conductor layer. The powder can be filled into the grooves relatively easily due to its small size. Furthermore, a more compact, void and pore free filling effect can be provided.
The trench may be obtained by a gate-last process. Specifically, a sacrificial gate stack may be formed on a substrate, and a gate sidewall may be formed on a sidewall of the sacrificial gate stack. Device fabrication, e.g., source/drain implantation, may be performed on the basis of the sacrificial gate stack (and gate sidewall spacers). A dielectric layer may then be formed on the substrate on which the sacrificial gate stack is formed and subjected to a planarization process, such as Chemical Mechanical Polishing (CMP), to expose the sacrificial gate stack. The exposed sacrificial gate stack may be removed, leaving a trench to be filled inside the gate sidewall.
Such a layer of conductive material may be formed layer by layer. For example, the trenches may be filled with a conductive material powder in multiple passes, and laser annealing may be performed after each fill until the resulting conductive material layer fills the trenches. The conductive material powder filled each time can be approximately uniformly distributed in the groove, so that the conductive material layer with approximately uniform thickness is formed after annealing. The conductive material layers are continuous with each other to form a body, thereby constituting a gate conductor layer. Further, each charge of the conductive material powder may include different compositions.
When the conductive material powder is filled, the conductive material powder may be left only in the grooves. For example, at the time of filling, the conductive material powder located outside the trench may be removed. This removal may be achieved by means of adhesive tape.
Upon annealing, the laser may be applied without a pattern. Since the conductive material powder may be present only in the grooves, the conductive material layer is formed only in the grooves. Alternatively, the laser may be confined to the area where the trench is located. For example, the laser may be applied according to the formation pattern of the trench. Thus, the formed conductive material layer may be confined in the trench.
The techniques of this disclosure may be presented in a number of ways, some examples of which are described below.
Referring to fig. 1, a substrate 102 is provided. The substrate 102 may be any form of suitable substrate, such as a bulk semiconductor substrate, e.g., Si, Ge, etc., a compound semiconductor substrate, e.g., SiGe, GaAs, GaSb, AlAs, InAs, InP, GaN, SiC, InGaAs, InSb, InGaSb, etc., a semiconductor-on-insulator Substrate (SOI), etc. Here, a bulk silicon substrate and a silicon-based material are described as an example. It is noted, however, that the present disclosure is not so limited.
On the substrate 102, a sacrificial gate stack may be formed. The sacrificial gate stack may include a sacrificial gate dielectric layer 104 and a sacrificial gate conductor layer 106. Sacrificial gate dielectric layer 104 may comprise an oxide (e.g., silicon oxide) having a thickness of about 3-20 nm; the sacrificial gate conductor layer 106 may comprise polysilicon and may be about 30-100nm thick. Such a sacrificial gate stack may be obtained, for example, by sequentially depositing an oxide layer and a polysilicon layer on the substrate 102 and patterning them, such as Reactive Ion Etching (RIE), into, for example, stripes.
On the sidewalls of the sacrificial gate stack, gate sidewalls 108 may be formed. The gate sidewall spacers 108 may comprise a nitride (e.g., silicon nitride) having a thickness of about 1-20 nm. The gate spacers 108 may be obtained, for example, by depositing a layer of nitride substantially conformally on the substrate on which the sacrificial gate stack is formed, and then performing an anisotropic etch, such as RIE.
Device fabrication may be performed on the basis of the sacrificial gate stack (and gate sidewall spacers), such as performing source/drain implants and the like. Those skilled in the art will know the various ways to perform these processes and will not be described in further detail herein.
On the substrate 102, a dielectric layer 110 may be formed, for example, by deposition. The dielectric layer 110 may include an oxide and may completely cover the sacrificial gate stack and the gate sidewall. The dielectric layer 110 may be planarized such as Chemical Mechanical Polishing (CMP). The CMP may stop on the gate sidewall 108, exposing the sacrificial gate stack.
Next, as shown in fig. 2, the sacrificial gate stack may be removed by selective etching. The sacrificial gate conductor layer 106 may be selectively removed, for example, by TMAH solution. In addition, the sacrificial gate dielectric layer 104 may be selectively removed by, for example, RIE. Thus, inside the gate sidewall 108, a trench 112 is left. The trench 112 may then be filled with a true gate stack, such as a high-K/metal gate stack.
A gate dielectric layer 114 may then be formed, for example by deposition, over the structure shown in fig. 2, as shown in fig. 3. The gate dielectric layer 114 may include a high-K gate dielectric such as HfO2And a thickness of about 2-4 nm. In addition, a work function adjusting layer 116 may also be formed on the gate dielectric layer 114 by, for example, deposition. The work function adjusting layer 116 may include TiN with a thickness of about 3-10 nm.
Subsequently, as shown in fig. 4, the trench 112 filled with the gate dielectric layer 114 and the work function adjusting layer 116 may be filled with a conductive material powder 118 by, for example, deposition. The conductive material powder 118 may include a metal, such as at least one of TiN, W, Al, and Cu. During the filling process, the conductive material powder 118 may be confined within the trench 112. For example, the powder possibly existing outside the groove 112 may be removed by a tape or the like.
Next, as shown in fig. 5, the filled conductive material powder 118 may be laser annealed to melt/melt it, and then cooled to recrystallize to form a dense conductive material layer 120 within the trenches. The conductive material layer 120 serves as a gate conductor layer.
The laser may be applied unpatterned on the structure shown in fig. 4, for example scanned across the entire surface of the structure shown in fig. 4. Since the conductive material powder 118 is located only in the groove, the conductive material layer 120 formed by annealing is also located in the groove.
Alternatively, the laser may be applied according to the patterning of the trench, so that the annealing is localized to the region where the trench is located. In this case, the conductive material powder outside the trench may be removed even after the laser annealing.
In the above example, sufficient powder was deposited into the trench in one fill operation. However, the present disclosure is not limited thereto. For example, the powder may be filled multiple times, each time with a thinner layer of powder. This helps to avoid possible defects such as voids due to the one-time filling of the grooves with too much powder. The conductive material powder filled each time may be substantially uniform. Laser annealing may be performed after each fill to convert the filled conductive material powder into a layer of conductive material. Such operations may be repeated until a layer of conductive material of a desired size is formed, e.g., to substantially fill the trench. These conductive material layers are continuous and integral with each other, thereby forming a gate conductor.
It is to be noted here that the composition of the conductive material powder to be filled at each time is not necessarily the same.
After forming the gate conductor layer 120, a conventional process may be performed. For example, as shown in FIG. 6, the structure shown in FIG. 5 may be subjected to a planarization process such as CMP. The CMP may stop at the gate sidewall to remove portions of the gate dielectric layer 114 and the work function adjusting layer 116 outside the trench. In this way, the final true gate stack is formed within the trench, including the gate dielectric layer 116 ', the work function adjusting layer 116', and the gate conductor layer 120.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (11)
1. A method of fabricating a gate conductor layer, comprising:
filling conductive material powder into the groove defined by the gate side wall; and
the filled conductive material powder is subjected to laser annealing to be melted/melted, and then cooled and recrystallized to form a conductive material layer which forms the gate conductor layer.
2. The method of claim 1, wherein the trenches are filled with a conductive material powder in multiple passes, and laser annealing is performed after each fill.
3. The method of claim 2, wherein each fill of conductive material powder comprises a different composition.
4. The method of claim 1, wherein prior to filling the conductive material powder, the method further comprises:
and filling a gate dielectric layer into the trench.
5. The method of claim 4, further comprising:
and filling a work function adjusting layer in the groove, wherein the work function adjusting layer is arranged on the gate dielectric layer.
6. The method of claim 5, wherein after forming the gate conductor layer, the method further comprises:
and carrying out planarization treatment to remove the part of the gate dielectric layer and the part of the work function adjusting layer which are arranged outside the groove.
7. The method of claim 1, wherein the conductive material powder comprises at least one of TiN, W, Al, and Cu.
8. The method of claim 1, further comprising: and removing the conductive material powder existing outside the groove.
9. The method of claim 8, wherein the removing is performed with an adhesive tape.
10. The method of claim 1, wherein the laser annealing is localized to the region where the trench is located.
11. A gate conductor layer comprising a substantially void-free and pore-free conductive material, wherein said conductive material comprises a conductive material that recrystallizes upon melting.
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| CN201510147801.5A CN105632910B (en) | 2015-03-31 | 2015-03-31 | Gate conductor layer and manufacturing method thereof |
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| CN201510147801.5A CN105632910B (en) | 2015-03-31 | 2015-03-31 | Gate conductor layer and manufacturing method thereof |
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| CN105632910B true CN105632910B (en) | 2021-04-30 |
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| US10763165B2 (en) | 2017-04-18 | 2020-09-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive powder formation method, device for forming conductive powder, and method of forming semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1959531A (en) * | 2005-10-31 | 2007-05-09 | 飞思卡尔半导体公司 | Method for forming multi-layer bumps on a substrate |
| CN102339752A (en) * | 2010-07-14 | 2012-02-01 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device based on gate replacement technique |
| CN102915949A (en) * | 2011-08-01 | 2013-02-06 | 中国科学院微电子研究所 | Method for embedding metal material in substrate |
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| JPS60502233A (en) * | 1983-09-21 | 1985-12-19 | アライド コ−ポレイシヨン | Printed board manufacturing method |
| KR101156177B1 (en) * | 2010-06-16 | 2012-06-18 | 한국생산기술연구원 | Anisotropic Conductive Film Having Containing Groove of Conductive Material, Joining Method of Flip Chip Using Epoxy Resin Having Containing Groove of Conductive Material and Flip Chip Package Using the Same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1959531A (en) * | 2005-10-31 | 2007-05-09 | 飞思卡尔半导体公司 | Method for forming multi-layer bumps on a substrate |
| CN102339752A (en) * | 2010-07-14 | 2012-02-01 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device based on gate replacement technique |
| CN102915949A (en) * | 2011-08-01 | 2013-02-06 | 中国科学院微电子研究所 | Method for embedding metal material in substrate |
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