CN105632897A - MIM (metal-insulator-metal) capacitor and preparation method therefor - Google Patents
MIM (metal-insulator-metal) capacitor and preparation method therefor Download PDFInfo
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- CN105632897A CN105632897A CN201610100039.XA CN201610100039A CN105632897A CN 105632897 A CN105632897 A CN 105632897A CN 201610100039 A CN201610100039 A CN 201610100039A CN 105632897 A CN105632897 A CN 105632897A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
Abstract
The invention relates to a preparation method for a semiconductor device, and provides a preparation method for an MIM (metal-insulator-metal) capacitor capable of restraining electric leakage when upper and lower polar plates of the MIM capacitor are mutually connected; meanwhile, the preparation method can prevent an insulating material on a metal layer of the lower polar plate from being etched into an irregular shape when the lower polar plate is formed. A lower part metal layer, a first dielectric layer and an upper part metal layer are formed on a substrate from upper to lower in sequence; the upper part metal layer is patterned to form an upper part capacitor plate; the lower part metal layer is patterned to form a lower part capacitor plate; and the first dielectric layer is etched into an interlayer dielectric layer between the upper and lower capacitor plates.
Description
Technical field
The preparation method that the present invention relates to semiconductor device, or rather, it is to provide the upper bottom crown interconnection that can suppress MIM capacitor and produces the MIM capacitor preparation method of electric leakage, also avoid the insulant on the metal level at bottom crown place to be etched to irregular shape when forming bottom crown simultaneously.
Background technology
The passive device such as electric capacity and resistance is widely used in production of integrated circuits technology, these devices are typically with the integrated circuit technology of standard, doped monocrystalline silicon or DOPOS doped polycrystalline silicon and oxide-film or nitrogen oxidation film etc. is such as utilized to make flat pole plate, such as PIP capacitor (Poly-Insulator-Poly) or similar electric capacity. due to its assembly relatively silicon substrate, the parasitic capacitance between device and substrate makes the performance of device be affected, especially in radio circuit, with frequency rising device hydraulic performance decline quickly. the exploitation of MIM capacitor (Metal-Insulator-Metal) provides effective way for solving these problems, electric capacity is produced in interconnection layer namely postchannel process (Backendprocess) by this technology, thus integrated circuit technology that both can be similar with CMOS etc. is mutually compatible, the distance zooming out between passive device and conductive substrates can be passed through again, thus overcoming parasitic capacitance big completely and drawback that device performance increases with frequency and is decreased obviously, make this technology be increasingly becoming in radio frequency or other field integrated circuit make passive capacitor part mainstream scheme.
But the making of MIM capacitor there is also some defects, it is referred to disclosed Chinese patent application CN101577227A about basic mim capacitor structure. in existing MIM capacitor, it is usually provided with lower metal structure and upper strata metal structure, between this double layer of metal structure, utilizes insulant to isolate, and realize electrical connection by through-hole structure with lower metal structure and upper strata metal structure. analyze structure, this lower metal structure and upper strata metal structure and the insulant between them define basic MIM capacitor, upper strata metal structure be sized generally below lower metal structure, through-hole structure can not be sheltered from by upper strata metal structure and reach lower metal structure, if the sidewall of upper strata metal structure is attached with conductive polymer or similar conductor, one negative effect is, upper strata metal structure is short-circuit easily via polymer and lower metal structure produce directly to be electrically connected, produce dark current, this undesirably occurs.
Lower metal structure or bottom crown etch typically by metal level; this layer of metal level is except needing to be divided into the lower metal structure of electric capacity or bottom crown; also need to for forming some metal interconnection wires; but the insulant regrettably covered above metal interconnection wire is easy to be etched to irregular shape, thus it is many unfavorable to bring to the molding of the follow-up passivation layer for protecting chip. The present invention will elaborate solution hereinafter one by one.
Summary of the invention
The preparation method of a kind of MIM capacitor that the present invention relates to, comprises the following steps: step S1, sequentially form lower metal layer, first medium layer, upper metallization layer on a substrate from the bottom to top; Step S2, execution etching technics, patterning upper metallization layer forms a top capacitor plate, and etching first medium layer forms the interlayer dielectric layer being retained in below the capacitor plate of top; Step S3, one the first insulating barrier of deposition cover on the capacitor plate of top and cover on the exposed upper surface of lower metal layer, and top capacitor plate and the respective sidewall of interlayer dielectric layer are also covered by the first insulating barrier; Step S4, return carve the first insulating barrier, with the thickness of the first insulating barrier above the thinning upper surface being positioned at lower metal layer, the first insulating barrier of top capacitor plate and the side-walls of interlayer dielectric layer is returned simultaneously and is carved into side wall; Step S5, deposition one layer or multi-layer insulation, cover top capacitor plate and side wall, and covered by the first insulating barrier being retained in above the upper surface of lower metal layer; Step S6, etch the first insulating barrier and one layer or multi-layer insulation above it, in order in them, form one or more opening to expose the regional area of lower metal layer; Step S7, by the first insulating barrier and above it one layer or multi-layer insulation as mask, etch and pattern lower metal layer, overlapped on the region below the capacitor plate of top by lower metal layer and form bottom capacitor plate, and in the region that lower metal layer does not overlap on below the capacitor plate of top, form one or more metal interconnection wire.
Above-mentioned preparation method, this upper metallization layer and/or lower metal layer are metal composite layers, and metal composite layer includes metallic intermediate layer and intermetallic metal is clamped in interior underlying metal and top-level metallic.
Above-mentioned preparation method, also defines a second dielectric layer at the disposed thereon of upper metallization layer in step sl, and in the etch step of step S2, the top dielectric layer that patterning second dielectric layer and being formed is positioned at above the capacitor plate of top in the lump.
Above-mentioned preparation method, is positioned at the first insulating barrier above the capacitor plate of top in step s3 and directly overlays on top dielectric layer, and is positioned at a layer above the capacitor plate of top in step s 5 or multi-layer insulation directly overlays on top dielectric layer.
Above-mentioned preparation method, in step S2 in the etching process of first medium layer, except retaining the first medium layer being positioned at below the capacitor plate of top, other parts of first medium layer are all etched and remove.
Above-mentioned preparation method, utilizes anisotropic dry etching to return the first insulating barrier at quarter in step s 4, and removes the first insulating barrier in step s 4 completely and cover the part above the capacitor plate of top.
Above-mentioned preparation method, formation of deposits one is the second insulating barrier of insulant in step s 5, and the material of the second insulating barrier is identical with the material of top dielectric layer.
A kind of mim capacitor structure that the present invention relates to, including: it is arranged on the lower metal layer on a substrate; The bottom capacitor plate separated by lower metal pattern layers and define and metal interconnection wire; Be arranged on bottom capacitor plate upper surface regional area on a top capacitor plate and be positioned at top capacitor plate, bottom capacitor plate interlayer dielectric layer between the two; It is attached to the side wall of the electric insulation of top capacitor plate and interlayer dielectric layer each side-walls.
Above-mentioned MIM capacitor, the first insulating barrier also including being patterned and separate, one part region is attached on the upper surface of each metal interconnection wire, and another part region is also attached on the upper surface not covered by top capacitor plate, interlayer dielectric layer of bottom capacitor plate.
Above-mentioned MIM capacitor, one layer or the multi-layer insulation also including being patterned and separate, a part of region overlay in one layer or multi-layer insulation is on the first insulating barrier being positioned at above each metal interconnection wire, another part region overlay is on the first insulating barrier being positioned at above the capacitor plate of bottom, and side wall and top capacitor plate are also covered by this another part region.
Above-mentioned MIM capacitor, this upper metallization layer and/or lower metal layer are metal composite layers, and metal composite layer includes metallic intermediate layer and intermetallic metal is clamped in interior underlying metal and top-level metallic.
Above-mentioned MIM capacitor, also includes the top dielectric layer being superimposed upon above the capacitor plate of top, and side wall is attached to top dielectric layer, top capacitor plate and interlayer dielectric layer each side-walls simultaneously.
Above-mentioned MIM capacitor, also include the top dielectric layer being superimposed upon above the capacitor plate of top, side wall is also attached to the side-walls of top dielectric layer simultaneously, and wherein this another part region of a layer or multi-layer insulation directly contacts and covers on top dielectric layer.
Above-mentioned MIM capacitor, the material that a layer or multi-layer insulation adopt is identical with the material of top dielectric layer.
Above-mentioned MIM capacitor, this substrate-loading is on a Semiconductor substrate with integrated circuit.
Above-mentioned MIM capacitor, the multilayer insulation substrate and multiple layer metal interconnection layer that alternate interval configuration it is provided with in vertical direction in this semiconductor substrate, being provided with the substrate of one layer of insulation between two arbitrarily neighbouring metal interconnecting layers, wherein this lower metal layer of MIM capacitor is to be positioned at a metal interconnecting layer of top in all of metal interconnecting layer by order from the bottom to top.
Above-mentioned MIM capacitor, also includes the high-density plasma deposit covered above a layer or multi-layer insulation, and this high-density plasma deposit also fills up for separating in one or more grooves of lower metal layer.
Accompanying drawing explanation
After reading described further below and reference the following drawings, inventive feature and advantage will be apparent to:
Figure 1A��1D is the scheme that lower metal layer is etched when relatively thin insulating barrier covers.
Fig. 2 A��2D is the scheme that lower metal layer is etched when thicker insulating barrier covers.
Fig. 3 A��3F is the scheme adhering to side wall on the sidewall of top capacitor plate.
Fig. 4 A��4B is the structure that upper metallization layer and lower metal layer adopt complex metal layer.
Fig. 5 A��5C is that upper and lower metal level adopts the scheme of blanket dielectric layer in complex metal layer and upper metallization layer.
Fig. 6 A��6B is the basic framework that MIM capacitor is supported on a silicon substrate with integrated circuit.
Detailed description of the invention
Below in conjunction with each embodiment; technical scheme is carried out clear complete elaboration; but described embodiment is only the present invention illustrates embodiment used and not all embodiment with being described herein; based on such embodiment, the scheme that those skilled in the art obtains under not making the premise of creative work broadly falls into protection scope of the present invention.
Referring to Figure 1A, on the substrate 101 of an electric insulation, it is formed with the lower metal layer 102 of tool excellent conductive performance and is positioned at the first medium layer 103 above lower metal layer 102, first medium layer 103 is insulant, and is formed above the upper metallization layer 104 of tool excellent conductive performance at first medium layer 103. Lower metal layer 102 and upper metallization layer 104 will be respectively used to two capacitor plates up and down of preparation MIM capacitor, and they can be prepared by the mode of various prior aries, for example with the scheme such as mode of deposition or sputtering or plating, and the material of aluminium copper or the conduction such as tungsten or metallic copper can be adopted to prepare lower metal layer 102 and upper metallization layer 104. After preparation lower metal layer 102 or upper metallization layer 104, although not necessarily operation, but can select and then to carry out the step of cmp to obtain the surface of planarization at their upper surface, this can bring many advantages, for instance the follow-up surface in planarization is easier to generate the comparatively uniform material of thickness. Additionally lower metal layer 102 and upper metallization layer 104 are it is anticipated that design also needs to be made into different figures, so they may pattern because of being etched, it is usually and utilizes photoresist as etch mask, if there is the uneven photoetching process that may result in the upper surface of these metal levels, critical size or live width are lost control, also it is difficult to, self having making figure on the photoresist of step difference, grind and be polished, these negative factors can be avoided simultaneously. We also require that the first medium layer 103 between two capacitor plates up and down in MIM capacitor has good insulating properties and meets desired dielectric constant, the computing formula of common its capacitance of plane-parallel capacitor is C=�� �� S/d, �� in this functional relation is the dielectric material between capacitor plate namely the dielectric constant of first medium layer 103, S in functional relationship is the effective area between pole plate, and its value is determined by the capacitor plate that area is less. Consider that the present invention is about to the size being smaller in size than bottom capacitor plate 102A of the top capacitor plate 104A introduced hereinafter, so this effective area S essence refers to the area of top capacitor plate 104A. And the d in functional relation is the distance between pole plate namely the thickness of first medium layer 103. In certain embodiments, silicon dioxide or silicon nitride or Ta2O5Deng be all this first medium layer 103 can material selection.
Referring to Figure 1A, first spin coating one layer photoetching glue-line 105 above upper metallization layer 104, after the exposure imaging of photoetching process, retain a part of predetermined photoresist layer 105, and utilize the photoresist layer 105 of reservation thereby to etch the region that upper metallization layer 104 comes out as mask. As shown in Figure 1B, upper metallization layer 104 is only retained that part being positioned at below retained photoresist layer 105 after dry etching, the present invention is defined as it within a context for top capacitor plate 104A, and this process is also the process of patterning upper metallization layer 104. Last till for the etching of upper metallization layer 104 and expose first medium layer 103, and first medium layer 103 is also etched further, but the etching of first medium layer 103 and upper metallization layer 104 is slightly different, it is embodied in: upper metallization layer 104 is not photo-etched the region that glue-line 105 covers and is all removed, and first medium layer 103 is not photo-etched the region of glue-line 105 and top capacitor plate 104A covering because etching, it is only slightly lose on thickness, but this region also retains the first medium layer 103 of a part of thickness. The result of the program is exactly, cause that first medium layer 103 is positioned at the part below photoresist layer 105 and top capacitor plate 104A and keeps original thickness, but the thickness of another part that first medium layer 103 is not photo-etched glue-line 105 and top capacitor plate 104A covers is then less than original thickness, this from Figure 1B it is observed that. Thereafter spin coating one layer photoetching glue-line 106 above the capacitor plate 104A of top and above that part that first medium layer 103 is thinned again, as shown in Figure 1 C, after the exposure imaging of photoetching process, photoresist layer 106 is formed patterns of openings, and the region that utilize the photoresist layer 106 of reservation thereby to etch as mask that part that first medium layer 103 is thinned comes out, such that it is able to define some openings in that part that first medium layer 103 is thinned. Continue those regional areas that etching lower metal layer 102 comes out from opening part afterwards, etching lasts till that mode desirably patterns lower metal layer 102, for instance at least forms bottom capacitor plate 102A and forms some metal interconnection wire 102C and 102B etc. for realizing electric interconnection. Specifically as shown in figure ip, lower metal layer 102 overlaps on the region below the capacitor plate 104A of top can form a bottom capacitor plate 102A, then can form one or more metal interconnection wire 102B and 102C etc. in that a part of region that lower metal layer 102 does not overlap mutually with top capacitor plate 104A. Because we are from the angle of profile to observe bottom capacitor plate 102A and metal interconnection wire 102C and 102B in Fig. 1 D, they seem be off discrete, but if it is necessary, also can also select to be physically connected on the capacitor plate 102A of bottom a part of interconnection line in metal interconnection wire 102C and 102B etc. Preparation technology according to Figure 1A��1D, one stubborn problem is, after photoresist layer 106 is removed or is consumed in this etch step of patterning, because lower metal layer 102 and top capacitor plate 104A adopt metal material, so being easy to the polymer 203 producing to be mixed with fine metal material granule in this etch step, the source that granule produces is exactly metallized upper and lower capacitor plate. The polymer 203 of tool electric conductivity is very easily attached on the exposed sidewall of top capacitor plate 104A, and when that a part of region being thinned of first medium layer 103 is because self is very thin, it is easy to it is completely removed in this etch step.Just the negative results that those skilled in the art is reluctant to see is created thus, namely the top capacitor plate 104A and bottom capacitor plate 102A of MIM capacitor is by being attached to polymer 203 on the sidewall of top capacitor plate 104A and together with electrical couplings, causing short-circuit failure.
Referring to the embodiment of Fig. 2 A, perform the operation identical with Figure 1A��1B in advance, but Fig. 2 B is but additionally prepared for first insulating barrier 107 and second insulating barrier 108. the first insulating barrier 107 deposited, except covering the top of top capacitor plate 104A, also covers the top of that part that first medium layer 103 is thinned, and wherein the first insulating barrier 107 generally can adopt the insulant such as silicon dioxide or silicon nitride. the second insulating barrier 108 deposited then covers the top of the first insulating barrier 107 comprehensively, and this second insulating barrier 108 can be one layer of inorganic thin film, for instance can adopt silicon oxynitride film (SION). thereafter one layer of photoresist of spin coating namely photoresist layer 109 above the second insulating barrier 108 again, as shown in Figure 2 C, after the exposure imaging of photoetching process, forms some patterns of openings in photoresist layer 109. in fig. 2 c, that a part of region, the first insulating barrier 107 and second this three of insulating barrier 108 that first medium layer 103 is thinned is superimposed and forms a lamination 110, and this lamination 110 is positioned at not having and top capacitor plate 104A that a part of overlying regions overlapped mutually of lower metal layer 102. that retain and with patterns of openings photoresist layer 109 is utilized thereby to come, as mask, the region that etching stack 110 comes out from photoresist layer 109, such that it is able to define some openings in this lamination 110. continue some regional areas that etching lower metal layer 102 comes out from those opening parts of lamination 110 afterwards, and this etching is continued until that final mode desirably patterns lower metal layer 102, for instance at least need form a bottom capacitor plate 102A and form some metal interconnection wire 102C and 102B etc. for realizing electric interconnection. as shown in Figure 2 D, lower metal layer 102 overlaps on the region below the capacitor plate 104A of top can form a bottom capacitor plate 102A, another part of lower metal layer 102 not then can not form one or more metal interconnection wire 102B and 102C etc. with the top capacitor plate 104A region overlapped mutually, and lower metal layer 102 split gained bottom capacitor plate 102A be slightly larger in dimension than top capacitor plate 104A. because in the step of etching lower metal layer 102, that a part of region that first medium layer 103 is thinned, first insulating barrier 107 and second this three of insulating barrier 108 thickness of lamination 110 formed that is superimposed is relatively thick, and cover the top of top capacitor plate 104A and cover the first insulating barrier 107 of its sidewall and the second insulating barrier 108 is also relatively thick, so after namely box lunch photoresist layer 109 is removed after photoetching or is etched in the etch step of patterning and consumes, because the existence of lamination 110, and also have the existence of the first insulating barrier 107 and the second insulating barrier 108 covering on the sidewall of top capacitor plate 104A, even creating the polymer of tool electric conductivity, it is not easy to be attached on the sidewall of top capacitor plate 104A thus being unlikely to top capacitor plate 104A and bottom capacitor plate 102A at side-walls short circuit also, so the doubt mentioned in Fig. 1 D above is solved. but meanwhile, bringing again the thorny problem that other are new, shown in Fig. 2 D, because the time etching thicker lamination 110 and lower metal layer 102 is relatively long, when lamination 110 exposes from photoresist layer 109 time, how much it also can be partially etched.Consider that lamination 110 is relatively thick, so the opening in lamination 110 seems relatively deep, be equivalent to that there is high-aspect-ratio. in figure 2d, this lower metal layer 102 is etched and forms some grooves 211 of separating lower metal layer 102, the lower section of the opening that these grooves 211 are substantially docked in lamination 110. along with the etching process of lower metal layer 102 also can synchronize to allow each edge of lamination 110 etched, comparatively it is apparent that in Fig. 2 D, the edge of those a part of both sides that lamination 110 is positioned on metal interconnection wire 102C is etched, the edge of those a part of both sides that lamination 110 is positioned on metal interconnection wire 102B is also etched, and the edge of another part that lamination 110 is positioned on the capacitor plate 102A of bottom is equally also etched. in this, unexpected over etching can bring many disadvantageous negative effects, such as cause that the part that lamination 110 is positioned on metal interconnection wire 102C and metal interconnection wire 102B even becomes the wedge structure with corners, its width is progressively linearly increasing successively from top to bottom, it is believed that the vertical section of this part lamination 110 is the del that top is the most sharp-pointed. passivation is prepared in rear extended meeting on the second insulating barrier 108, mode as deposited by high-density plasma (highdensityplasma) is generated deposit and covers the second insulating barrier 108 and fill groove 211, the plasma process of higli density plasma deposition process may aggravate the acuity of the part that lamination 110 is positioned on metal interconnection wire 102C and metal interconnection wire 102B potentially, plasma is caused to bring out damage (PlasmaInduceDamage is called for short PID), cause that high-density plasma deposit (as mixing the silica glass of F fluorine element) may form good composition surface on the lamination 110 of this irregularly shaped structure, and the electrical parameter of device can be affected, because it is follow-up it is also possible to need the through hole (internal filler metal) forming alignment metal interconnection wire 102C and metal interconnection wire 102B in high-density plasma deposit to be used for being electrically connected. in a word, the shape without wishing to the distortion produced of lamination 110 needs to do one's utmost to avoid, because it can worsen the physical arrangement of whole device from every aspect and be negatively affected to the properly functioning of device.
Referring to Fig. 3 A, performing the operation identical with Figure 1A��1B in advance, but be slightly different with this embodiment, first medium layer 103 and upper metallization layer 104 synchronize to be performed etching and patterning. can find that in Figure 1A��1B, etching stopping is on first medium layer 103 through contrast, make first medium layer 103 not be photo-etched region that glue 105 shelters from is by slightly thinning but still exist, and first medium layer 103 is photo-etched the region that glue 105 shelters from and then directly keeps original thickness. but in figure 3 a, etching stopping is at the upper surface of lower metal layer 102, namely except upper metallization layer 104 is not photo-etched except the region that glue 105 shelters from is completely etched away, first medium layer 103 is not photo-etched the region that glue 105 shelters from and is completely etched away without any reservation yet. final upper metallization layer 104 patterning is subsequently formed the top capacitor plate 104A being positioned at below photoresist 105, first medium layer 103 patterning is subsequently formed the interlayer dielectric layer 103A being positioned at below the capacitor plate 104A of top, the patterning process of this namely first medium layer 103 and upper metallization layer 104. thereafter one layer of first insulating barrier 201 is also deposited, for example with the insulant such as silicon dioxide or silicon nitride, notice that the first insulating barrier 201 covers on the exposed upper surface out of lower metal layer 102, here the exposed part out of lower metal layer 102 namely its region of not sheltered from by interlayer dielectric layer 103A and top capacitor plate 104A, and the first insulating barrier 201 also covers on interlayer dielectric layer 103A and the top respective sidewall of capacitor plate 104A. first insulating barrier 201 has two main usess, and the first forms side wall, and it two is cover on the exposed upper surface of lower metal layer 102. after the first insulating barrier 201 is reversed vertical etch, namely perform to form a desired side wall 201A structure on interlayer dielectric layer 103A and the top respective sidewall of capacitor plate 104A time quarter (Blanketetching) comprehensively, carve by dry back makes the part that the first insulating barrier 201 covers on the capacitor plate 104A of top be disposed of simultaneously, but the first insulating barrier 201 of the overlying regions that lower metal layer 102 is not sheltered from by interlayer dielectric layer 103A and top capacitor plate 104A is then retained when, due to the reason being partially etched on thickness, the thickness of the part that the first insulating barrier 201 is positioned on the upper surface of lower metal layer 102 relatively its original thickness also can reduce.
Referring to Fig. 3 B, one layer or more multi-layered insulant can be deposited, thus covering top capacitor plate 104A and side wall 201A, meanwhile, it is retained in above the upper surface of lower metal layer 102 and is that a part of first insulating barrier 201 after being thinned also is covered by one layer or more multi-layered insulant. for exemplary explaination, Fig. 3 B show only one layer of insulant, hereinafter will be defined as the second insulating barrier 202, and this second insulating barrier 202 can be one layer of inorganic thin film, for instance can adopt silicon oxynitride film (SION). one layer of photoresist of spin coating namely photoresist layer 203 above the second insulating barrier 202 more afterwards, as shown in Figure 3 C, after the exposure imaging of photoetching process, forms some patterns of openings in photoresist layer 203. in fig. 3 c, both that a part of region that first insulating barrier 201 is thinned and the second insulating barrier 202 are superimposed one lamination 208 of formation, this lamination 208 be positioned at lower metal layer 102 not and top capacitor plate 104A that a part of overlying regions overlapped mutually. that retain and with patterns of openings photoresist layer 203 is utilized thereby to come, as mask, the region that etching stack 208 comes out from photoresist layer 203, such that it is able to define some openings 210 in this lamination 208. continue some regional areas that etching lower metal layer 102 comes out from those openings 210 of lamination 208 afterwards, as shown in Figure 3 D, and this etching is continued until that final mode desirably patterns lower metal layer 102, such as at least need form a bottom capacitor plate 102A and form some metal interconnection wire 102C and 102B etc. for interconnecting, as shown in FIGURE 3 E. lower metal layer 102 forms the some grooves 211 for separating lower metal layer 102 therein after being etched, the underface of the substantially corresponding opening 210 being arranged in lamination 208 of each groove 211. lower metal layer 102 overlaps on the region below the capacitor plate 104A of top can form a bottom capacitor plate 102A, another part of lower metal layer 102 not then can not form one or more metal interconnection wire 102B and 102C etc. with the top capacitor plate 104A region overlapped mutually, and lower metal layer 102 split gained bottom capacitor plate 102A be slightly larger in dimension than top capacitor plate 104A. because in the step of etching lower metal layer 102, the be superimposed thickness of the lamination 208 formed of both that a part of region that first insulating barrier 201 is thinned and the second insulating barrier 202 is relatively suitable, the such as thickness of that part that the first insulating barrier 201 is thinned is right at 50��200 Izods, the thickness of the second insulating barrier 202 is right at 150��450 Izods, and side wall 201A is attached to top capacitor plate 104A and the respective side-walls of interlayer dielectric layer 103A, namely after box lunch photoresist layer 203 is removed after photoetching or is etched in the patterning etch step of lower metal layer 102 and consumes, because the existence of lamination 208, and also have the existence of side wall (Spacer) 201A and the second insulating barrier 202, even if creating polymer to be not easy also to be attached on the sidewall of top capacitor plate 104A thus being unlikely to top capacitor plate 104A and bottom capacitor plate 102A at side-walls short circuit. the etching of lamination 208 and lower metal layer 102, unlike so thickness of the lamination 110 of Fig. 2 C, is not needed long time by the lamination 208 in Fig. 3 E yet.Although along with the etching process of lower metal layer 102 may allow the end face of the lamination 208 come out from photoresist 203 slightly lose, but when lower metal layer 102 finishing patterns time, the end face of lamination 208 can't occur to distort as Fig. 2 D, the edge of those a part of both sides that lamination 2080 is positioned on metal interconnection wire 102C, 102B is etched hardly, so we are still it is believed that the end face of lamination 208 is now the end face of planarization. Passivation is prepared in rear extended meeting on the second insulating barrier 202, mode as deposited by high-density plasma (highdensityplasma) is generated deposit 220 and covers the second insulating barrier 202, and a part for high-density plasma deposit 220 also fills up in groove 211.
Referring to Fig. 4 A, with each embodiment above is slightly different it is, in this alternative, this upper metallization layer 102 and/or lower metal layer 104 are the metal structures of metal composite layer rather than monolayer, and metal composite layer 104 includes metallic intermediate layer (such as aluminium copper, metallic copper, tungsten etc.) 104-2 and intermetallic metal 104-2 is clamped in interior underlying metal (as being positioned at the titanium nitride etc. of bottom) 104-1 and top-level metallic (as being positioned at the titanium nitride etc. at top) 104-3. Same metal composite layer 102 includes metallic intermediate layer (such as aluminium copper, metallic copper, tungsten etc.) 102-2 and intermetallic metal 102-2 is clamped in interior underlying metal (as being positioned at the titanium nitride etc. of bottom) 102-1 and top-level metallic (as being positioned at the titanium nitride etc. at top) 102-3. Corresponding MIM capacitor is as shown in Figure 4 B, top capacitor plate 104A is patterned so their structure is identical by metal composite layer 104, and same metal interconnection wire 102B and 102C and bottom capacitor plate 102A is patterned by metal composite layer 102 so their structure is identical. Now the second insulating barrier 202 directly covers and contacts on the top-level metallic 104-3 at capacitor plate 104A top, top, first insulating barrier 201 directly covers with on the top-level metallic 102-3 contacting capacitor plate 102A top, bottom, and the first insulating barrier 201 also directly covers and on the top-level metallic 102-3 at contacting metal interconnection line 102B and 102C top.
Referring to Fig. 5 A, with the embodiment of figure 4 above A��4B is slightly different it is, in this alternative, before patterning upper metallization layer 104, one layer of second dielectric layer 104-4 is deposited in advance in upper metallization layer 104, this second dielectric layer 104-4 can be one layer of inorganic thin film, for instance can adopt silicon oxynitride film (SION). In this alternative, when first medium layer 103 and upper metallization layer 104 being performed etching and forming interlayer dielectric layer 103A and top capacitor plate 104A, need the top dielectric layer 104-4A that patterning second dielectric layer 104-4 and being formed is positioned at above the capacitor plate 104A of top in the lump, in time going back to the first insulating barrier 201 at quarter, top dielectric layer 104-4A can from the first insulating barrier 201 exposed out, as shown in Figure 5 B. Second insulating barrier 202 of subsequent deposition, except covering on the part that the first insulating barrier 201 is thinned, also directly contacts and covers on side wall 201A and top dielectric layer 104-4A, such as Fig. 5 C. Except these difference schemes, other flow processs of Fig. 5 A��5C are identical with Fig. 3 A��3F.
Referring to Fig. 6 A, the MIM capacitor that the present invention mentions is except can be used alone, can also and a Semiconductor substrate 100 with integrated circuit integrate, refer to the Semiconductor substrate 100 of integrated circuit and substrate 100 can be prepared various suitable active or passive component, and substrate 101 is just carried on above this Semiconductor substrate 100. Explain this point as an example, shown in Fig. 6 B, it is integrated with CMOS transistor in substrate 100, in the well region 310 of a P conduction type, preparation has source area 311 and the drain region 312 of N conduction type, and the well region 310 between source area 311 and drain region 312 be formed above grid structure 313, namely form a nmos pass transistor 301. In the well region 320 of a N conduction type, preparation has source area 321 and a drain region 322 of P conduction type, and the well region 320 between source area 321 and drain region 322 be formed above grid structure 323, namely form a PMOS transistor 302. And P type trap zone 310 and N-type well region 320 are separated by fleet plough groove isolation structure STI. The top of Semiconductor substrate 100 is coated with the boron-phosphorosilicate glass BPSG of insulation or similar dielectric base, it is formed over metal interconnecting layer (interconnectionmetallayer) 330 at boron-phosphorosilicate glass, metal interconnecting layer 330 can also be referred to as first layer metal interconnection layer (M1), and each electrode of nmos pass transistor 301 and PMOS transistor 302 can be electrically connected on a part of line in metal interconnecting layer 330 by the metal material filled in through hole 340. Certainly, in vertical direction, metal interconnecting layer and dielectric base (dielectric base can also be stated with interlayer insulating film or similar term) of more level can be prepared above Semiconductor substrate 100, and multilayer insulation substrate and multiple layer metal interconnection layer alternate interval configuration, are provided with the substrate of one layer of insulation between two arbitrarily neighbouring metal interconnecting layers. It is directed to outside thus being coupled by each layer interconnection layer by the electrode of the components and parts in Semiconductor substrate 100 by this way. This lower metal layer 102 of the MIM capacitor that the present invention relates to can be such as be positioned at a metal interconnecting layer of top in all of metal interconnecting layer by order from the bottom to top. Such as assume there are (M1��M4) four layers of metal interconnecting layer, wherein M1 is positioned at they central bottoms and M2 takes second place, and M3 above M2 M4 above M3, so lower metal layer 102 can be just the metal level M4 of the top, so would not affect the operation of routine when preparing electric capacity. Additionally what deserves to be explained is, Fig. 6 B is only used to prove that the MIM capacitor of the present invention can carry out highly integrated with the Semiconductor substrate 100 with integrated circuit, and does not mean that MIM capacitor shall be limited only to carry out integrated with CMOS. Such as, in Semiconductor substrate 100 can also be integrated be junction field effect transistor or bipolar transistor etc., or the transistor etc. with the grid of plough groove type rather than the grid of plane, or passive device rather than the active device etc. such as integrated resistor inductance, or integrated digital circuit and/or analog circuit and/or memory device etc., in a word, Semiconductor substrate 100 here can be prepared the various components and parts of any existing integrated circuit (Integratedcircuit).
Above, by illustrating and accompanying drawing, giving the exemplary embodiments of the ad hoc structure of detailed description of the invention, foregoing invention proposes existing preferred embodiment, but these contents are not intended as limitation. For a person skilled in the art, after reading described above, various changes and modifications will be apparent to undoubtedly. Therefore, appending claims should regard whole variations and modifications of the true intention containing the present invention and scope as. In Claims scope, the scope of any and all equivalence and content, be all considered as still belonging to the intent and scope of the invention.
Claims (17)
1. the preparation method of a MIM capacitor, it is characterised in that comprise the following steps:
Step S1, on a substrate, sequentially form lower metal layer, first medium layer, upper metallization layer from the bottom to top;
Step S2, execution etching technics, patterning upper metallization layer forms a top capacitor plate, and etching first medium layer forms the interlayer dielectric layer being retained in below the capacitor plate of top;
Step S3, one the first insulating barrier of deposition cover on the capacitor plate of top and cover on the exposed upper surface of lower metal layer, and top capacitor plate and the respective sidewall of interlayer dielectric layer are also covered by the first insulating barrier;
Step S4, return carve the first insulating barrier, with the thickness of the first insulating barrier above the thinning upper surface being positioned at lower metal layer, the first insulating barrier of top capacitor plate and the side-walls of interlayer dielectric layer is returned simultaneously and is carved into side wall;
Step S5, deposition one layer or multi-layer insulation, cover top capacitor plate and side wall, and covered by the first insulating barrier being retained in above the upper surface of lower metal layer;
Step S6, etch the first insulating barrier and one layer or multi-layer insulation above it, in order in them, form one or more opening to expose the regional area of lower metal layer;
Step S7, by the first insulating barrier and above it one layer or multi-layer insulation as mask, etch and pattern lower metal layer, overlapped on the region below the capacitor plate of top by lower metal layer and form bottom capacitor plate, and in the region that lower metal layer does not overlap on below the capacitor plate of top, form one or more metal interconnection wire.
2. the preparation method of a kind of MIM capacitor according to claim 1, it is characterized in that, this upper metallization layer and/or lower metal layer are metal composite layers, and metal composite layer includes metallic intermediate layer and intermetallic metal is clamped in interior underlying metal and top-level metallic.
3. the preparation method of a kind of MIM capacitor according to claim 1, it is characterized in that, also define a second dielectric layer at the disposed thereon of upper metallization layer in step sl, and in the etch step of step S2, the top dielectric layer that patterning second dielectric layer and being formed is positioned at above the capacitor plate of top in the lump.
4. the preparation method of a kind of MIM capacitor according to claim 3, it is characterized in that, it is positioned at the first insulating barrier above the capacitor plate of top in step s3 to directly overlay on top dielectric layer, and is positioned at a layer above the capacitor plate of top in step s 5 or multi-layer insulation directly overlays on top dielectric layer.
5. the preparation method of a kind of MIM capacitor according to claim 1, it is characterized in that, in step S2 in the etching process of first medium layer, except retaining the first medium layer being positioned at below the capacitor plate of top, other parts of first medium layer are all etched and remove.
6. the preparation method of a kind of MIM capacitor according to claim 1, it is characterized in that, utilize anisotropic dry etching to return the first insulating barrier at quarter in step s 4, and remove the first insulating barrier in step s 4 completely and cover the part above the capacitor plate of top.
7. the preparation method of a kind of MIM capacitor according to claim 3, it is characterised in that formation of deposits one is the second insulating barrier of insulant in step s 5, and the material of the second insulating barrier is identical with the material of top dielectric layer.
8. a MIM capacitor, it is characterised in that including:
It is arranged on the lower metal layer on a substrate;
The bottom capacitor plate separated by lower metal pattern layers and define and metal interconnection wire;
Be arranged on bottom capacitor plate upper surface regional area on a top capacitor plate and be positioned at top capacitor plate, bottom capacitor plate interlayer dielectric layer between the two;
It is attached to the side wall of the electric insulation of top capacitor plate and interlayer dielectric layer each side-walls.
9. a kind of MIM capacitor according to claim 8, it is characterized in that, the first insulating barrier also including being patterned and separate, one part region is attached on the upper surface of each metal interconnection wire, and another part region is also attached on the upper surface not covered by top capacitor plate, interlayer dielectric layer of bottom capacitor plate.
10. a kind of MIM capacitor according to claim 9, it is characterized in that, one layer or the multi-layer insulation also including being patterned and separate, a part of region overlay in one layer or multi-layer insulation is on the first insulating barrier being positioned at above each metal interconnection wire, another part region overlay is on the first insulating barrier being positioned at above the capacitor plate of bottom, and side wall and top capacitor plate are also covered by this another part region.
11. a kind of MIM capacitor according to claim 8, it is characterised in that this upper metallization layer and/or lower metal layer are metal composite layers, and metal composite layer includes metallic intermediate layer and intermetallic metal is clamped in interior underlying metal and top-level metallic.
12. a kind of MIM capacitor according to claim 8, it is characterised in that also include the top dielectric layer being superimposed upon above the capacitor plate of top, and side wall is attached to top dielectric layer, top capacitor plate and interlayer dielectric layer each side-walls simultaneously.
13. a kind of MIM capacitor according to claim 10, it is characterized in that, also include the top dielectric layer being superimposed upon above the capacitor plate of top, side wall is also attached to the side-walls of top dielectric layer simultaneously, and wherein this another part region of a layer or multi-layer insulation directly contacts and covers on top dielectric layer.
14. a kind of MIM capacitor according to claim 13, it is characterised in that the material that a layer or multi-layer insulation adopt is identical with the material of top dielectric layer.
15. a kind of MIM capacitor according to claim 8, it is characterised in that this substrate-loading is on a Semiconductor substrate with integrated circuit.
16. a kind of MIM capacitor according to claim 15, it is characterized in that, the multilayer insulation substrate and multiple layer metal interconnection layer that alternate interval configuration it is provided with in vertical direction in this semiconductor substrate, being provided with the substrate of one layer of insulation between two arbitrarily neighbouring metal interconnecting layers, wherein this lower metal layer of MIM capacitor is to be positioned at a metal interconnecting layer of top in all of metal interconnecting layer by order from the bottom to top.
17. a kind of MIM capacitor according to claim 10, it is characterized in that, also include the high-density plasma deposit covered above a layer or multi-layer insulation, and this high-density plasma deposit also fills up for separating in one or more grooves of lower metal layer.
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| CN113517400A (en) * | 2021-09-13 | 2021-10-19 | 广州粤芯半导体技术有限公司 | Metal capacitor structure and preparation method thereof |
| CN113517401A (en) * | 2021-09-13 | 2021-10-19 | 广州粤芯半导体技术有限公司 | Metal capacitor structure and preparation method thereof |
| CN116322297A (en) * | 2023-05-17 | 2023-06-23 | 粤芯半导体技术股份有限公司 | MIM capacitor and preparation method thereof |
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