CN105630732B - A kind of hot change-over method of duplication redundancy microprocessor - Google Patents
A kind of hot change-over method of duplication redundancy microprocessor Download PDFInfo
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- CN105630732B CN105630732B CN201510955157.4A CN201510955157A CN105630732B CN 105630732 B CN105630732 B CN 105630732B CN 201510955157 A CN201510955157 A CN 201510955157A CN 105630732 B CN105630732 B CN 105630732B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
- G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
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Abstract
The invention discloses a kind of hot change-over methods of duplication redundancy microprocessor, purpose is, better processor state monitoring and fault-tolerant effect are provided, and the ability for making it have hot-swap, to improve Stability and adaptability of the embedded microprocessor under radiation environment, used technical solution is：Establish duplication redundancy processor decision logic, command status machine, address are accessed respectively, Data Stream Processing and processor state are monitored, to which processor state is evaluated, second processor rests on idle state when reset, first processor sequence executes the command content in memory, until mistake occurs in first processor, processor switching can occur at this time, bus switch logic can cut off the data path of first processor, it transfers second processor to, while handoff request is sent out to second processor；Second processor uses the data in shared data memory, restores the execution state of first processor and continues to execute instruction, to realize hot-swap.
Description
Technical field
The present invention relates to a kind of design method of duplication redundancy processor more particularly to a kind of duplication redundancy microprocessors
Hot change-over method.
Background technology
Existing microprocessor system usually using single-core processor as control core, once control core occur therefore
Barrier, usually can only repair soft error, then helpless for hardware error.
Redundancy copes with equipment fault by hardware redundancy.Amount of redundancy is typically 3 or more EM equipment modules
It works at the same time, this makes the power consumption, volume, resource occupation of equipment become original 3 times or more, and pole does not meet microprocessor
Application scenario brings great difficulty to the design of microprocessor system.
Duplication redundancy technology refers to that two identical subsystems or module are used in same system, between two modules
It backups each other, can be overhauled and be switched automatically.It, can be by less compared to triplication redundancy even multimode redundant system
Amount of redundancy reaches preferable fault-tolerant effect.With reference to figure 1, dual-modular redundancy system is usually made of following components：
Functional circuit is the modular circuit that main function of system is completed in subsystem；Self-detection circuit passes through to functional circuit
Status monitoring, realize the function self-test of subsystem；
Decision logic is made decisions by collecting the running state information of two subsystems, to which which subsystem operation obtained
State is normal, and attempts to repair abnormal subsystem；
Switch logic gates data/address bus according to court verdict, realizes the switching between subsystem.
It is hard using resetting usually using house dog as self-detection circuit for existing duplication redundancy processor
The mode of switching switches two processor.The mode of data exchange or data exchange can not be carried out between two processor more
Complexity needs to carry out data exchange by additional component.One side existence context of detection there are inexactnesies, can only
Detect the mistake of cycle interruption, it is difficult to find the mistake in instruction cycles, conditional jump and data calculating process；On the other hand,
Data exchange difficulty causes two processor that can not hand over to working condition on additional processor rapidly so that switching time-histories
The execution efficiency of sequence is very low.
Invention content
In order to solve the problems in the prior art, the present invention propose one kind be capable of providing the monitoring of better processor state and
Fault-tolerant effect, and the ability for making it have hot-swap, to improve stability of the embedded microprocessor under radiation environment and
The hot change-over method of the duplication redundancy microprocessor of adaptability.
In order to achieve the goal above, the technical solution adopted in the present invention includes the following steps：
1) duplication redundancy processor decision logic is established：Respectively to command status machine, address access, Data Stream Processing and place
Reason device state is monitored, and is evaluated processor state；
2) hot-swap based on duplication redundancy processor decision logic：Second processor receives do-nothing instruction, rests on the free time
State, first processor sequence executes the command content in memory at this time can point until mistake occurs in first processor
Device switching is managed, switch logic can change the mark for the processor being carrying out, and this information is passed to bus switch logic；
Bus switch logic can cut off the data path of first processor, transfer second processor to, while sending out to second processor
Go out handoff request；When second processor receives handoff request, initial phase is skipped, is stored using shared data
Data in device restore the execution state of first processor and continue to execute instruction, to realize hot-swap.
The monitoring of described instruction state machine includes：The state of command status machine is recompiled using Gray code, is made
Code distance between two states it is constant be 1, for being inserted into additional dummy status among the part that cannot encode, when command status machine goes out
Existing code distance is not 1 when redirecting, and generates abnormal signal, and repair by being resetted to command status electromechanics road.
Described address accesses monitoring：The internal storage access of monitoring processor, when processor is attempted to access in illegal
When depositing address, abnormal signal is generated, and repaired by address of reruning.
The Data Stream Processing monitors：Error detection point is inserted on data processing access, by using error correction to data
Error detection mode is reinforced, when data in processing procedure when the error occurs, by error correcting and detecting code check data correctness,
When there is wrong data, abnormal signal is generated, and restore by the error correcting and detecting ability of data itself.
Data are reinforced using Hamming code or Berger code error correcting and detecting modes in the Data Stream Processing monitoring.
The processor state monitoring and evaluation include：House dog logic is set, entirety is carried out to processor and decision logic
Monitoring, and collect command status machine, address access and three part abnormal signals of Data Stream Processing, to the work shape of processor
State makes assessment, and makes corresponding repair process.
The processor state evaluation uses the practice condition of the form assessment processing device of score-sheet, if processor occurs
Multiple mistake then carries out the task switching of processor, and state evaluation logic uses the mode tissue of single mode, or superfluous using three moulds
Remaining mode is reinforced.
The first processor and second processor are reset on startup, and first processor connects peripheral bus and instruction
The value operation of rambus, second processor is assigned 0, and second processor obtains the do-nothing instruction of full 0, rests on idle state,
First processor sequence executes the command content in memory.
The first processor and second processor access memory by different ports, and memory is using check bit
Mode carries out redundancy.
Compared with prior art, the present invention establishes duplication redundancy processor decision logic, respectively to command status machine, address
Access, Data Stream Processing and processor state are monitored, and are evaluated processor state, and second processor rests on sky
Not busy state, first processor sequence, which executes the command content in memory, can occur at this time until mistake occurs in first processor
Processor switches, and switch logic can change the mark for the processor being carrying out, and this information is passed to bus switch and is patrolled
Volume；Bus switch logic can cut off the data path of first processor, transfer second processor to, while to second processor
Send out handoff request；When second processor receives handoff request, initial phase is skipped, is deposited using shared data
Data in reservoir restore the execution state of first processor and continue to execute instruction, to realize hot-swap, using the present invention
Method on the basis of original duplication redundancy processor designs, increase less circuit, can be into line number between two processor
According to exchange, processor can hand over to working condition on additional processor rapidly, provide better processor state monitoring
With fault-tolerant effect, and the ability for making it have hot-swap, to improve stability of the embedded microprocessor under radiation environment
And adaptability.
Further, in the present invention, decision logic can select suitable mode to handle according to different grades of exception,
It is abnormal for command status machine, by achieving the purpose that reparation to modular circuit reset；For data flow anomaly, pass through data
The error correcting and detecting ability of itself is restored；When unknown exception occurs, found by watchdog circuit, and by processor into
Row hot-swap is handled.
Further, monitoring result submits to processor state assessment logic, carries out the judgement that processor executes state, state
Assessing logic can be located using the practice condition of the form assessment processing device of score-sheet if multiple mistake occurs in processor
Manage device task switching, state evaluation logic can use single mode mode tissue, can also use triplication redundancy mode into
The reinforcing of row high reliability.
Further, word is usually pressed in the access of data storage and byte carries out, and is needed at this time by data storage by access
The difference of mode, using the separated form tissue of high low byte.The two processor of the present invention is accessed by different ports
Memory, memory the mode for increasing check bit can be used to carry out Redundancy Design, increase the reliability of storage.
Description of the drawings
Fig. 1 is typical dual-modular redundancy system composition；
Fig. 2 is the processor state decision logic of the present invention；
Fig. 3 is the system structure of processor state decision logic of the present invention；
Fig. 4 is processor switching flow in the present invention；
Fig. 5 a are the coding modes of traditional instruction cycles；Fig. 5 b are the coding modes of instruction cycles in the present invention；
Fig. 6 is the organizational form of data storage in the present invention.
Specific implementation mode
The present invention is further explained with reference to specific embodiment and Figure of description.
The present invention includes the following steps：
1) duplication redundancy processor decision logic is established：Respectively to command status machine, address access, Data Stream Processing and place
Reason device state is monitored, and is evaluated processor state；
2) hot-swap based on duplication redundancy processor decision logic：First processor and second processor pass through different
Port accesses memory, and memory carries out redundancy by the way of check bit, and first processor and second processor are on startup
It is reset, first processor connects peripheral bus and instruction memory bus, and the value operation of second processor is assigned 0, at second
Reason device obtains the do-nothing instruction of full 0, rests on idle state, and first processor sequence executes the command content in memory, until
There is mistake in first processor, and processor switching can occur at this time, and switch logic can change the mark for the processor being carrying out,
And this information is passed into bus switch logic；Bus switch logic can cut off the data path of first processor, transfer
Handoff request is sent out to second processor, while to second processor；When second processor receives handoff request,
Initial phase is skipped, using the data in shared data memory, restores the execution state of first processor and continues to execute
Instruction, to realize hot-swap.
The monitoring of command status machine includes：The state of command status machine is recompiled using Gray code so that two
Constant code distance between state is 1, for being inserted into additional dummy status among the part that cannot encode, when code occurs in command status machine
Away from not for 1 when redirecting, generating abnormal signal, and repaired by being resetted to command status electromechanics road；Address accesses monitoring
Including：The internal storage access of monitoring processor generates abnormal signal when processor is attempted to access illegal memory address, and
By reruning, address is repaired；Data Stream Processing monitors：Error detection point is inserted on data processing access, by data
Reinforced using using Hamming code or Berger code error correcting and detecting modes, when data in processing procedure when the error occurs, it is logical
The correctness that error correcting and detecting code checks data is crossed, when there is wrong data, generates abnormal signal, and entangling by data itself
Wrong error detecing capability restores.
Processor state monitors and evaluation includes：House dog logic is set, whole prison is carried out to processor and decision logic
Control, and command status machine, address access and three part abnormal signals of Data Stream Processing are collected, the working condition of processor is done
Go out assessment, and makes corresponding repair process.Processor state evaluation uses the execution shape of the form assessment processing device of score-sheet
Condition carries out the task switching of processor if multiple mistake occurs in processor, and state evaluation logic uses the mode group of single mode
It knits, or is reinforced using the mode of triplication redundancy.
The present invention includes mainly two parts：In duplication redundancy processor the structure of decision logic and be based on the decision logic
Hot-swap flow.
Processor state decision logic：Referring to Fig. 2 and Fig. 3, the present invention devises a kind of judgement of duplication redundancy processor
Logic.It is broadly divided into following components：
Command status machine monitors：The state for referring to state machine is recompiled using Gray code so that between two states
Code distance it is constant be 1, be 1 when command status machine code distance occurs not for being inserted into additional dummy status among the part that cannot encode
When redirecting, generate abnormal signal；
Address accesses monitoring：The internal storage access of monitoring processor, when processor is attempted to access illegal memory address,
Generate abnormal signal；
Data Stream Processing monitors：Error detection point is inserted on data processing access, by using Hamming code, Berger to data
Code etc. error correcting and detectings mode reinforced, when data in processing procedure when the error occurs, can pass through error correcting and detecting code check number
According to correctness, when there is wrong data, generate abnormal signal；
Processor state monitoring and evaluation；On the one hand setting house dog logic carries out entirety to processor and decision logic
On the other hand monitoring collects three above part abnormal signal, assessment is made to the working condition of processor, and make corresponding
Processing.
Duplication redundancy hot-swap flow：
Referring to Fig. 4, two processor is reset on startup, but peripheral bus and program internal memory bus are all integrated into place
Device 0 is managed, and the operation of the value of processor 1 can be assigned 0.Because what processor 1 obtained is the do-nothing instruction of full 0, stop always
In idle state, and processor 0 understands the command content in sequence program memory.Until mistake occurs in processor 0, can send out at this time
Raw processor switching.Switch logic can change the mark for the processor being carrying out, and this information is passed to bus switch
Logic.Bus switch logic can cut off the data path of processor 0, transfer processor 1 to, while sending out and cutting to processor 1
Change interrupt requests.It is that cold start-up or processor switch that handoff request can recognize current reset with helper person.Processing
When device 1 receives handoff, the initial phase of program can be skipped, uses the data recovery process in shared data memory
The execution state of device 0 continues to execute, to realize hot-swap.
In the present invention, decision logic can be handled according to the different grades of abnormal suitable mode of selection.For instruction
State machine is abnormal, can be by achieving the purpose that reparation to modular circuit reset；For data flow anomaly, data can be passed through
The error correcting and detecting ability of itself is restored；It when unknown exception occurs, can be found by watchdog circuit, and by processing
Device carries out hot-swap processing.Table 1 is the comparison of decision logic error handle and the prior art of the present invention：
| Exception Type | Original decision logic | Novel decision logic |
| Command status machine redirects extremely | It can not directly find | It can directly find, reset state machine |
| Address access exception | It can not directly find | It can directly find, address of reruning |
| Data processing is abnormal | It can not directly find | It can directly find, error correction reparation |
| Instruct throat floater | Pass through watchdog reset processor | Task is hot-switched onto back-up processing device |
Processor system knot of the processor state monitoring of the present invention in conjunction with conventional processors state monitoring mechanism and reinforcing
Structure designs typical processor monitoring running state mechanism.
Processor instruction state machine is recompiled, legitimacy is redirected using XOR logic inspection state；
Increase the monitoring of processor memory access address, monitoring processor accesses the legitimacy of memory address；
Increase the monitoring of processor data error correcting and detecting in suitable position, checks the correctness of data handling procedure；
It designs whether house dog counters monitor processor is in task major cycle, prevents processor from entering the instruction of mistake
Stream.
Usually there are following instruction cycles for a typical processor referring to Fig. 5 a：
Acquisition instruction (FI)；
Decoding instruction (DEC)；
Obtain extended instruction word (EXT)；
Instruction execution (EXEC)；
Write-back result (WB)；
Idle (IDLE)；
Wherein extended instruction word and write-back result state may be skipped, so being inserted into dummy status design command status machine such as
Shown in Fig. 5 b.
The above monitoring result is submitted into processor state and assesses logic, carries out the judgement that processor executes state.State
The practice condition of form assessment processing device of score-sheet can be used by assessing logic, can be into if multiple mistake occurs in processor
The task of row processor switches.State evaluation logic can use the mode tissue of single mode, can also use the side of triplication redundancy
Formula carries out the reinforcing of high reliability.
For the storage organization of the present invention as shown in fig. 6, for 16 bit processors, the access of data storage is logical
It is often carried out by word and byte, the difference by access mode by data storage is needed at this time, using the separated form of high low byte
Tissue.Two processor is accessed by different ports.The mode for increasing check bit can be used to carry out Redundancy Design for memory,
Increase the reliability of storage.
Switch logic, which interrupts to generate with hot-swap, changes logic by receiving the court verdict of processor execution state to judge
Whether switching signal is generated.
For software designer, if not using hot-swapping function, it can be used according to normal house dog,
Intermediate additional error processing procedure is all transparent.If software designer wishes to retain certain data in switching,
It needs to place data into shared data register, and handles hot-swap and interrupt to complete corresponding handover operation.
The present invention proposes a kind of novel fine granularity, the duplication redundancy processor decision logic of high reliability and its switching side
Formula, compared with existing decision logic, more fully to the monitoring of processor state, it is easier to find and solve the problems, such as.System
System can monitor processor operating status in real time, and take suitable mode to handle processor when the error occurs in processor execution
It is abnormal.If mistake cannot be handled immediately, switch logic can will handle task under the premise of not interrupt handler execution state
It is transformed into additional processor core in the heart, is particularly suitable for the higher field of reliability requirement using this duplication redundancy processor
It closes.
Claims (9)
1. a kind of hot change-over method of duplication redundancy microprocessor, which is characterized in that include the following steps：
1) duplication redundancy processor decision logic is established：Respectively to command status machine, address access, Data Stream Processing and processor
State is monitored, and is evaluated processor state；
2) hot-swap based on duplication redundancy processor decision logic：Second processor receives do-nothing instruction, rests on idle state,
First processor sequence executes the command content in memory can occur processor until mistake occurs in first processor at this time
Switching, switch logic can change the mark for the processor being carrying out, and this information is passed to bus switch logic；Bus
Switch logic can cut off the data path of first processor, transfer second processor to, while sending out and cutting to second processor
Change interrupt requests；When second processor receives handoff request, initial phase is skipped, using in shared data memory
Data, restore the execution state of first processor and continue to execute instruction, to realize hot-swap.
2. a kind of hot change-over method of duplication redundancy microprocessor according to claim 1, which is characterized in that described instruction
The monitoring of state machine includes：The state of command status machine is recompiled using Gray code so that the code between two states
Away from it is constant be 1, for being inserted into additional dummy status among the part that cannot encode, when the jump that code distance occur not be 1 of command status machine
When turning, abnormal signal is generated, and repair by being resetted to command status electromechanics road.
3. a kind of hot change-over method of duplication redundancy microprocessor according to claim 1, which is characterized in that described address
Accessing monitoring includes：The internal storage access of monitoring processor generates abnormal when processor is attempted to access illegal memory address
Signal, and repaired by address of reruning.
4. a kind of hot change-over method of duplication redundancy microprocessor according to claim 1, which is characterized in that the data
Stream process monitors：Error detection point is inserted on data processing access, by being reinforced using error correcting and detecting mode to data,
When data in processing procedure when the error occurs, by error correcting and detecting code check data correctness, when there is wrong data,
Abnormal signal is generated, and is restored by the error correcting and detecting ability of data itself.
5. a kind of hot change-over method of duplication redundancy microprocessor according to claim 4, which is characterized in that the data
Data are reinforced using Hamming code or Berger code error correcting and detecting modes in stream process monitoring.
6. a kind of hot change-over method of duplication redundancy microprocessor according to claim 1, which is characterized in that the processing
Device status monitoring and evaluation include：House dog logic is set, whole monitoring is carried out to processor and decision logic, and collects and refer to
State machine, address access and three part abnormal signals of Data Stream Processing are enabled, assessment are made to the working condition of processor, and do
Go out corresponding repair process.
7. a kind of hot change-over method of duplication redundancy microprocessor according to claim 6, which is characterized in that the processing
Device state evaluation is carried out using the practice condition of the form assessment processing device of score-sheet if multiple mistake occurs in processor
The task of processor switches, and state evaluation logic uses the mode tissue of single mode, or is added using the mode of triplication redundancy
Gu.
8. a kind of hot change-over method of duplication redundancy microprocessor according to claim 1, which is characterized in that described first
Processor and second processor are reset on startup, and first processor connects peripheral bus and instruction memory bus, at second
The value operation for managing device is assigned 0, and second processor obtains the do-nothing instruction of full 0, rests on idle state, and first processor sequence is held
Command content in line storage.
9. a kind of hot change-over method of duplication redundancy microprocessor according to claim 8, which is characterized in that described first
Processor and second processor access memory by different ports, and memory carries out redundancy by the way of check bit.
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| US10078544B2 (en) * | 2015-12-19 | 2018-09-18 | Intel Corporation | Apparatus and method for an on-chip reliability controller |
| CN107423243B (en) * | 2017-04-18 | 2020-09-15 | 深圳市有芯半导体技术有限公司 | Method for preventing CPU from being hung up |
| CN109782578A (en) * | 2018-12-24 | 2019-05-21 | 中国船舶重工集团公司第七一0研究所 | A kind of high reliability deep-sea autonomous underwater vehicle control method |
| CN112506701B (en) * | 2020-12-02 | 2022-01-21 | 广东电网有限责任公司佛山供电局 | Multiprocessor chip error recovery method based on three-mode lockstep |
| CN113342613A (en) * | 2021-06-25 | 2021-09-03 | 深圳市商汤科技有限公司 | Data processing apparatus, data processing method, computer device, and storage medium |
| CN113671373A (en) * | 2021-07-27 | 2021-11-19 | 三门三友科技股份有限公司 | Electrolytic process monitoring system and method in electrolytic cell with self-checking function |
| CN115168079B (en) * | 2022-09-08 | 2022-12-02 | 深圳市恒运昌真空技术有限公司 | Dual-processor device and control method thereof |
| CN115525137A (en) * | 2022-11-23 | 2022-12-27 | 紫光同芯微电子有限公司 | Data coprocessing method and system, storage medium and electronic equipment |
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| CN101178674A (en) * | 2007-12-13 | 2008-05-14 | 北京理工大学 | Three modes redundant fault tolerant control system based on godson |
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