CN105630664A - Reverse debugging method and device as well as debugger - Google Patents
Reverse debugging method and device as well as debugger Download PDFInfo
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Abstract
Embodiments of the invention provide a reverse debugging method and device as well as a debugger. The method comprises the following steps: after a single-step instruction is sent to an agent module, receiving an event or command generation notification, wherein the single-step instruction is determined by a control module according to a debugging control command input by a user; judging whether the event or command generation notification aims at events or commands to obtain a first judging result; when the first judging result indicates that the event or command generation notification aims at commands, analyzing a user command to obtain a first command aiming at the event or command generation notification, and processing the first command; and when the first judging result indicates that the event or command generation notification aims at events, obtaining a completion event of the single-step instruction aiming at the event or command generation notification from the agent module, and processing the completion event. According to the embodiments of the invention, the reverse debugging under an asynchronous debugging mode is realized.
Description
Technical field
The present invention relates to debugging field, particularly relate to a kind of reversely adjustment method, device and debugger.
Background technology
The process of a debugging conjecture often needs the code replicate analysis suspected, breakpoint is just placed on most suitable position by general unlikely first time. Such as we will often find that important code have already passed by or before running to breakpoint some state of program incorrect, generally we can only exit debugging and restart new debugging and do again from the beginning, and debugging efficiency is relatively low.
Reversely debugging function if having, as long as we are without restarting the place that debugging simply allows called program reverse execution suspect to us in this case, after having investigated, we can also continue to forward and perform debugging. This will greatly improve debugging efficiency undoubtedly.
Standard gdb starts to support reversely to debug (reversedebug) new features from 7.0 versions, this New function allows user just can object code be debugged back and forth without restarting debugging, just as the part do not understood is reset by we using language repeater when studying English and analyzes.
Its ultimate principle is: each the order details that program is performed by debugger is recorded, and the operation of each instruction is recovered according to record when needing rollback, thus by program recovery to state at that time. Such as certain instruction the value of depositor reg1 has been added 1 so undo subtracted 1 exactly. The common debugging process that reverse debugging process is familiar with as us is the same, simply needs to use corresponding reversely debugging control order. It should be noted that only support that the operation of file or terminal then cannot be recovered by recovery routine by the operation of internal memory and depositor at present.
Standard gdb realizes this function under the framework of synchronous mode, in such a mode unless it is any debug command that can not receive and process user that called program is in halted state otherwise debugger.
Module is decomposed by gdb debugger subsystem debugger part according to function, and then refining function in each inside modules is each functional unit. Module Division is debugging control module gdb and debugging proxy module gdbserver two parts:
Debugging control module gdb:
Gdb major function is receive the debug command of user's input and destination end is carried out debugging control, and the debugging event that proxy module is returned resolves.
Debugging proxy module gdbserver:
Gdbserver major function is accept the gdb debug command sent, and actively returns debugging event to gdb; Gdbserver, based on synchronistic model, monitors the state event of gdb debug command and tracked task simultaneously.
Gdb-gdbserver synchronization framework basic procedure:
Then step A.gdb resolves the debug command of user's input allows program behave to the corresponding order of gdbserver transmission, then waits that gdbserver debugs reporting events. Synchronizing due to gdb to wait gdbserver reported event, therefore gdb cannot receive user's input in the process always.
Step B.gdbserver receives the debug command of gdb and has then performed corresponding debugging action or triggering event (receive signal or sever a little etc.) and report gdb.
If step C. called program generation event is reported by gdbserver, gdb could again receive user after receiving this event handling and input order, still can not receive user's input if not stopping event.
The recording flow process of reversely debugging under synchronous mode:
Step A. starts to record, and all debugging control orders that user is issued by gdb such as continue to run with order, and source code single step, return etc. is all converted to instruction single step.
Step B.gdbserver controls single step to be completed after program completes once command single step reporting events and to gdb, gdb, this instruction is carried out dis-assembling analysis and see which operation this instruction completes and in these operation notes to log chained list.
Step C. completes gdb just beginning director's part flow process after recording, sees currently whether sever a little or current pc has met the boundary condition of this operation, if words just stopping issue instruction single-step operation then report of user if not then continuing to walk single step. In synchronous mode, gdb need not return to event handling circulation go perception and obtain gdbserver report debugging event.
The structure of instruction recording frame is as shown in Figure 1. Inst1 in figure represents the recording frame of Article 1 instruction, internal memory and depositor have all been operated by this instruction, therefore have recorded this instruction details to internal memory and the write operation of depositor with mementry and regentry respectively at this frame, such as being modified the address of internal memory and value or be modified numbering and the value etc. of depositor, endentry represents that this records the end of frame. In like manner, inst2 represents that frame is recorded in Article 2 instruction, and internal memory and depositor are also had operation by it; And inst3 represents that frame is recorded in Article 3 instruction, depositor is only had operation to so there is no memenrty by this instruction; And internal memory or depositor are not had the instruction of write operation by those, such as Tapped Delay slot order, it is recorded frame and only has endentry; By that analogy, all instructions within the scope of recording are all recorded according to this form and are preserved with the doubly linked list that frame is node of recording of each instruction by debugger, use these data when instruction plays back.
Recording flow process under synchronous mode is as shown in Figure 2. Wherein, the arrow from step 203 to step 211 represents that gdb sends instruction single step to gdbserver when being in the state sending single step order so that gdbserver processes order transmission eventing step from order waiting step entrance and processes this instruction single step. Arrow from step 212 to step 204 represents that gdbserver is in process order when sending eventing step, will process the reporting events of this instruction single step to gdb.
The playback flow process of reversely debugging under synchronous mode:
Step A. user inputs reverse execution order (such as reverse execution, return, single step) gdb and depositor or internal memory is performed reverse operating from recording to read a upper instruction record information log chained list and resolve then notification agent module.
Step B. often performs a reverse operating gdb and is regarded as a debugging event generation, enters event handling flow process, if current pc has met this operational boundaries condition gdb, just stopping inverted running operating, and report of user.
Owing to the debugging of synchronous mode does not allow debugger to process user command when program is run, Consumer's Experience is poor, and therefore some debugger adopts asynchronous mode framework. The basic procedure of asynchronous framework:
Step A. controls module command proxy module and behaves by program, and then waiting agents module reports program debugging reporting events, and control module returns to event/order and waits that therefore flow process still can receive and process user command in this process.
Step B. proxy module receives notice control module after order completes corresponding debugging efforts, and currently event occurs.
Step C. control module learnt debugging event occur to proxy module query event then proxy module by reporting events give control module.
Step D. controls resume module event.
But without the realization that can carry out reversely debugging in asynchronous mode in current debugger.
Summary of the invention
The purpose of the embodiment of the present invention is to provide a kind of reversely adjustment method, device and debugger so that reversely debugging also is able to realize under asynchronous debugging pattern.
For solving above-mentioned technical problem, the embodiment of the present invention provides scheme as follows:
The embodiment of the present invention provides a kind of reversely adjustment method, controls module for one, including:
After sending a single-step instruction to a proxy module, receiving an event or order notifies, the debugging control order that described single-step instruction is inputted according to user by described control module is determined;
Judge that described event or order occur notice to be for event or order, obtain one first judged result;
When described first judged result be described event or order occur notice for order time, resolve described user command, it is thus achieved that described event or order occur notice for first order; And process described first order;
When described first judged result be described event or order occur notice for event time, from described proxy module obtain described event or order occur notice for described single-step instruction complete event; And complete event described in processing.
Preferably, described first order of described process includes:
Judge whether described first order is instruction single step, obtains one second judged result;
When described second judged result be described first order be instruction single step time, to described proxy module send described first order so that described proxy module can to described first order process;
When described second judged result be described first order be not instruction single step time, described first order is converted to instruction sheet step command, and sending described instruction sheet step command to described proxy module so that described instruction sheet step command can be processed by described proxy module.
Preferably, described obtain described event from described proxy module or order occur notice for the event that completes of described single-step instruction include:
To described proxy module inquire about described event or order occur notice for event;
Receive described proxy module response described single-step instruction complete event;
Complete event described in described process to include:
Obtain the running state of programs information that described single-step instruction is processed by described proxy module;
Recorded in a logical memory space by described running state of programs information, described logical memory space carries out instruction playback for described control module according to the described running state of programs information of described logical memory space record.
Preferably, described running state of programs information includes: for recording described proxy module and internally depositing into the internal memory operation record frame of capable operation according to described single-step instruction, for recording the end frame created when described proxy module completes described internal memory operation record frame and described register manipulation record frame according to the described single-step instruction register manipulation record frame to the operation that depositor carries out and described proxy module.
Preferably, described logical memory space includes chained list.
The embodiment of the present invention also provides for a kind of reversely debugging apparatus, controls module for one, including:
Receiver module, for, after sending a single-step instruction to a proxy module, receiving an event or order notifies, the debugging control order that described single-step instruction is inputted according to user by described control module is determined;
Judge module, is used for judging that described event or order occur notice to be for event or order, obtains one first judged result;
Resolve and processing module, for when described first judged result be described event or order occur notice for order time, resolve described user command, it is thus achieved that described event or order occur notice for first order; And process described first order;
Obtain and processing module, for when described first judged result be described event or order occur notice for event time, from described proxy module obtain described event or order occur notice for described single-step instruction complete event; And complete event described in processing.
Preferably, described parsing and processing module include:
Resolution unit, for when described first judged result be described event or order occur notice for order time, resolve described user command, it is thus achieved that described event or order occur notice for first order;
Judging unit, is used for judging whether described first order is instruction single step, obtains one second judged result;
Transmitting element, for when described second judged result be described first order be instruction single step time, to described proxy module send described first order so that described proxy module can to described first order process;
Conversion and transmitting element, for when described second judged result be described first order be not instruction single step time, described first order is converted to instruction sheet step command, and sending described instruction sheet step command to described proxy module so that described instruction sheet step command can be processed by described proxy module.
Preferably, described acquisition and processing module include:
Query unit, for described proxy module inquire about described event or order occur notice for event;
Receive unit, for receive described proxy module response described single-step instruction complete event;
Acquiring unit, for obtaining the running state of programs information that described single-step instruction is processed by described proxy module;
Record unit, for recorded in a logical memory space by described running state of programs information, described logical memory space carries out instruction playback for described control module according to the described running state of programs information of described logical memory space record.
Preferably, described running state of programs information includes: for recording described proxy module and internally depositing into the internal memory operation record frame of capable operation according to described single-step instruction, for recording the end frame created when described proxy module completes described internal memory operation record frame and described register manipulation record frame according to the described single-step instruction register manipulation record frame to the operation that depositor carries out and described proxy module.
Preferably, described logical memory space includes chained list.
The embodiment of the present invention also provides for a kind of debugger including above-described reverse debugging apparatus.
From the above it can be seen that the embodiment of the present invention at least has the advantages that
Notify by receiving an event or order, it is judged that described event or order occur notice to be for event or order, do different disposal according to the difference of judged result, it is achieved thereby that the reverse debugging under asynchronous debugging pattern.
Accompanying drawing explanation
Fig. 1 represents that the structure chart of frame is recorded in instruction;
Fig. 2 represents the recording flow chart under synchronous mode;
Fig. 3 represents the flow chart of steps of a kind of reverse adjustment method that the embodiment of the present invention provides;
Fig. 4 represents the recording flow chart under asynchronous mode;
Fig. 5 represents replayed section flow chart;
Fig. 6 represents the structured flowchart of a kind of reverse debugging apparatus that the embodiment of the present invention provides.
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawings and the specific embodiments the embodiment of the present invention is described in detail.
Fig. 3 represents the flow chart of steps of a kind of reverse adjustment method that the embodiment of the present invention provides, and with reference to Fig. 3, inventive embodiments provides a kind of reversely adjustment method, comprises the steps:
Step 301, after sending a single-step instruction to a proxy module, receives an event or order notifies, the debugging control order that described single-step instruction is inputted according to user by described control module is determined;
Step 302, it is judged that described event or order occur notice to be for event or order, obtain one first judged result;
Step 303, when described first judged result be described event or order occur notice for order time, resolve described user command, it is thus achieved that described event or order occur notice for first order; And process described first order;
Step 304, when described first judged result be described event or order occur notice for event time, from described proxy module obtain described event or order occur notice for described single-step instruction complete event; And complete event described in processing.
Described method is for a control module.
Visible, by the way, notify by receiving an event or order, it is judged that described event or order occur notice to be for event or order, do different disposal according to the difference of judged result, it is achieved thereby that the reverse debugging under asynchronous debugging pattern.
Wherein, described logical memory space is such as: include chained list.
In the embodiment of the present invention, described first order of described process may include that
Judge whether described first order is instruction single step, obtains one second judged result;
When described second judged result be described first order be instruction single step time, to described proxy module send described first order so that described proxy module can to described first order process;
When described second judged result be described first order be not instruction single step time, described first order is converted to instruction sheet step command, and sending described instruction sheet step command to described proxy module so that described instruction sheet step command can be processed by described proxy module.
In the embodiment of the present invention, described obtain described event from described proxy module or order occur notice for the event that completes of described single-step instruction may include that
To described proxy module inquire about described event or order occur notice for event;
Receive described proxy module response described single-step instruction complete event;
Complete event described in described process to include:
Obtain the running state of programs information that described single-step instruction is processed by described proxy module;
Recorded in a logical memory space by described running state of programs information, described logical memory space carries out instruction playback for described control module according to the described running state of programs information of described logical memory space record.
Wherein, described running state of programs information comprises the steps that for recording described proxy module and internally depositing into the internal memory operation record frame of capable operation according to described single-step instruction, for recording the end frame created when described proxy module completes described internal memory operation record frame and described register manipulation record frame according to the described single-step instruction register manipulation record frame to the operation that depositor carries out and described proxy module.
This better embodiment provides the reverse adjustment method under a kind of asynchronous debugging pattern. What this better embodiment related to debugger realizes technology, the method that especially debugger realizes reversely debugging in asynchronous mode. Specifically, it is simply that a kind of means are provided, allow debugger in asynchronous mode the instruction of called program can be recorded then reverse execution. If to realize reverse debugging in asynchronous mode, then need reverse debugging module and asynchronous debugging framework are adjusted correspondingly and integration.
The purpose of this better embodiment is in that, integrates the reverse debugging module of debugger and asynchronous framework, it is provided that a kind of reversely adjustment method.
For reaching this purpose, this better embodiment relates to following several respects content.
(1) debugging control is run
Reversely the premise of debugging is exactly that debugger each instruction that program is performed is recorded, and under recording mode, any one operation control command of user is all finally complete with the form of instruction single step. With reference to Fig. 3, its flow process is as follows:
1. step A. user inputs debugging control order, control module and resolve this order, if continue to run with, the operation such as source code single step or return is then all converted to instruction sheet step command notification agent module and completes once command single-step operation, then control module and enter event and wait and process circulation.
2. step B. proxy module completes notice after a single step and controls module event occurs.
3. step C. controls module and knows and inquire about after event occurs and obtain event, before process event, this instruction is recorded.
4. step D. controls this single step event of resume module, if having breakpoint or reaching the boundary condition of this operation, stops issuing single step order report of user, then continues to walk single step without reaching above-mentioned debugging.
(2) instruction is recorded
Owing to reversely file and terminal (as screen shows) cannot be carried out reverse operating by debugging, therefore the only record operation to internal memory and depositor is recorded in instruction. The function that instruction is recorded is completed by controlling module, and with reference to Fig. 3, basic procedure is as follows:
1. step A. if Article 1 instruction single step then recovery routine run flow process in record, if not just event wait flow process in record. With under synchronous mode the difference is that, synchronous mode can wait walking single step recording continuously in the circulation of flow process and must often recording an instruction under asynchronous mode and be returned to event handling circulation and otherwise control module and will be unable to receive single step and complete event in event.
2. instruction is analyzed by step B. entrance opcode module.
If 3. this instruction of step C. has the operation to internal memory, set up its operation to internal memory of internal memory operation record frame recording; If this instruction has the operation to depositor, set up its operation to depositor of register manipulation record frame recording; An end frame is created after completing the record to this instruction. These record frames are all added in the log chained list controlling module.
(3) playback
Instruction plays back, and controls module and is then played back one by one by the record reading each instruction from log chained list. It should be noted that if forward performs and execution scope then also will adopt playback mode to perform within the range of instructions recorded. With reference to Fig. 4, basic procedure is as follows:
1. step A: check log chained list, if the former frame of the current chain list index of reverse execution is sky then represents that the instruction record not had forward directly exits playback flow process report of user; In like manner if it is that empty then expression does not have record backward directly exit playback flow process and report that forward performs a later frame of current chain list index.
2. step B: obtain a record frame from log chained list, if internal memory record frame then recovers internal memory, if depositor record frame then recovers depositor.
3. step C: if reverse execution and when frame be this instruction playback first end frame represent this end frame be present instruction a part from log chained list read former frame continue step B, represent if not first end frame be a upper instruction end frame illustrate be complete the playback to present instruction.
4. step D: if forward performs and when frame is that end frame just terminates this instruction playback, otherwise goes to read a later frame from log chained list and continues step B.
5. step E: terminate playback one SIGTRAP event of labelling of an instruction, then this event is processed, in event handling flow process, control module if it find that current pc exists breakpoint or reaches the boundary condition of this operation and just stop playback and report of user.
In Fig. 4, when the arrow extended to the left from step 421 represents that proxy module is in notification event step, sending, to controlling module, the notification event that instruction single step has processed, making control module carry out about what perceive is the judgement of event or order. Arrow from step 402 to step 422 represents that control module sends inquiry request to proxy module when being in event query step, the event that notification event that inquiry proxy module sent just now is targeted. Arrow from step 413 to step 424 represents that control module sends instruction single step to proxy module when being in transmission commands steps so that proxy module is from waiting that commands steps entrance processes coomand mode and processes this instruction single step.
<specific embodiment>
Below this asynchronous mode debugger support is reversely debugged by the local_zdb User space order line debugger researched and developed for academy Chengdu, ZTE Corporation center institute and be briefly described.
(1) instruction is recorded
Performing an instruction control module just the operation about this instruction to be recorded, these information can be fully described by the effect that an instruction performs, including two classes: the operation information to depositor and the operation information to internal memory every time.
If one machine instruction it have modified internal memory, then just record the address and value that are modified internal memory; If it have modified depositor, just record sequence number and the value of depositor. These amendment records are represented by structrecord_entry and store:
Multiple record_entry connect into record_list chained list by prev and next. Article one, machine instruction is likely to both revise internal memory and also revises depositor, and therefore the implementation effect of an instruction is made up of the multiple entry in record_list. There are three kinds of entry, represent the entry of depositor, the entry that the entry of expression memory and flags instruction terminate. As its name suggests, registerentry is used for recording the amendment situation of depositor; Memoryentry is used for recording the amendment of internal memory; Endentry represents order fulfillment.
Instruction record frame structure is represented by Fig. 1.
Two overall record_full_list and record_full_first that log linked list head and chained list current pointer are defined by this structure respectively represent.
Instruction is recorded and playback is all completed by record_target layer, under record pattern, it is positioned at the top layer of target stack, run all control to debugging routine of control flow first call it and complete wherein to record or playback, then called operation control function corresponding to the asynchronous layer of async_target by it and program done actual operation, below between two-layer target important run between control function call corresponding relation:
record_full_resume->remote_async_resume
record_wait->remote_async_wait
Record_full_resume is that the target of record_target layer is resumed operation function, and in recording process because after he has performed, pc has pulled up the recording of next instruction place therefore Article 1 pointer and must here complete:
Hereafter instruction is recorded and is all completed in event wait function record_full_wait.
(2) instruction playback
Instruction playback is also complete in record_full_wait function:
(3) control is run
All of forward and reverse resuming operation, single step, the operations such as return all can call the proceed function controlling module, resume function is called and final by the record_full_resume of record layer by it, the remote_async_resume of record_full_wait and asynchronous layer completes to record and playback, and corresponding operation controls also to complete in this flow process.
Resume function call remote_async_resume function during recording, is judged whether be currently recording state by him, if words all run order all referring to making single step to what proxy module issued:
In proceed function, enter wait_for_inferior () during instruction playback, control module and will not enter this function under non-recording mode. The circulation each time of this function is all called record_full_wait and is completed instruction playback and then call handle_inferior_event function and process event and control to run:
Fig. 6 represents the structured flowchart of a kind of reverse debugging apparatus that the embodiment of the present invention provides, and with reference to Fig. 6, the embodiment of the present invention also provides for a kind of reversely debugging apparatus, including:
Receiver module 601, for, after sending a single-step instruction to a proxy module, receiving an event or order notifies, the debugging control order that described single-step instruction is inputted according to user by described control module is determined;
Judge module 602, is used for judging that described event or order occur notice to be for event or order, obtains one first judged result;
Resolve and processing module 603, for when described first judged result be described event or order occur notice for order time, resolve described user command, it is thus achieved that described event or order occur notice for first order; And process described first order;
Obtain and processing module 604, for when described first judged result be described event or order occur notice for event time, from described proxy module obtain described event or order occur notice for described single-step instruction complete event; And complete event described in processing.
Described device is for a control module.
Visible, by the way, notify by receiving an event or order, it is judged that described event or order occur notice to be for event or order, do different disposal according to the difference of judged result, it is achieved thereby that the reverse debugging under asynchronous debugging pattern.
Wherein, described parsing and processing module 603 comprise the steps that
Resolution unit, for when described first judged result be described event or order occur notice for order time, resolve described user command, it is thus achieved that described event or order occur notice for first order;
Judging unit, is used for judging whether described first order is instruction single step, obtains one second judged result;
Transmitting element, for when described second judged result be described first order be instruction single step time, to described proxy module send described first order so that described proxy module can to described first order process;
Conversion and transmitting element, for when described second judged result be described first order be not instruction single step time, described first order is converted to instruction sheet step command, and sending described instruction sheet step command to described proxy module so that described instruction sheet step command can be processed by described proxy module.
Described acquisition and processing module 604 comprise the steps that
Query unit, for described proxy module inquire about described event or order occur notice for event;
Receive unit, for receive described proxy module response described single-step instruction complete event;
Acquiring unit, for obtaining the running state of programs information that described single-step instruction is processed by described proxy module;
Record unit, for recorded in a logical memory space by described running state of programs information, described logical memory space carries out instruction playback for described control module according to the described running state of programs information of described logical memory space record.
Described running state of programs information comprises the steps that for recording described proxy module and internally depositing into the internal memory operation record frame of capable operation according to described single-step instruction, for recording the end frame created when described proxy module completes described internal memory operation record frame and described register manipulation record frame according to the described single-step instruction register manipulation record frame to the operation that depositor carries out and described proxy module.
Described logical memory space can include chained list.
The embodiment of the present invention also provides for a kind of debugger, and described debugger includes above-described reverse debugging apparatus.
The above is only the embodiment of the embodiment of the present invention; should be understood that; for those skilled in the art; under the premise without departing from embodiment of the present invention principle; can also making some improvements and modifications, these improvements and modifications also should be regarded as the protection domain of the embodiment of the present invention.
Claims (11)
1. a reverse adjustment method, controls module for one, it is characterised in that including:
After sending a single-step instruction to a proxy module, receiving an event or order notifies, the debugging control order that described single-step instruction is inputted according to user by described control module is determined;
Judge that described event or order occur notice to be for event or order, obtain one first judged result;
When described first judged result be described event or order occur notice for order time, resolve described user command, it is thus achieved that described event or order occur notice for first order; And process described first order;
When described first judged result be described event or order occur notice for event time, from described proxy module obtain described event or order occur notice for described single-step instruction complete event; And complete event described in processing.
2. reverse adjustment method according to claim 1, it is characterised in that described first order of described process includes:
Judge whether described first order is instruction single step, obtains one second judged result;
When described second judged result be described first order be instruction single step time, to described proxy module send described first order so that described proxy module can to described first order process;
When described second judged result be described first order be not instruction single step time, described first order is converted to instruction sheet step command, and sending described instruction sheet step command to described proxy module so that described instruction sheet step command can be processed by described proxy module.
3. reverse adjustment method according to claim 1, it is characterised in that described obtain described event from described proxy module or order occur notice for the event that completes of described single-step instruction include:
To described proxy module inquire about described event or order occur notice for event;
Receive described proxy module response described single-step instruction complete event;
Complete event described in described process to include:
Obtain the running state of programs information that described single-step instruction is processed by described proxy module;
Recorded in a logical memory space by described running state of programs information, described logical memory space carries out instruction playback for described control module according to the described running state of programs information of described logical memory space record.
4. reverse adjustment method according to claim 3, it is characterized in that, described running state of programs information includes: for recording described proxy module and internally depositing into the internal memory operation record frame of capable operation according to described single-step instruction, for recording the end frame created when described proxy module completes described internal memory operation record frame and described register manipulation record frame according to the described single-step instruction register manipulation record frame to the operation that depositor carries out and described proxy module.
5. reverse adjustment method according to claim 1, it is characterised in that described logical memory space includes chained list.
6. a reverse debugging apparatus, controls module for one, it is characterised in that including:
Receiver module, for, after sending a single-step instruction to a proxy module, receiving an event or order notifies, the debugging control order that described single-step instruction is inputted according to user by described control module is determined;
Judge module, is used for judging that described event or order occur notice to be for event or order, obtains one first judged result;
Resolve and processing module, for when described first judged result be described event or order occur notice for order time, resolve described user command, it is thus achieved that described event or order occur notice for first order; And process described first order;
Obtain and processing module, for when described first judged result be described event or order occur notice for event time, from described proxy module obtain described event or order occur notice for described single-step instruction complete event; And complete event described in processing.
7. reverse debugging apparatus according to claim 6, it is characterised in that described parsing and processing module include:
Resolution unit, for when described first judged result be described event or order occur notice for order time, resolve described user command, it is thus achieved that described event or order occur notice for first order;
Judging unit, is used for judging whether described first order is instruction single step, obtains one second judged result;
Transmitting element, for when described second judged result be described first order be instruction single step time, to described proxy module send described first order so that described proxy module can to described first order process;
Conversion and transmitting element, for when described second judged result be described first order be not instruction single step time, described first order is converted to instruction sheet step command, and sending described instruction sheet step command to described proxy module so that described instruction sheet step command can be processed by described proxy module.
8. reverse debugging apparatus according to claim 6, it is characterised in that described acquisition and processing module include:
Query unit, for described proxy module inquire about described event or order occur notice for event;
Receive unit, for receive described proxy module response described single-step instruction complete event;
Acquiring unit, for obtaining the running state of programs information that described single-step instruction is processed by described proxy module;
Record unit, for recorded in a logical memory space by described running state of programs information, described logical memory space carries out instruction playback for described control module according to the described running state of programs information of described logical memory space record.
9. reverse debugging apparatus according to claim 8, it is characterized in that, described running state of programs information includes: for recording described proxy module and internally depositing into the internal memory operation record frame of capable operation according to described single-step instruction, for recording the end frame created when described proxy module completes described internal memory operation record frame and described register manipulation record frame according to the described single-step instruction register manipulation record frame to the operation that depositor carries out and described proxy module.
10. reverse debugging apparatus according to claim 6, it is characterised in that described logical memory space includes chained list.
11. a debugger, it is characterised in that include the reverse debugging apparatus as according to any one of claim 6 to 10.
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| CN112416790B (en) * | 2020-11-30 | 2023-04-14 | 中国航空工业集团公司西安航空计算技术研究所 | Embedded software offline replay debugging method and device |
| CN113179227B (en) * | 2021-04-26 | 2023-05-19 | 哈尔滨铁路科研所科技有限公司 | AT instruction control method based on queue |
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| WO2015184908A1 (en) | 2015-12-10 |
| CN105630664B (en) | 2020-03-13 |
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