CN105630120A - Processor hardware configuration word loading method and device - Google Patents
Processor hardware configuration word loading method and device Download PDFInfo
- Publication number
- CN105630120A CN105630120A CN201410608256.0A CN201410608256A CN105630120A CN 105630120 A CN105630120 A CN 105630120A CN 201410608256 A CN201410608256 A CN 201410608256A CN 105630120 A CN105630120 A CN 105630120A
- Authority
- CN
- China
- Prior art keywords
- driver
- processor
- data bit
- hardware configuration
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Logic Circuits (AREA)
Abstract
The application discloses a processor hardware configuration word loading device. The processor hardware configuration word loading device comprises a second-category data bit output module and a third-category data bit output module. The second-category data bit output module comprises m branches, each branch comprises a resistor and a driver, an input end of each driver is pulled up to a power source through a corresponding resistor, and an output end of each driver outputs corresponding second-category data bits. The third-category data bit output module comprises at least one resistor, at least one NOT gate, at least one switch and n drivers respectively corresponding to n third-category data bits, an output end of each driver outputs corresponding third-category data bits, and an input end of each driver achieves connection through a corresponding resistor, a corresponding NOT gate and a corresponding switch; combination of high and low levels under corresponding operating modes is achieved through the resistors, the NOT gates and the switches, and combination switching of high and low levels under different operating modes is achieved through on and off of the switches; an enabling end of each driver is connected with a reset signal of a processor.
Description
Technical field
The application relates to digital circuit technique field, particularly relates to method and the device of a kind of loading processing device hardware configuration word.
Background technology
Along with the development of electron trade, the scene of processor application is more and more extensive. General processor is required for when electrification reset offer hardware configuration word, and processor determines the hardware resource of how initialization processor according to the hardware configuration word obtained when resetting, as processor work clock, data-interface pattern, some pin definition etc.
Processor obtains hardware configuration word, i.e. processor data on readout data bus when reset state when being in reset state, and the data according to obtaining determine its mode of operation. If changing the mode of operation of processor, then must reset system, the data that change processor obtains when resetting simultaneously. Existing hardware designs determines processor data value in reset time data bus typically via drop-down on resistance. When mode of operation changed by processor, it is necessary to reconfigure pull down resistor. Although configuration resistance is changed less, but owing to relating to hardware modifications, can have a strong impact on work efficiency, it is also possible to cause the operation of series of complex simultaneously.
Fix a certain start-up mode of processor by resistance and will affect the use scene of processor. In actual applications, multiple-working mode is a relatively common demand, and changes resistance by hardware mode and realize the method for change mode of operation by impact production and maintenance efficiency.
In prior art, it is also possible to by flash memory (flash) upper storage hardware configuration word, by the address selecting flash drop-down on resistance and read-write after powering on, making the data being stored in flash export on data/address bus. When needing to update processor operating mode, by the data of instruction modification flash internal hardware configuration words, resetting processor again after revise, make processor reacquisition hardware configuration word. As, in a system application, processor needs to support Three models: 16 bit patterns, 8 bit patterns and chip test mode. When system is in normal operation, processor is in 16 bit patterns, and when starting under 16 bit patterns (board initial power-on, under 16 bit patterns, flash is without code, or flash code update is made mistakes), it is necessary to operate in the flash code under 8 bit patterns programming 16 bit pattern again. 8 bit patterns can as debugging mode, and now the flash under 8 bit patterns has only to the startup code that storage is most basic, and code simply need not update, and nonexistent code updates to make mistakes and causes the problem that system cannot start. Without this pattern, then under 16 bit patterns, the programming of flash needs to lean on emulator. Meanwhile, in order to better detect system hardware problem, processor also needs to be operated in chip test mode.
The mode being obtained hardware configuration word by flash there is also some shortcomings. Owing to hardware configuration word is exported by flash, flash is previously required to programming in advance in welding and starts configuration words. Processor must assure that when gathering the data of data wire the flash data exported are stable correct, simultaneously need to do drop-down process on appropriate address line, to ensure that flash output is the data of hardware configuration word. Owing to hardware configuration word is to be modified by processor, then must assure that processor can not be made mistakes when changing configuration words, being otherwise easily caused processor cannot start. During change start-up mode, it is necessary to processor is in normal operating conditions, now processor just can send the order of change hardware configuration word. Reset after having changed system again, and processor reacquires hardware configuration word. The process CIMS of whole hardware configuration word change is complicated, and spended time is long, in amendment process can not power-off, be in this way not suitable for producing in enormous quantities and maintenance period use. The method needs software to participate in simultaneously, can introduce uncertain factor, the stability of influential system.
Summary of the invention
This application provides the device of a kind of loading processing device hardware configuration word, in all hardware configuration words that need to load, be often low level data bit as primary sources position, be often the data bit of high level as secondary sources position, it is individual that secondary sources position has m; Need the data bit of height change as the 3rd class data bit, total n of the 3rd class data bit; This device includes: secondary sources position output module and the 3rd class data bit output module;
Described secondary sources position output module includes m branch road, corresponding with each secondary sources position respectively; In described m branch road, i-th branch road includes: resistance Ri and driver DRi; The input of driver DRi is pulled upward to the secondary sources position of the outfan output correspondence of power supply VCC, driver DRi by resistance Ri;
3rd class data bit output module includes: at least one resistance, at least one not gate, at least one switch and n the driver corresponding respectively with n the 3rd class data bit, 3rd class data bit of the outfan output correspondence of driver, the input of driver realizes connecting by resistance, not gate and switch, realized the low and high level combination under corresponding mode of operation by resistance, not gate and switch, the closed and disconnected through switching realizes the switching of the low and high level combination under different working modes;
The Enable Pin of each driver described connects the reset signal of processor.
It is preferred that the span of the resistance value of described resistance is 1000 ohm to 1000000 ohm.
It is preferred that described resistance has the resistance value of 4700 ohm or 10000 ohm.
It is preferred that described switch adopts jumper or toggle switch to realize.
Negate the circuit of function realize it is preferred that described not gate adopts independent logical device or use to have signal.
It is preferred that data bit corresponding to described processor hardware configuration words is 16,8,32 or 64.
It is preferred that described primary sources position is by the pull down resistor output within processor.
The embodiment of the present application additionally provides a kind of method of loading processing device hardware configuration word, and the method is realized by device as previously mentioned, and the method includes:
Before processor reset, the switch state for Guan Bi or disconnection is set according to required processor operating mode;
When processor reset, reset signal output low level, it is low level that driver enables, and the now output of driver enables as opening, the data bit of the hardware configuration word that driver output is corresponding;
Processor reset time obtain hardware configuration word, complete reset after, reset signal output high level, driver enable for height, now driver output enable close, the output of driver becomes high-impedance state.
As can be seen from the above technical solutions, the various configurations pattern realizing processor hardware configuration words by including the peripheral circuit of resistance, not gate, switch and driver device loads, it is not necessary to software is assisted, and is entirely through hardware and realizes. System stability is reliable, can effectively reduce system start-up time, is conducive to producing in enormous quantities and safeguarding, can effectively improve efficiency.
Accompanying drawing explanation
The device circuit schematic diagram of the loading processing device hardware configuration word that Fig. 1 provides for the embodiment of the present application;
Fig. 2 obtains the schematic flow sheet of hardware configuration word for the processor that the embodiment of the present application provides;
Detailed description of the invention
The method of the loading processing device hardware configuration word that the application provides is a kind of method by switching and peripheral circuit realizes processor hardware configuration words loading various configurations pattern, described method uses following device in circuit: resistance, not gate, switch and driver, realizes the different hardware configuration word of processor by the Guan Bi switched or disconnection and loads. In order to simplify design, it is possible to processor configuration words is analyzed, processor built-in function is utilized to reduce upper pull down resistor. To distinguishing data bit, the device of signal inversion can be made to realize by not gate etc.; By the hardware configuration word of analysis processor, finding out the rule of hardware configuration word corresponding to different mode of operations, for being often low level data bit, it is possible to use the weak pull-down resistance within processor, outside does not need resistive pull-downs; For being often the data bit of high level, it is possible to driver input end corresponding for data bit is pulled upward to VCC by resistance; For the different data bit of the state under different mode, it is possible to analysis of law, the devices such as resistance, switch and not gate are used to realize the combination of corresponding low and high level.
The device of a kind of loading processing device hardware configuration word that the application provides, in all hardware configuration words that need to load, be often low level data bit as primary sources position, be often the data bit of high level as secondary sources position, it is individual that secondary sources position has m; Need the data bit of height change as the 3rd class data bit, total n of the 3rd class data bit; This device includes: secondary sources position output module and the 3rd class data bit output module;
Described secondary sources position output module includes m branch road, corresponding with each secondary sources position respectively; In described m branch road, i-th branch road includes: resistance Ri and driver DRi; The input of driver DRi is pulled upward to the secondary sources position of the outfan output correspondence of power supply VCC, driver DRi by resistance Ri;
3rd class data bit output module includes: at least one resistance, at least one not gate, at least one switch and n the driver corresponding respectively with n the 3rd class data bit, 3rd class data bit of the outfan output correspondence of driver, the input of driver realizes connecting by resistance, not gate and switch, realized the low and high level combination under corresponding mode of operation by resistance, not gate and switch, the closed and disconnected through switching realizes the switching of the low and high level combination under different working modes;
The Enable Pin of each driver described connects the reset signal of processor.
The method of the loading processing device hardware configuration word realized by said apparatus that the application provides, before processor reset, arranges the switch state for Guan Bi or disconnection according to required processor operating mode;
When processor reset, reset signal output low level, it is low level that driver enables, and the now output of driver enables as opening, the data bit of the hardware configuration word that driver output is corresponding;
Processor reset time obtain hardware configuration word, complete reset after, reset signal output high level, driver enable for height, now driver output enable close, the output of driver becomes high-impedance state.
For making the know-why of technical scheme, feature and technique effect clearly, below in conjunction with specific embodiment, technical scheme is described in detail.
The hardware configuration word that the Three models of a kind of processor as listed in Table 1 is corresponding. By analysis, D0, D2, D3, D6, D8, D11, D13, D14, D15 are often low level, and D1, D7, D9 and D10 are often high level, and D4, D5 and D12 need to make corresponding change according to mode of operation.
Table 1
In this example, D0, D2, D3, D6, D8, D11, D13, D14, D15 are often low level data bit, it is possible to directly using the weak pull-down within processor, circuit need not do special process.
The device circuit schematic diagram of the loading processing device hardware configuration word that the embodiment of the present application provides is as shown in Figure 1, secondary sources position output module 101 includes four branch roads, respectively corresponding D1, D7, D9 and D10 these four are often the data bit of high level, in circuit respectively with outfan 1B, the 2B of driver, 3B and 4B is connected, at input 1A, 2A, 3A and the 4A of driver respectively through resistance R1, R2, R3 and R4 are pulled upward to VCC.
D4, D5 and D12 level state need in different modes to make change, during 16 bit pattern, D4, D5 and D12 need be configured to " 100 " state, during 8 bit pattern, D4, D5 and D12 need be configured to " 010 " state, D4 and D5 state is just contrary. 3rd class data bit output module 102 is for outputs data bits D4, D5 and D12, including resistance R5 and R6, switchs S1 and S2, NAND gate V1 and V2 and three drivers.
Driver input end 5A corresponding to D4 data bit uses resistance R5 to be pulled upward to VCC, re-use R5 after the driver input end 6A connection not gate V1 that D5 data bit is corresponding and be pulled upward to VCC, the effect of not gate V1 is so that driver 5A and 6A state are just contrary, the centre that R5 and V1 connects accesses switch S1 to earth level GND again, the effect of switch S1 is so that the state of 5A and 6A can change, when S1 disconnects, the state of A5 and A6 is " 10 ", when S1 closes, the state of A5 and A6 is " 01 ", the configuration variation of D4 and D5 is thus achieved by the disconnection of S1 and Guan Bi, when chip test mode, the state of D4 and D5 is not concerned with, D12 becomes high level from low level, it is pulled upward to VCC again through R6 resistance after the 7A input of driver is connected not gate V2, the centre that R6 and V2 connects accesses switch S2 to GND again, when so making S2 disconnect, the state of A12 is low level, and when S2 closes, the state of A12 is high level, so can enter chip test mode.
Circuit concrete form in Fig. 1 is merely illustrative, not in order to limit the application scheme. Those skilled in the art can enlighten according to Fig. 1 technology provided, and designs the loading of the various hardware configuration word of circuit realiration of entirely different form based on present techniques thought.
Can be seen that according to above-mentioned example, when the data bit that the outfan of driver connects needs high level, then corresponding input is pulled upward to VCC by resistance, when the data bit that the outfan of driver connects needs high level or low level change, then corresponding input is realized by resistance, not gate and switch combination the configuration variation of corresponding low and high level.
The effect of the output Enable Pin (EN) of driver is: when EN is low level, and driver output enable is opened, and when EN is high level, driver output enables closes. The EN of driver is connected by circuit used in this application with processor reset signals (HRESET), the HRESET output low level when processor reset, processor obtains hardware configuration word, and EN is low level, driver enables and opens, and outfan can export signal; When processor reset completes, HRESET signal becomes high level, and EN is high level, and driver enables closes, and outfan is high-impedance state, and now driver is without influence on processor data bus.
Processor output reset signal HRESET, HRESET when resetting represent that processor resets when being low level, and after processor reset completes, HRESET becomes high level.
Switch S1 and S2 can realize the change of processor hardware configuration words by closed and disconnected, the mode of wire jumper can be used to realize, it is possible to use toggle switch realizes on circuit realiration. The closed and disconnected of switch must be provided with before processor reset.
The resistance value range of choice can from 1000 ohm to 1000000 ohm, it is possible to select 4700 ohm, or 10000 ohm etc.
The effect of not gate V1 and V2 is to realize anti-phase to logic 1 or logic 1 to logical zero of logical zero, and independent logic chip can be used on circuit realiration to realize, it is possible to use has signal and negates the circuit of function and realize.
The embodiment of the present application provide processor obtain hardware configuration word flow process as in figure 2 it is shown,
When processor needs to be operated in 16 bit pattern, disconnecting S1, disconnect S2, resetting processor, processor gathers the hardware configuration word of data/address bus;
When processor needs to be operated in 8 bit pattern, closing S1, disconnect S2, resetting processor, processor gathers the hardware configuration word of data/address bus;
When processor needs to be operated in chip test mode, the state of Guan Bi S2, S1 is not concerned with. Resetting processor, processor gathers the hardware configuration word of data/address bus.
The data bit that the processor hardware configuration words mentioned in above example is corresponding is D0-D15 totally 16, but this method is not limited to 16, can also be 32 hardware configuration words of 8 hardware configuration words of D0-D7 or D0-D31, it is also possible to be the situation such as hardware configuration word of more such as 64.
The different configuration mode loading methods of the processor hardware configuration words mentioned in above example can realize the switching of 3 kinds of processor operating modes, but the application method is not limited to the 3 kinds of patterns being previously mentioned in above-described embodiment, may also be used for configuring other mode of operation or interface rate state etc. to processor, such as: the PLL parameter of processor, the work dominant frequency of processor, the DDR mode of operation of processor, DDR speed, bus clock selects, start flash type, the speed grade of USB interface master slave mode and support, Ethernet, the 1X of SRIO high-speed interface, 2X, 4X pattern etc. mode hardware configuration words as required makes analysis, find out identical and different data bit, data bit for change uses switch, resistance, the device such as not gate and driver is combined into the combination of multiple hardwares configuration words, can make to realize in aforementioned manners the loading of different hardware configuration words.
The foregoing is only the preferred embodiment of the application; not in order to limit the protection domain of the application; within all spirit in technical scheme and principle, any amendment of making, equivalent replacements, improvement etc., should be included within the scope that the application protects.
Claims (8)
1. the device of a loading processing device hardware configuration word, it is characterized in that, in all hardware configuration words that need to load, be often that low level data bit is as primary sources position, be often the data bit of high level as secondary sources position, total m is individual in secondary sources position; Need the data bit of height change as the 3rd class data bit, total n of the 3rd class data bit; This device includes: secondary sources position output module and the 3rd class data bit output module;
Described secondary sources position output module includes m branch road, corresponding with each secondary sources position respectively; In described m branch road, i-th branch road includes: resistance Ri and driver DRi; The input of driver DRi is pulled upward to the secondary sources position of the outfan output correspondence of power supply VCC, driver DRi by resistance Ri;
3rd class data bit output module includes: at least one resistance, at least one not gate, at least one switch and n the driver corresponding respectively with n the 3rd class data bit, 3rd class data bit of the outfan output correspondence of driver, the input of driver realizes connecting by resistance, not gate and switch, realized the low and high level combination under corresponding mode of operation by resistance, not gate and switch, the closed and disconnected through switching realizes the switching of the low and high level combination under different working modes;
The Enable Pin of each driver described connects the reset signal of processor.
2. device according to claim 1, it is characterised in that the span of the resistance value of described resistance is 1000 ohm to 1000000 ohm.
3. device according to claim 2, it is characterised in that described resistance has the resistance value of 4700 ohm or 10000 ohm.
4. device according to claim 1, it is characterised in that described switch adopts jumper or toggle switch to realize.
5. device according to claim 1, it is characterised in that described not gate adopts independent logical device or use to have signal and negates the circuit of function and realize.
6. device according to claim 1, it is characterised in that the data bit that described processor hardware configuration words is corresponding is 16,8,32 or 64.
7. device according to claim 1, it is characterised in that described primary sources position is by the pull down resistor output within processor.
8. the method for a loading processing device hardware configuration word, it is characterised in that the method is realized by the device as described in any one of claim 1 to 7, and the method includes:
Before processor reset, the switch state for Guan Bi or disconnection is set according to required processor operating mode;
When processor reset, reset signal output low level, it is low level that driver enables, and the now output of driver enables as opening, the data bit of the hardware configuration word that driver output is corresponding;
Processor reset time obtain hardware configuration word, complete reset after, reset signal output high level, driver enable for height, now driver output enable close, the output of driver becomes high-impedance state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410608256.0A CN105630120B (en) | 2014-11-03 | 2014-11-03 | A kind of method and device of loading processing device hardware configuration word |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410608256.0A CN105630120B (en) | 2014-11-03 | 2014-11-03 | A kind of method and device of loading processing device hardware configuration word |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105630120A true CN105630120A (en) | 2016-06-01 |
| CN105630120B CN105630120B (en) | 2019-03-08 |
Family
ID=56045164
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410608256.0A Expired - Fee Related CN105630120B (en) | 2014-11-03 | 2014-11-03 | A kind of method and device of loading processing device hardware configuration word |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105630120B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106681876A (en) * | 2016-12-29 | 2017-05-17 | 上海斐讯数据通信技术有限公司 | Device and method for recognizing whether software and hardware are matched or not |
| CN114035532A (en) * | 2021-09-23 | 2022-02-11 | 岚图汽车科技有限公司 | ECU marking method, device, storage medium and electronic equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5606715A (en) * | 1995-06-26 | 1997-02-25 | Motorola Inc. | Flexible reset configuration of a data processing system and method therefor |
| CN1725207A (en) * | 2005-04-27 | 2006-01-25 | 杭州华为三康技术有限公司 | Method and system for regulating processor allocation mode |
| CN101465754A (en) * | 2008-12-31 | 2009-06-24 | 上海华为技术有限公司 | Method, equipment and communication veneer for loading reset configuration words |
| CN101515240A (en) * | 2009-03-30 | 2009-08-26 | 华为技术有限公司 | Digital signal processor loading method, electronic device and electronic system |
| CN102854962A (en) * | 2012-08-23 | 2013-01-02 | 哈尔滨工业大学 | MPC8280 minimum system applying CPLD (complex programmable logic device) and state switching method for setting hard reset configuration words |
-
2014
- 2014-11-03 CN CN201410608256.0A patent/CN105630120B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5606715A (en) * | 1995-06-26 | 1997-02-25 | Motorola Inc. | Flexible reset configuration of a data processing system and method therefor |
| CN1725207A (en) * | 2005-04-27 | 2006-01-25 | 杭州华为三康技术有限公司 | Method and system for regulating processor allocation mode |
| CN101465754A (en) * | 2008-12-31 | 2009-06-24 | 上海华为技术有限公司 | Method, equipment and communication veneer for loading reset configuration words |
| CN101515240A (en) * | 2009-03-30 | 2009-08-26 | 华为技术有限公司 | Digital signal processor loading method, electronic device and electronic system |
| CN102854962A (en) * | 2012-08-23 | 2013-01-02 | 哈尔滨工业大学 | MPC8280 minimum system applying CPLD (complex programmable logic device) and state switching method for setting hard reset configuration words |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106681876A (en) * | 2016-12-29 | 2017-05-17 | 上海斐讯数据通信技术有限公司 | Device and method for recognizing whether software and hardware are matched or not |
| CN106681876B (en) * | 2016-12-29 | 2019-08-09 | 上海斐讯数据通信技术有限公司 | A kind of identification software and the whether matched device and method of hardware |
| CN114035532A (en) * | 2021-09-23 | 2022-02-11 | 岚图汽车科技有限公司 | ECU marking method, device, storage medium and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105630120B (en) | 2019-03-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107493685B (en) | Reprogramming a port controller via its own external port | |
| CN102609286B (en) | A kind of FPGA configurator remote update system based on processor control and method thereof | |
| TWI528199B (en) | System and method for automatic extraction of power intent from custom analog/custom digital/mixed signal schematic designs | |
| CN103677671B (en) | Data reading-writing method and system of electrical port module | |
| US10026499B2 (en) | Memory testing system | |
| US10489337B2 (en) | Method, apparatus and system for dynamic optimization of signal integrity on a bus | |
| CN207249670U (en) | Prevent the circuit that the retention time breaks rules | |
| US20140157051A1 (en) | Method and device for debugging a mips-structure cpu with southbridge and northbridge chipsets | |
| CN102622044A (en) | Mainboard and dynamic configuration method of peripheral component interface express (PCIE) interface | |
| CN113986796A (en) | PCIe link width dynamic configuration method, device, equipment and readable medium | |
| CN105446937A (en) | Circuit board based on programmable chip and configuration method of circuit board | |
| CN101076866B (en) | System and method for collocating integrate circuit | |
| CN107305526A (en) | A kind of debugger for microcontroller | |
| CN103793263A (en) | DMA transaction-level modeling method based on Power PC processor | |
| CN105630120A (en) | Processor hardware configuration word loading method and device | |
| US9378027B2 (en) | Field-programmable module for interface bridging and input/output expansion | |
| CN110781130A (en) | System on chip | |
| TWI631355B (en) | Communication and control topology for efficient testing of sets of devices | |
| CN110096291A (en) | Power management chip upgrades circuit, method and the network equipment | |
| CN203250312U (en) | Extensible common core processing daughter board with interferences | |
| CN103477562A (en) | Logic device for combining various interrupt sources into a single interrupt source and various signal sources to control drive strength | |
| CN105573950B (en) | A kind of method based on gate circuit chip setting VR chip address | |
| TWI689818B (en) | Variable electronic apparatus | |
| CN208538117U (en) | A kind of electricity server master board memory failure indicating lamp structure | |
| CN106055510A (en) | FPGA-based control system for automatic detection of configuration bus bit width |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190308 Termination date: 20211103 |