CN105608054B - FFT/IFFT converting means based on LTE system and method - Google Patents

Abstract

The present invention discloses FFT/IFFT converting means and method based on LTE system, and six kinds of transformation points that LTE system defines are divided into two classes：The integral number power of smaller transformation points (128,256,512) all 2, directly carries out corresponding FFT/IFFT transformation.Larger transformation points (1024,1536,2048) are all based on 512 point FFT or IFFT and base r operations are realized, it is simple in structure, the multiplier and adder resource needed is few, compared with prior art, six kinds of transmission bandwidth processing can be supported simultaneously but also block floating point FFT/IFFT is supported to convert.And execute 1536 point FFT/IFFT transformation and only need to use and store 512 twiddle factors, it executes 1024,1536,2048 point FFT/IFFT transformation and only needs to store 1536 twiddle factors in total, reduce the occupancy of resource.

Description

FFT/IFFT (fast Fourier transform/inverse fast Fourier transform) device and method based on LTE (Long term evolution) system

Technical Field

The present invention relates to the field of digital signal processing and communication, and in particular, to an FFT/IFFT transformation apparatus and method based on an LTE system.

Background

The LTE system adopts a 15KHz subcarrier bandwidth, and realizes a variable system bandwidth from 1.4MHz to 20MHz by setting different subcarrier numbers, more specifically, mapping to different resource block (PRB) numbers, where the LTE system defines the correspondence between different system bandwidths in 6 and subcarrier numbers and PRB numbers as follows:

the DFT/IDFT conversion points corresponding to the above six transmission bandwidths are 128, 256, 512, 1024, 1536 and 2048, respectively. For the six transform points required by the LTE system, mainstream FPGA manufacturers such as XILINX and ALTERA provide solutions based on respective FFT/IFFTIP cores, but the common defects are that only one IP core cannot be used to satisfy the requirements of simultaneously implementing the six transmission bandwidths and performing block floating point FFT/IFFT processing, and patent 1536-point FFT/IFFT implementing method and device (application number: 200910172964.3) provides a 1536-point FFT/IFFT implementing method and device, which cannot support block floating point FFT/IFFT transformation, and requires 1536 twiddle factors to be used and stored, which undoubtedly consumes more storage resources.

Disclosure of Invention

An object of the embodiments of the present invention is to provide an FFT/IFFT transformation apparatus and method based on the LTE system, so as to support processing of all transmission bandwidths and support block floating point FFT/IFFT transformation.

In order to achieve the purpose, the invention provides the following scheme:

an FFT/IFFT conversion device based on LTE comprises an input ping-pong buffer unit, a first conjugate processing unit, a 512-point FFT/IFFT processing unit, an input control unit, a radix r operation unit, a second conjugate processing unit and an output end;

wherein the input control unit is configured to:

receiving configuration data and a first sequence p (m), m being 0,1,2.. N-1, N representing the number of transform points and the length of the sequence; the configuration data comprises at least N and a transformation flag; the first value of the transformation mark is used for representing that the first sequence needs to be subjected to forward transformation, and the second value of the transformation mark is used for representing that the first sequence needs to be subjected to inverse transformation;

when the N is not more than 512, directly inputting the first sequence p (m) to the 512-point FFT/IFFT processing unit;

when the N is larger than 512 and the transformation flag is a first value, inputting the first sequence p (m) into the input ping-pong buffer unit;

when the N is larger than 512 and the transformation flag is a second value, the first sequence p (m) is input to the first conjugate processing unit, and the first conjugate processing unit performs conjugation processing to obtain a second sequence p^*(m) and outputting to the input ping-pong buffer unit;

when the N is larger than 512, reading out p (m) or p from the input ping-pong buffer unit r times^*(m) sending to the 512-point FFT/IFFT processing unit; r is N/512; the data read out from the input ping-pong buffer unit at the ith time are as follows: p (m) or p^*(m) 512 point data located at the position where the positive integer of r is multiplied by r-i, wherein i is more than or equal to 1 and less than or equal to r;

the 512-point FFT/IFFT processing unit is used for executing FFT/IFFT conversion with the number of the transform points being 2 to the nth power, n is more than or equal to 1 and less than or equal to 9, wherein:

when the N is not more than 512, performing corresponding FFT/IFFT transformation on the input data according to the transformation mark, and outputting a transformation result to the output end; or,

when the N is more than 512, performing r times of FFT transformation on the data input by the input control unit in r times,obtaining r groups of transformation results and sending the r groups of transformation results to the base r arithmetic unit; wherein the 512 point data in the ith group of transformation results is p (m) or p^*(m) the transform result of FFT transform of 512 point data located at the position where r is a positive integer multiple minus r-i;

the base r operation unit is configured to:

when the N is larger than 512 and the transformation flag is a first value, performing a base r operation on the r group transformation results to obtain a third sequence Y (m), and outputting the third sequence Y (m) to the output end, wherein the third sequence Y (m) is a sequence obtained by performing forward transformation on the first sequence p (m); or,

when the N is larger than 512 and the transformation mark is a second value, performing a basic r operation on the r groups of transformation results to obtain a fourth sequence yy (m), multiplying yy (m) by 1/N to obtain a fifth sequence yy (m), and outputting the yy (m) to the second conjugation processing unit;

the second conjugation processing unit is configured to perform conjugation processing on input data to obtain a sixth sequence y (m), and output the sixth sequence y (m) to the output end, where the sixth sequence y (m) is a sequence obtained by performing inverse transformation on the first sequence p (m);

the FFT/IFFT transformation, the radix r operation and the multiplication by 1/N are operated in a block floating point mode; the block floating point mode represents one datum by a block floating point factor and a mantissa, and the block floating point factors of 512-point data in the ith group of transformation results are the same.

An FFT/IFFT transform method based on LTE comprises the following steps:

receiving a first sequence p (m); n-1, N representing the number of transform points and the length of a sequence, the first sequence being intended to be transformed into a forward transform or an inverse transform;

directly carrying out corresponding FFT/IFFT transformation on the first sequence p (m) with N not more than 512;

performing first transformation processing on a first sequence p (m) to be subjected to forward transformation, wherein N is greater than 512 points;

conjugating the first sequence p (m) with N larger than 512 points and to be inverse transformed to obtain a second sequence p^*(m) for the second sequence p^*(m) performing the first transform process, and performing a second transform process on the sequence obtained after the first transform process;

the first transform process includes:

for p (m) or p^*(m) performing r times of 512-point FFT to obtain r groups of transform results, wherein the ith time of 512-point FFT comprises p (m) or p^*(m) performing FFT on 512 point data located at a positive integer multiple of r minus r-i position; the 512 point data in the ith group of transformation results is p (m) or p^*(m) a transform result of 512 points located at the position where r is a positive integer multiplied by r-i after FFT; r is N/512, i is more than or equal to 1 and less than or equal to r;

performing a base r operation on the r groups of transformation results;

the second transform process includes: multiplying by 1/N and then performing conjugation treatment, or performing conjugation treatment and then multiplying by 1/N;

the FFT/IFFT transformation, the radix r operation and the multiplication by 1/N are operated in a block floating point mode;

the block floating point mode represents data by block floating point factors and mantissas, and the 512-point data in the ith group of transformation results have the same block floating point factor.

An FFT/IFFT conversion device based on LTE comprises an input ping-pong buffer unit, a first conjugate processing unit, a 512-point FFT/IFFT processing unit, an input control unit, a radix r operation unit, a second conjugate processing unit and an output end;

wherein the input control unit is configured to:

receiving configuration data and a first sequence p (m), m being 0,1,2.. N-1, N representing the number of transform points and the length of the sequence; the configuration data comprises at least N and a transformation flag; the first value of the transformation mark is used for representing that the first sequence needs to be subjected to forward transformation, and the second value of the transformation mark is used for representing that the first sequence needs to be subjected to inverse transformation;

when the N is not more than 512, directly inputting the first sequence p (m) to the 512-point FFT/IFFT processing unit;

when the N is larger than 512 and the transformation flag is a second value, inputting the first sequence p (m) into the input ping-pong buffer unit;

when the N is larger than 512 and the transformation flag is a first value, inputting the first sequence p (m) to the first conjugate processing unit, and performing conjugate processing by the first conjugate processing unit to obtain a second sequence p^*(m) and outputting to the input ping-pong buffer unit;

when the N is larger than 512, reading out p (m) or p from the input ping-pong buffer unit r times^*(m) sending to the 512-point FFT/IFFT processing unit; r is N/512; the data read out from the input ping-pong buffer unit at the ith time are as follows: p (m) or p^*(m) 512 point data located at the position where the positive integer of r is multiplied by r-i, wherein i is more than or equal to 1 and less than or equal to r;

the 512-point FFT/IFFT processing unit is used for executing FFT/IFFT conversion with the number of the transform points being 2 to the nth power, n is more than or equal to 1 and less than or equal to 9, wherein:

when the N is not more than 512, performing corresponding FFT/IFFT transformation on the input data according to the transformation mark, and outputting a transformation result to the output end; or,

when the N is larger than 512, performing r-time IFFT transformation on data input by the input control unit for r times to obtain r groups of transformation results, and sending the r groups of transformation results to the base r operation unit; wherein the 512 point data in the ith group of transformation results is p (m) or p^*(m) a transform result of IFFT-transforming 512 point data located at a positive integer multiple-minus r-i position of r;

the base r operation unit is configured to:

when the N is larger than 512 and the transformation flag is a second value, performing a base r operation on the r groups of transformation results to obtain a third sequence Y (m), and outputting the third sequence Y (m) to the output end, wherein the third sequence Y (m) is a sequence obtained by performing inverse transformation on the first sequence p (m); or,

when the N is larger than 512 and the transformation mark is a first value, performing a basic r operation on the r groups of transformation results to obtain a fourth sequence yy (m), multiplying yy (m) by 512 to obtain a fifth sequence y (m), and outputting y (m) to the second conjugation processing unit;

the second conjugation processing unit is configured to perform conjugation processing on input data to obtain a sixth sequence y (m), and output the sixth sequence y (m) to the output end, where the sixth sequence y (m) is a sequence obtained by performing forward transformation on the first sequence p (m);

the FFT/IFFT transformation, the radix r operation and the multiplication by 1/N are operated in a block floating point mode;

the block floating point mode expresses data by block floating point factors and mantissas, and the block floating point factors of 512 point data in the ith group of transformation results are the same; the block floating point mode represents one datum by a block floating point factor and a mantissa, and the block floating point factors of 512-point data in the ith group of transformation results are the same.

An FFT/IFFT transform method based on LTE is characterized by comprising the following steps:

receiving a first sequence p (m); n-1, N representing the number of transform points and the length of a sequence, the first sequence being intended to be transformed into a forward transform or an inverse transform;

directly carrying out corresponding FFT/IFFT transformation on the first sequence p (m) with N not more than 512;

performing first transformation processing on a first sequence p (m) to be subjected to inverse transformation, wherein N is greater than 512 points;

the first sequence p (m) with N larger than 512 points and to be subjected to forward transformation is subjected to conjugation processing to obtain a second sequence p^*(m) for the second sequence p^*(m) performing the first transform process, and performing a second transform process on the sequence obtained after the first transform process;

the first transform process includes:

for p (m) or p^*(m) carrying out 512-point IFFT for r times to obtain r groups of transformation results, wherein the ith 512-point IFFT comprises p (m) or p^*(m) performing IFFT on 512 point data located at a positive integer multiple of r minus r-i position; the 512 point data in the ith group of transformation results is p (m) or p^*(m) a transform result of IFFT transform of 512 points located at the position where r is a positive integer multiplied by r-i; r is N/512, i is more than or equal to 1 and less than or equal to r;

performing a base r operation on the r groups of transformation results;

the second transform process includes: multiplying by 512 and then performing conjugation treatment, or performing conjugation treatment and then multiplying by 512;

the 512-point FFT transformation, the radix r operation and the multiplication by N are operated in a block floating point mode;

the block floating point mode represents data by block floating point factors and mantissas, and the 512-point data in the ith group of transformation results have the same block floating point factor.

In the embodiment of the invention, six kinds of conversion points defined by the LTE system are divided into two types: the smaller transform points (128, 256, 512, i.e. N is not greater than 512) are all integer powers of 2, and the corresponding FFT/IFFT transform is performed directly. The larger transform point numbers (1024, 1536, 2048, that is, N is greater than 512) are all realized based on 512-point FFT or IFFT and radix r operation, the structure is simple, and the needed multiplier and adder resources are few. Compared with the prior art, the embodiment of the invention can simultaneously support six kinds of transmission bandwidth processing and block floating point FFT/IFFT transformation, only 512 twiddle factors need to be used and stored when 1536-point FFT/IFFT transformation is executed, only 1536 twiddle factors need to be stored when 1024, 1536 and 2048-point FFT/IFFT transformation is executed, and the occupation of resources is reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1,2 and 4 are exemplary structural diagrams of an FFT/IFFT transformation apparatus based on an LTE system according to an embodiment of the present invention;

fig. 3a, 3b, 5a, and 5b are exemplary flowcharts of an FFT/IFFT transformation method based on an LTE system according to an embodiment of the present invention.

Detailed Description

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The technical principle on which the invention is based is as follows:

let the length N of the sequence x (N) to be Discrete Fourier Transformed (DFT) be 512r, and the sequence index N be r N₁+n₀Wherein n is₁＝0,1,2,...511，n₀R-1, 0,1,2,; let the length N of the transformed sequence X (k) be r 51, and the 2 index k be 512 k₁+k₀Wherein k is₁＝0,1,r2-,，k₀No. 0,1,2.. 511, substituting N equal to 1024, 1536, and 2048 into the DFT relation, respectivelyThe DFT relations of 1024, 1536, and 2048 points obtained by the expansion are shown in the following formulas (1) to (3), respectively:

wherein k is₁＝0,1；k₀＝0,1,2,...511

Wherein k is₁＝0,1,2；k₀＝0,1,2,...511

Wherein k is₁＝0,1,2,3；k₀＝0,1,2,...511

In the above formulas (1) to (3), [ ] indicate a 512-point DFT transform.

The equations (1) to (3) are summarized and each includes 512-point DFT. Also, 512 twiddle factors are required for each of the 1024-point and 2048-point DFT calculationsThe 2048 point DFT computation also requires 512 twiddle factors1536-point DFT calculation requires 512 twiddle factors

As for Inverse Discrete Fourier Transform (IDFT), the result X (k) of the N-point DFT may be represented as X (k) ═ R_k+j*I_kK-0, 1,2.. N-,1 wherein R_kIs the real part of X (k), I_kIs the imaginary part of X (k); let the conjugation of X (k) be X^*(k)，X^*(k)＝R_k-j*I_kN-1, substituting X (k) into the IDFT equationEquation (4) is obtained:

for the above X^*(k) Performs DFT and multiplies the transform result byEquation (5) is obtained:

comparing the formula (4) and the formula (5), the left sides of the two formulas are equal, and the right sides of the two formulas are conjugate, so that the following can be obtained: for an IDFT to be obtained by inputting a sequence X (k) of length N, k being 0,1,2^*(k) Then, X is added^*(k) And performing DFT of N points, multiplying the transformation result by 1/N, and then taking conjugation to obtain a time domain signal x (N).

That is, IDFT may be implemented by DFT.

Similarly, the length N of the sequence X (k) to be subjected to IDFT is 512 r; sequence index k ═ r × k₁+k₀Wherein k is₁＝0,1,2,...511，k₀R-1, 0,1,2,; let the transformed sequence index n be 512 n₁+n₀Wherein n is₁＝0,1,2,...r-1，n₀Substituting 0,1,2.. 511 into equation (5) can convert the relation of 1024, 1536, 2048-point IDFT into the following equations (6) to (8):

wherein n is₁＝0,1；n₀＝0,1,2...511

Wherein n is₁＝0,1,2；n₀＝0,1,2...511

Wherein n is₁＝0,1,2,3；n₀＝0,1,2...511

In the above formulas (6) to (8), [ ] indicates a 512-point DFT. The general expressions (1) - (3) and (6) - (8) all include 512-point DFTs.

Of these, 512 twiddle factors are needed for 1024-point and 2048-point DFTsWhile 1024-point and 2048-point IDFT requires 512 twiddle factorsDue to k₀＝0,1,2,...511，n₀＝0,1,2,...511, therefore, in practice, 512 twiddle factors are needed for each of 1024-point and 2048-point DFT/IDFT

Similarly, a 1536-point DFT/IDFT computation requires 512 twiddle factorsThe 2048-point DFT/IDFT calculation also requires 512 twiddle factors

In this way, DFT and IDFT at 1024, 1536, and 2048 points can be collectively implemented by DFT, and specific implementations of DFT processing at 1024, 1536, and 2048 points can be referred to as equations (1) - (3), and specific implementations of IDFT processing at 1024, 1536, and 2048 points can be referred to as equations (6) - (8), which is referred to as principle one in the present disclosure.

Principle two will be described below:

the sequence x (n) to be subjected to DFT is represented as x (n) ═ R_n+j*I_nN-1, wherein R is 0,1,2_nIs the real part of x (n), I_nIs the imaginary part of x (n); let the conjugation of x (n) be x^*(n)＝R_n-j*I_nN-1, substituting x (N) into the DFT relationTo obtain formula (9):

conjugate x to x (n)^*(N) performing an N-point IDFT, and multiplying the result of the transformation by N to obtain formula (10):

comparing the formula (9) and the formula (10), the left sides of the two formulas are equal, and the right sides of the two formulas are conjugate, so that the following can be obtained: for a DFT to be obtained for a sequence x (N) with an input length N, where N is 0,1,2^*(n) adding x^*And (N) carrying out IDFT, and finally, multiplying the transformation result by N and then taking conjugation to obtain X (k).

That is, DFT may also be implemented by IDFT.

Let N512 r, index N r N₁+n₀Wherein n is₁＝0,1,2,，n₀R-1, and a transformed sequence index k 512 k₁+k₀Whereink₀0,1,2.. 511, mixing the above x^*(N) substituting into equation (10), let N equal 1024, 1536, and 2048 respectively and develop their corresponding DFTs respectively can be converted into the following equations (11) - (13):

wherein k is₁＝0,1；k₀＝0,1,2,...511

Wherein k is₁＝0,1,2；k₀＝0,1,2,...511

Wherein k is₁＝0,1,2,3；k₀＝0,1,2,...511。

Let the length N of the sequence X (k) to be IDFT be equal to512 x r; sequence index k ═ r × k₁+k₀Wherein k is₁＝0,1,2,...511，k₀R-1, 0,1,2,; let the transformed sequence index n be 512 n₁+n₀Wherein n is₁＝0,1,2,...r-1，n₀Substitute X (k) into IDFT formula 0,1,2And let N be 1024, 1536 and 2048 respectively to obtain their corresponding IDFT as following formulas (14) to (16):

wherein n is₁＝0,1；n₀＝0,1,2...511

Wherein n is₁＝0,1,2；n₀＝0,1,2...511

Wherein n is₁＝0,1,2,3；n₀＝0,1,2...511

In the above formulas (11) to (16)]The inner table represents a 512-point IDFT transform. The general expressions (11) to (13) and (14) to (16) each include an IDFT of 512 points. Due to k₀＝0,1,2,...511，n₀511 thus, 512 twiddle factors are needed for each of the 1024-point and 2048-point DFT/IDFTSimilarly, a 1536-point DFT/IDFT computation requires 512 twiddle factorsThe 2048-point DFT/IDFT calculation also requires 512 twiddle factors

Similarly, DFT and IDFT at 1024, 1536, and 2048 points can be collectively implemented by IDFT, and specific implementations of DFT processing at 1024, 1536, and 2048 points can be referred to as equations (11) - (13), and specific implementations of IDFT processing at 1024, 1536, and 2048 points can be referred to as equations (14) - (16), which is referred to as principle two in the present invention.

Based on the first principle, please refer to fig. 1, the FFT/IFFT transforming apparatus based on the LTE system according to the embodiment of the present invention may include the following components:

the device comprises an input ping-pong buffer unit 1, a first conjugate processing unit 2, a second conjugate processing unit 3, a 512-point FFT/IFFT processing unit 4, an input control unit 5, an output end 6 and a radix r operation unit 7;

wherein,

the input control unit 5 may include at least one input terminal and three output terminals (first to third output terminals).

The input control unit 5 is configured to perform the following operations:

1) receiving (by an input) configuration data and a first sequence;

the sequence to be transformed can be referred to as the first sequence, denoted as p (m), m being 0,1,2

p (m) can be X (n) or X (k) as described in principle one.

The configuration data may include a number of transform points N and a transform flag.

Wherein the number of transform points is used to characterize the length of the first sequence. For example, N128, 256, 512, 1024, 1536, 2048.

The transformation flag can be a first value or a second value, wherein the first value is used for representing that the first sequence needs to be subjected to forward transformation (FFT transformation), and the second value is used for representing that the first sequence needs to be subjected to inverse transformation (IFFT transformation); more specifically, a positive transform may be represented by 0 and an inverse transform may be represented by 1, or vice versa. Wherein p (m) is X (n) in the forward transform and X (k) in the reverse transform.

2) If N is not greater than 512, p (m) is directly input to the 512-point FFT/IFFT processing unit 4.

That is, p (m) at 128, 256, and 512 points is subjected to FFT/IFFT, and the first sequence p (m) is directly input to the 512-point FFT/IFFT processing unit 4 through the first output terminal of the input control unit 5.

3) If N is greater than 512 and the conversion flag is the first value, p (m) is input to the input ping-pong buffer unit 1.

For example, if N is 2048 and the transform flag indicates that a forward transform is performed (the first value), p (m) may be input to the input ping-pong buffer unit 1 through the second output terminal of the input control unit 5.

4) When N is greater than 512 and the conversion flag is a second value, the p (m) is input to the first conjugate processing unit 2, and the first conjugate processing unit 2 performs conjugation processing to obtain a conjugation sequence p of p (m)^*(m) and reacting p^*(m) output to the input ping-pong buffer unit 1.

p^*(m) is X in the description of the aforementioned principle^*(k)。

For example, if N is 2048 and the transform flag indicates that the inverse transform (the second value) is performed, the first sequence p (m) may be input to the first conjugate processing unit 2 through the third output terminal of the input control unit 5.

It should be noted that, the execution of 2) to 4) is performed according to the values of N and the transformation flag.

5) When the N is larger than 512, reading out p (m) or p (m) from the input ping-pong buffer unit 1 r times^*(m) is sent to the 512-point FFT/IFFT processing unit 4.

Where r is N/512, the data read out from the input ping-pong buffer unit 1 by the input control unit 5 the ith time is: p (m) or p^*And (m) 512 point data at the position where the positive integer of r is multiplied by r-i, wherein i is more than or equal to 1 and less than or equal to r.

For example, when N is 2048, the input control unit 5 needs to read 4 times from the input ping-pong buffer unit 1, where the 4 read operations are: reading p (m) or p^*(m) at 512 points located at the positive integer multiple of 4 minus 3, reading p (m) or p^*(m) at 512 points located at the positive integer multiple of 4 minus 2, reading p (m) or p^*(m) at 512 points at the positive integer multiple 1 position of 4, reading p (m) or p^*512 dots located at positive integer multiple positions of 4 in (m); the transformation of other points can be analogized, and is not described in detail.

First conjugate processing unit 2: for performing conjugate processing on input data (X (k) in the first introduction of the aforementioned principle) and outputting the processing result to the input ping-pong buffer unit 1.

Inputting a ping-pong buffer unit 1: for buffering input sequences (p (m) or p)^*(m)), the sequence of inputs being provided by the first conjugate processing unit 2 or the input control unit 5, p (m) or p^*The number of points of (m) is greater than 512 points (1024, 1536, and 2048).

The first conjugate processing unit 2, the input control unit 5, and the input ping-pong buffer unit 1 may be integrated into (constitute) a pre-processing unit.

512-point FFT/IFFT processing unit 4: the block floating point FFT/IFFT conversion device is used for executing block floating point FFT/IFFT conversion with the number N of the N-th power of 2, N is more than or equal to 1 and less than or equal to 9, the block floating point mode expresses data by block floating point factors and mantissas, N conversion results obtained by the N-point FFT/IFFT share one block floating point factor, when N is not more than 512, the block floating point factor is blk _ exp3 described later in the text, and when N is more than 512, the block floating point factor is blk _ exp in the text described later_nN is more than or equal to 1 and less than or equal to r, wherein:

1) if N is not greater than 512, performing corresponding FFT/IFFT conversion on the input data, and outputting the conversion result to an output end 6;

for example, if N is 128 points and the transform flag indicates that the forward transform is performed, the 512-point FFT/IFFT processing unit 4 performs 128-point FFT on the first sequence p (m). If the transform flag indicates inverse transform, the 512-point FFT/IFFT processing unit 4 performs 128-point IFFT on the first sequence p (m).

2) If N is larger than 512, the input control unit is divided into r times of input p (m)/p^*(m) r FFT transformations are performed to obtain r sets of transformation results (each set includes 512 transformation results or each set includes 512 point data), and the r sets of transformation results are sent to the radix r arithmetic unit 7, where r is N/512.

Wherein the 512 point data in the ith group of transformation results is p (m) or p^*(m) the conversion result of the 512 point data positioned at the position where the positive integer of r is multiplied by r-i after FFT conversion, i is more than or equal to 1 and less than or equal to r.

By configuring the 512-point FFT/IFFT processing unit 4, when N is less than or equal to 512, the input data is subjected to corresponding FFT/IFFT conversion according to the conversion mark, and the conversion result is output to the output end 6; and at N > 512 the transformation result is sent to the write control unit 31. This, of course, requires that the input control unit 5 and the 512-point FFT/IFFT processing unit 4 share configuration data.

The base r arithmetic unit 7 is configured to:

1) if N is greater than 512 and the conversion flag is the first value, the r groups of conversion results are subjected to the base r operation, and the obtained operation results form a third sequence Y (m) and are output to the output terminal 6.

2) When N is greater than 512 and the conversion flag is the second value, the input r groups of conversion results are subjected to a base r operation, the obtained operation results form a fourth sequence yy (m), the fifth sequence yy (m) is obtained by multiplying yy (m) by 1/N, and y (m) is output to the second conjugation processing unit 3.

The specific composition of the radix operation unit 7 will be described in detail later herein.

The second conjugation processing unit 3 is configured to: the input data (y × m output from the base r arithmetic unit 7) is subjected to conjugate processing to obtain a sixth sequence y (m), and is output to the output terminal 6.

Wherein y (m) corresponds to the output result obtained by equation (5).

In this embodiment, the sixth sequence Y (m) is a time domain signal X (n), and the third sequence Y (m) is a frequency domain transformation result X (k).

In another embodiment of the present invention, referring to fig. 2, the radix operation unit 7 may include a write control unit 31, first to fourth ping-pong buffer units (32, 33, 34, 35), a twiddle factor first storage unit 36, a twiddle factor second storage unit 37, a twiddle factor third storage unit 38, a read control unit 39, a first twiddle factor read control unit 40, a first multiplexer MUX1, a twiddle factor multiplication unit 41, a block floating point processing unit 42, first to third complex multiplication units (43, 44, 45), first to third complex addition units (46, 47, 48), and a second multiplexer MUX 2.

Wherein,

the write control unit 31: and the unit is configured to, when N is greater than 512, perform write control on the output result of the 512-point FFT/IFFT processing unit 4, and output the ith group of transform results in the r groups of transform results to the ith ping-pong buffer unit in the first to fourth ping-pong buffer units.

That is, p (m) or p^*And (m) the conversion result of FFT conversion is output to the ith ping-pong buffer unit after 512 points positioned at the positive integer multiple reduction (r-i) position of r, wherein i is more than or equal to 1 and is less than or equal to r.

For example, when N is 2048, p (m) or p^*The conversion result of FFT conversion of 512 points which are positioned at the positive integer multiple-minus-3 position of 4 in (m) is stored in a first ping-pong buffer unit, and p (m) or p^*(m) the conversion result of FFT conversion is carried out on 512 points which are positioned at the positive integer multiple minus 2 position of 4, and the conversion result is stored into a second ping-pong buffer unit, and p (m) or p^*(m) a positive integer multiple reduction at 4The conversion result of the FFT conversion of 512 points on the position 1 is stored in a third ping-pong buffer unit; p (m) or p^*(m) the conversion result of FFT conversion of 512 points which are positioned on the positive integral multiple position of 4 is stored in a fourth ping-pong buffer unit.

Outputting the 512-point FFT-transformed transform result located at the positive integer multiple-minus (r-i) position of r to the ith ping-pong buffer unit can be realized by configuring the write control unit 31.

In a specific implementation, the input control unit 5 may share configuration data with the write control unit 31.

First to fourth ping-pong buffer units (32-35): the four ping-pong buffer units are completely the same and each ping-pong buffer unit has a depth of 1024.

Twiddle factor first storage unit 36: for storing (512 first twiddle factors (first group of first twiddle factors) needed in calculation of 1024 points and 2048 points FFT/IFFTk₀No. 0,1,2,. 511 (please refer to the description of the first principle, which is not repeated herein).

Twiddle factor first storage unit 37: used for storing 512 first twiddle factors (a second group of first twiddle factors) needed by 1536-point FFT/IFFT calculationk₀0,1,2.. 511 (please refer to the introduction of the aforementioned principle one, which is not described herein);

twiddle factor first storage unit 38: for storing another 512 first twiddle factors (third group of first twiddle factors) needed in 2048-point FFT/IFFT calculationk₀No. 0,1,2,. 511 (please refer to the description of the first principle, which is not repeated herein).

The twiddle factor first through third storage units may be collectively referred to as twiddle factor storage units.

The read control unit 39: for controlling the reading of the data stored in the first to the r ping-pong buffer units and sending the read data to the block floating point processing unit 42, and controlling the time when the first twiddle factor read control unit 40 reads the first twiddle factor each time (the read control unit 39 controls the first twiddle factor read control unit to read the corresponding twiddle factor storage unit synchronously each time it issues a read instruction).

The "controlling reading of the data stored in the first to the r-th ping-pong buffer units" may specifically include:

the read command is sent to the same address space of the first ping-pong buffer unit to the r-ping-pong buffer unit r times at the same time to read the r set of transformation results, i.e. the r set of transformation results are read r times each time. And (3) the r groups of conversion results read out at the jth time are used for calculating data (j is more than or equal to 1 and less than or equal to r) at 512(j-1) + 1-512 j positions of Y (m) or Y (m).

For example, when N is 2048, valid read instructions are simultaneously issued to the same address space of the first to fourth ping-pong buffer units, and the first to fourth ping-pong buffer units are simultaneously read four times, each time 512 data of the first to fourth ping-pong buffer units are read. 512 × 4 data (four groups of conversion results) which are simultaneously read out from the first ping-pong buffer unit to the fourth ping-pong buffer unit for the first time are used for calculating the first 512 data of Y (m) or Y (m), namely the first group of operation results in the r groups of operation results; 512 × 4 data (four groups of conversion results) simultaneously read out from the first ping-pong buffer unit to the fourth ping-pong buffer unit for the second time are used for calculating the first middle 512 data of Y (m) or Y (m), namely the second group of operation results in the r groups of operation results; 512 × 4 data (four groups of conversion results) which are simultaneously read out from the first ping-pong buffer unit to the fourth ping-pong buffer unit for the third time are used for calculating 512 data in the second middle of Y (m) or Y (m), namely a third group of operation results in the r groups of operation results; the 512 × 4 data (four groups of conversion results) read out from the first ping-pong buffer unit to the fourth ping-pong buffer unit at the same time are used for calculating the last 512 data of Y (m) or Y (m), i.e. the fourth (r) group of operation results in the aforementioned r group of operation results.

The first to fourth input ping-pong buffer units may be collectively referred to as ping-pong buffer units.

First twiddle factor read control unit 40: for controlling the reading of the data in the twiddle factor first storage unit 36, the twiddle factor second storage unit 37, and the twiddle factor third storage unit 38, and outputting the read data to the twiddle factor multiplication unit 41.

Wherein:

when N is 1024, the first twiddle factor reading control unit 40 reads out the twiddle factor from the twiddle factor first storage unit 36And outputs to the twiddle factor multiplying unit 41;

when N is 1536, the first twiddle factor reading control unit 40 reads out the twiddle factor from the second twiddle factor storage unit 37And outputs to the twiddle factor multiplying unit 41;

when N is 2048, the first twiddle factor reading control unit 40 simultaneously reads out the twiddle factors from the first twiddle factor storage unit 36The twiddle factor is read from the twiddle factor third storage unit 38And output to twiddle factor multiplying unit 41 where k₀＝0,1,2,...511。

It should be noted that the read control unit 39 and the first twiddle factor read control unit 40 respectively need to synchronously read the corresponding ping-pong buffer unit and the corresponding twiddle factor storage unit r times.

The first multiplexer MUX1 is configured to select one second twiddle factor from three sets (11) of second twiddle factors and output the selected second twiddle factor to the twiddle factor multiplying unit 41.

The second twiddle factor parameter 1 in FIG. 2 is a first set of second twiddle factors, includingAndcalculation of FFT/IFFT for 1024 points and 2048 points.

The second twiddle factor parameter 2 is a second set of second twiddle factors comprisingAndfor 1536-point FFT/IFFT calculation.

The second twiddle factor parameter 3 is a third set of second twiddle factors comprisingAndfor 2048-point FFT/IFFT computation.

In the actual implementation process, simplification is carried out according to the characteristics of the twiddle factors;

for example:

wherein:

when N is 1024, the first 512 data of Y (m) or Y x (m) are calculated and selectedSelection of last 512 data

When N is 1536, the first 512 data of Y (m) or Y (m) are calculated and selectedSelect 512 data in the middleSelection of last 512 data

When N is 2048, the first 512 transform results of Y (m) or Y (m) are calculated and selectedAndselection of the first intermediate 512 transform resultsAndsecond intermediate 512 transform resultsAndselecting the last 512 transform resultsAnd

twiddle factor multiplying unit 41: for performing complex multiplication operation on the first twiddle factor and the second twiddle factor and outputting a first calculation result G and a second calculation result H to the first and second complex multiplication units, respectively. Wherein:

when N is 1024, H is 0, and when the first 512 data items of Y (m) or Y (m) are calculated, that is, when the last 512 data items of Y (m) or Y (m) are calculated, that is, when the data items at the 512(j-1) +1 to 512j positions of Y (m) or Y (m) are calculated, N is 1536, when the data items at the 512(j-1) +1 to 512j positions of Y (m) or Y (m) are calculated

2048, when calculating data at the 512(j-1) + 1-512 j position in Y (m) or Y x (m)

J is not less than 1 and not more than r, k₀＝0,1,2...511。

Block floating point processing unit 42: the device is used for carrying out block floating point processing on the input r groups of transformation results and sending the processing results to the first complex multiplication unit and the first and second complex addition units.

The result of the block floating point processing is actually a mantissa and the block floating point factor is an exponent.

The specific way of block floating point processing is as follows:

taking any one block floating point factor (for example, the block floating point factor with the maximum or minimum absolute value) in the r block floating point factors corresponding to the r groups of conversion results as a reference, and taking other block floating point factors blk _ exp₁,blk_exp₂...blk_exp_rCorresponding transformation result (mantissa) S₁,S₂...S_rMake a corresponding left or right shift, therebyEach set of transform results (mantissas) R₁,R₂...R_rThere is the same block floating point factor blk _ exp 1.

For example, when the block floating point factor as the reference is 10 and the block floating point factor corresponding to the group a transform result is 9, the 512 point data in the group a transform result is shifted to the right by one bit, and when the block floating point factor corresponding to the group B transform result is 12, the 512 point data in the group B transform result is shifted to the left by 2 bits.

Meanwhile, in order to ensure that data does not overflow during the operation of the radix R, the block floating point processing unit 42 needs to perform the above R pairs according to the difference of the number of conversion points₁,R₂...R_rScaling and simultaneously adjusting the block floating point factor blk _ exp1 results in the adjusted block floating point factor blk _ exp 2.

For example, when N is 2048, the calculation of X (k) or X (N) requires four-term summation regardless of whether the transform flag is the first value or the second value, and when the word length is constant, 4 sets of transform results R are required to ensure that the result of the radix R operation does not overflow₁,R₂,R₃,R₄Scaling and simultaneously adjusting the block floating point factors blk _ exp1 results in new block floating point factors blk _ exp 2.

Specifically, scaling may be achieved by right shifting, for example, when N is 2048, each data in 4 sets of transform results is right shifted by X bits (X may be equal to 4, 3 or other positive numbers), and blk _ exp1 is summed with X to obtain the adjusted reference block floating point factor blk _ exp 2.

For another example, when N equals 1536, each data in 3 sets of transform results is right shifted by Y bits (Y may be equal to 3, 2, or other positive number), and blk _ exp1 is summed with Y to obtain the adjusted base block floating point factor blk _ exp 2.

By analogy, the larger the number of transform points, the larger the number of bits to be right-shifted.

In the process of carrying out 1024, 1536 and 2048-point IFFT, in order to prevent the influence of directly multiplying by 1/1024, 1/1536 and 1/2048 on the calculation precision, the following processing can be carried out:

when N is 1024 and the transform flag is the second value, the difference between the block floating point factor blk _ exp2 and 10 is made to obtain the final block floating point factor blk _ exp 3.

For example, assume that the block floating point factor blk _ exp2 is 11, and for an IFFT transform with N-1024, let 11-10 be 1. The final block floating point factor blk _ exp3 is 1.

When N is 1536 and the transform flag is the second value, the difference between the block floating point factors blk _ exp2 and 9 is made to obtain the final block floating point factor blk _ exp 3.

It should be noted that for the 1536-point IFFT, the mantissa needs to be multiplied by 1/3, since (1/1536) — (1/3) × 2^-9To achieve multiplication by 1/1536, multiplication by 1/3 is subsequently required. As will be described later, at the second multiplexer MUX2, a multiplication by 1/3 is achieved.

When N is 2048 and the transform flag is the second value, the difference between the block floating point factors blk _ exp2 and 11 is made to obtain the final block floating point factor blk _ exp 3.

In the present invention, the twiddle factor multiplying unit 41, the first to third complex multiplying units (43, 44, 45), and the first to third complex adding units (46, 47, 48) all operate in a block floating point manner. The output result at output 6 is also the final block floating point factor (e.g., blk _ exp3) and mantissa, so the actual transformation result is the output result at output 6 multiplied by 2^blk_exp3。

In addition, in order to ensure that the processing architectures of 1024, 1536, and 2048-point FFT/IFFT are the same, when N is 1024, the first output terminal a of the block floating point processing unit 42 outputs the first set of processing results (i.e., the result of block floating point processing on the data read by the read control unit 39 from the first ping-pong buffer unit 32), and the fourth output terminal D outputs the second (r) set of processing results (i.e., the result of block floating point processing on the data read by the read control unit 39 from the second ping-pong buffer unit 33); the second output terminal B and the third output terminal C of the block floating point processing unit 42 output 0;

when N is 1536, the second output terminal B of the block floating point processing unit 42 outputs 0, and the first output terminal a, the third output terminal C, and the fourth output terminal D respectively output the first to third groups of processing results, that is, the results of block floating point processing on the data read out from the first to third ping-pong cache units by the read control unit 39 are respectively output;

when N is 2048, the first to fourth groups of processing results output by the first to fourth output terminals of the block floating point processing unit 42, that is, the data read out from the first to third ping-pong buffer units by the read control unit 39 are output to the block floating point processing unit for processing.

The block floating point processing unit 42 may share configuration data with the input control unit 5.

First complex multiplication unit 43: the processing unit is configured to complex-multiply the first calculation result G output by the twiddle factor multiplying unit 41 with the processing results output by the second output terminal and the fourth output terminal of the block floating point processing unit 42, respectively, to obtain a first complex multiplication result E ═ G × B and a second complex multiplication result F ═ G × D, send the first complex multiplication result E ═ G × B to the first complex adding unit 46, and send the second complex multiplication result F ═ G × D to the second complex adding unit 47.

First complex addition unit 46: for performing complex addition on the processing result output from the first output terminal of the block floating point processing unit 42 and the first complex multiplication result output from the first complex multiplication unit 43 to obtain a first complex addition result, and sending the first complex addition result to the third complex addition unit 48.

Second complex addition unit 47: for performing complex addition on the processing result output from the third output terminal of the block floating point processing unit 42 and the second complex multiplication result F output from the first complex multiplication unit 43 to obtain a second complex addition result, and sending the second complex addition result to the second complex multiplication unit 44.

Second complex multiplication unit 44: for complex-multiplying the second complex addition result output by the second complex addition unit 47 with the second calculation result H output by the twiddle factor multiplication unit 41 to obtain a third complex multiplication result, and sending the third complex multiplication result to the third complex addition unit 48.

Third complex addition unit 48: for complex-adding the first complex addition result output by the first complex adding unit 47 and the third complex multiplication result of the second complex multiplying unit 44 to obtain a third complex addition result, and sending the third complex addition result to the third complex multiplying unit 45.

A second multiplexer MUX2 for sending 1/3 to the third complex multiplication unit when N1536 and the transform flag is the second value (inverse transform); when N is 1024, 1536, or 2048 and the transform flag is the first value (positive transform), sending 1 to the third complex multiplication unit 45; when N is 1024 or 2048 and the transform flag is the second value, 1 is sent to the third complex multiplication unit 45.

The output of MUX2 may be controlled by the SEL signal.

Third complex multiplication unit 45: a Multiplexer (MUX) 3(MUX3 is the aforementioned output terminal 6) for complex-multiplying the output data of the second multiplexer MUX2 with the third complex addition result output by the third complex addition unit 48 to obtain a fourth complex multiplication result, and when N is 1024, 1536, or 2048 and the transformation flag is the first value, sending the fourth complex multiplication result to the third multiplexer MUX 3; when N is 1024, 1536, or 2048, and the transform flag is the second value, the fourth complex multiplication result is sent to the second conjugation processing unit 3.

A third multiplexer MUX3, for selecting the output result, and outputting the output result of the 512-point FFT/IFFT processing unit 4 when N is 128, 256 or 512; when N is 1024, 1536, or 2048 and the transform flag is the first value, outputting the output result of the third complex multiplication unit 45; and when the N is 1024, 1536 or 2048 and the transformation flag is the second value, outputting the output result of the second conjugation processing unit 3.

In accordance with the first principle, the first embodiment of the present invention further requires to protect an FFT/IFFT implementation method, please refer to fig. 3a or fig. 3b, which at least includes the following steps:

s1, receiving a first sequence p (m); n-1, where N denotes the number of transform points and the sequence length, and the transform to be performed on the first sequence is either a forward transform or an inverse transform;

s2, directly carrying out corresponding FFT/IFFT transformation on the first sequence p (m) with N not more than 512;

s3, performing a first transformation process on a first sequence p (m) to be subjected to forward transformation, wherein N is larger than 512 points;

s4, conjugate processing is carried out on the first sequence p (m) which is to be subjected to inverse transformation and N is larger than 512 points to obtain a second sequence p^*(m) for the second sequence p^*(m) performing a first transformation process, and performing a second transformation process on the sequence obtained after the first transformation process.

The first conversion process includes:

for p (m) or p^*(m) carrying out r times of 512-point FFT (fast Fourier transform) to obtain r groups of transform results, wherein the ith time of 512-point FFT comprises p (m) or p^*(m) performing FFT on 512 point data located at a positive integer multiple of r minus r-i position; the 512 point data in the ith group of transformation results is p (m) or p^*(m) a transform result of 512 points located at the position where r is a positive integer multiplied by r-i after FFT; r is N/512, i is more than or equal to 1 and less than or equal to r;

performing a base r operation on the r groups of transformation results;

and the second transformation process comprises: multiplying by 1/N and then performing conjugation, or performing conjugation and then multiplying by 1/N.

In other embodiments of the present invention, the FFT/IFFT transformation, the radix r operation, and the multiplication by 1/N can all be performed by a block floating point method. For specific details, reference may be made to the description above and to the details not described herein.

Based on the second principle, the embodiment of the present invention additionally provides an FFT/IFFT transformation apparatus to implement forward and backward transformation of six transformation points, and the forward and backward transformation is mainly implemented by IFFT and radix r operation.

The FFT/IFFT transformation apparatus provided in the embodiment of the present invention is the same as the FFT/IFFT transformation apparatus shown in fig. 1, and the connection relationship between the devices is the same, and the difference is mainly in the base r operation unit portion and the first conjugate processing unit portion.

For convenience, this embodiment only describes the devices with changed functions, and the devices with unchanged functions are not described or taken along:

the input control unit 5 is configured to perform the following operations:

1) receiving configuration data and a first sequence;

the sequence to be transformed can be referred to as the first sequence, denoted as p (m), m being 0,1,2.

p (m) and the configuration data are the same as those described in the previous embodiments and are not described herein.

2) If N is not greater than 512, p (m) is directly input to the 512-point FFT/IFFT processing unit 4.

3) If N is greater than 512 and the conversion flag is the second value, the p (m) is input to the input ping-pong buffer unit 1.

4) When N is greater than 512 and the conversion flag is a first value, the p (m) is input to the first conjugate processing unit 2, and the first conjugate processing unit 2 performs conjugation processing to obtain a conjugation sequence p of p (m)^*(m), and p^*(m) output to the input ping-pong buffer unit 1.

P is above^*(m) is x in the introduction of the second principle^*(n)。

5) Above is atWhen N is greater than 512, reading out p (m) or p from the input ping-pong buffer unit 1 r times^*(m) is sent to the 512-point FFT/IFFT processing unit 4.

Where r is N/512, the data read out from the input ping-pong buffer unit 1 by the input control unit 5 the ith time is: p (m) or p^*And (m) 512 point data at the position where the positive integer of r is multiplied by r-i, wherein i is more than or equal to 1 and less than or equal to r. For details, please refer to the above description, which is not repeated herein.

The 512-point FFT/IFFT processing unit 4 is configured to:

1) if N is not greater than 512, performing corresponding FFT/IFFT on the input data, and outputting a transformation result to an output end 6;

2) if N is larger than 512, the input control unit is divided into r times of input p (m)/p^*The 512-point data at the position where r is the positive integer multiple minus r-i in (m) is subjected to 512-point IFFT r times to obtain r sets of transform results, and the r sets of transform results are sent to the base r arithmetic unit 7.

Wherein r is N/512, and i is more than or equal to 1 and less than or equal to r.

For the related content of the 512-point FFT/IFFT processing unit 4, please refer to the above description, which is not repeated herein.

The base r arithmetic unit 7 is configured to:

1) when N is greater than 512 and the transformation flag is the second value, the r groups of transformation results are subjected to the base r operation, the obtained operation results form a third sequence Y (m), and the third sequence Y (m) is output to the output terminal 6. The third sequence Y (m) is a sequence X (n) obtained by inverse transformation of the first sequence p (m) (i.e., the aforementioned X (k)).

2) When N is greater than 512 and the transform flag is the first value, the operation result obtained by performing a base r operation on the input data forms a fourth sequence yy (m), the fifth sequence y (m) is obtained by multiplying y (m) by 512, and the fifth sequence y (m) is output to the second conjugation processing unit 3, and the sixth sequence y (m) obtained by performing conjugation processing by the second conjugation processing unit 3 is the frequency domain signal X (k).

Further, in another embodiment of the present invention, referring to fig. 4, the radix operation unit 7 may include a write control unit 31, first to fourth ping-pong buffer units (32, 33, 34, 35), a twiddle factor first storage unit 36, a twiddle factor second storage unit 37, a twiddle factor third storage unit 38, a read control unit 39, a first twiddle factor read control unit 40, a first multiplexer MUX1, a second multiplexer MUX2, a twiddle factor multiplication unit 41, a block floating point processing unit 42, first to third complex multiplication units (43, 44, 45), first to third complex addition units (46, 47, 48), a third conjugation processing unit, and a fourth conjugation processing unit.

The components included in the base r arithmetic unit 7 shown in fig. 4 are basically the same as those shown in fig. 2, and the connection relationship between the components is also basically the same, but some components not shown in fig. 2 are added.

Wherein: in fig. 4, the write control unit 31, the first to fourth ping-pong buffer units (32, 33, 34, 35), the twiddle factor first storage unit 36, the twiddle factor second storage unit 37, the twiddle factor third storage unit 38, the read control unit 39, the first twiddle factor read control unit 40, the first multiplexer MUX1, the first to third complex addition units (46, 47, 48), and the first to second complex multiplication units (43, 44) have the same functions as those described above, and the functions thereof are as described above, and are not repeated herein.

Third and fourth conjugation processing units in fig. 4 for conjugating the data (first and second twiddle factors, respectively) inputted thereto and outputting the processing result to twiddle factor multiplying unit 41.

The twiddle factor multiplication unit 41 in fig. 4 differs from the twiddle factor multiplication unit 41 in fig. 2 as follows:

when N is 1024, H is 0, and data at the 512(j-1) +1 to 512j positions in Y (m) or Y (m) is calculated

When N is 1536, the data at the 512(j-1) +1 to 512j positions in Y (m) or Y x (m) is calculated

2048 for N, when calculating data at 512(j-1) + 1-512 j positions in Y (m) or Y x (m)1≤j≤r。

Block floating point processing unit 42 in fig. 4: the device is used for carrying out block floating point processing on the input r groups of transformation results and sending the processing results to the first complex multiplication unit and the first and second complex addition units.

The block floating point processing unit 42 in fig. 4 is substantially the same as the block floating point processing unit 42 in fig. 2, and the differences are emphasized here, and the same parts as the blk _ exp2 and the blk _ exp3 described below refer to the foregoing description, and are not repeated here.

When performing 1024, 1536, and 2048-point FFT transforms, the final block floating point factor blk _ exp3 is equal to the sum of blk _ exp2 and 9.

When performing 1024, 1536, and 2048-point IFFT transforms, the final block floating point factor blk _ exp3 is equal to blk _ exp 2.

A second multiplexer MUX2 for sending a 1 to the third complex multiplication unit when the transform flag is the first value (positive transform); when N is 1024, 1536, or 2048 and the transform flag is the second value (inverse transform), 1/2, 1/3, 1/4 is sent to the third complex multiplication unit 45, respectively.

In other embodiments of the present invention, when N is 1024 and the transform flag is the second value (inverse transform), blk _ exp2 may be further subtracted from 1 to obtain blk _ exp3, so that 1 is not sent to the third complex multiplication unit 45 but 1 is sent to 1; similarly, when N is 2048 and the transform flag is the second value (inverse transform), blk _ exp2 and 2 may be further subtracted to obtain blk _ exp3, so that 1/4 is not sent to the third complex multiplication unit 45.

Third complex multiplication unit 45: a Multiplexer (MUX) 3(MUX3 is the aforementioned output terminal 6) for complex-multiplying the output data of the second multiplexer MUX2 with the third complex addition result output by the third complex addition unit 48 to obtain a fourth complex multiplication result, and when N is 1024, 1536, or 2048 and the transformation flag is the second value, sending the fourth complex multiplication result to the third multiplexer MUX 3; when N is 1024, 1536, or 2048, and the transform flag is the first value, the fourth complex multiplication result is sent to the second conjugation processing unit 3.

A third multiplexer MUX3, for selecting the output result, and outputting the output result of the 512-point FFT/IFFT processing unit when N is 128, 256 or 512; when N is 1024, 1536, or 2048 and the transform flag is the second value, outputting the fourth complex multiplication result of the third complex multiplication unit 45; and when the N is 1024, 1536 or 2048 and the transformation flag is the first value, outputting the output result of the second conjugation processing unit.

Corresponding to the two principles, the embodiment of the present invention further claims an FFT/IFFT transformation method, please refer to fig. 5a or fig. 5b, which at least includes the following steps:

s61: receiving a first sequence p (m); n-1, where N denotes the number of transform points and the sequence length.

The first sequence is transformed into a forward transform or a reverse transform;

s62: directly carrying out corresponding FFT/IFFT on a first sequence p (m) of which N is not more than 512;

s63: performing first transformation processing on a first sequence p (m) to be subjected to inverse transformation, wherein N is greater than 512 points;

s64: the first sequence p (m) with N larger than 512 points and to be subjected to forward transformation is subjected to conjugation processing to obtain a second sequence p^*(m) toSecond sequence p^*(m) performing a first transformation process, and performing a second transformation process on the sequence obtained after the first transformation process.

The first conversion process includes:

for p (m) or p^*(m) performing 512-point IFFT r times to obtain r groups of transformation results, wherein the 512-point IFFT i time comprises p (m) or p^*(m) performing IFFT with 512 point data located at a positive integer multiple of r minus r-i; the 512 point data in the ith group of transformation results is p (m) or p^*(m) the transform result of IFFT of 512 points located at the position where r is a positive integer multiplied by r-i; r is N/512, i is more than or equal to 1 and less than or equal to r;

performing a base r operation on the r groups of transformation results;

and the second transformation process includes: multiplying 512 and then performing conjugation, or, performing conjugation and then multiplying 512.

In other embodiments of the present invention, the FFT/IFFT transformation, the radix r operation, and the multiplying by 512 may all be performed in a block floating point manner.

For specific details, reference may be made to the foregoing description herein and details will not be described herein.

It can be seen that in all the above embodiments of the present invention, the six transformation points defined by the LTE system are divided into two categories:

the smaller transform points (128, 256, 512, i.e. N is not greater than 512) are all integer powers of 2, and the corresponding FFT/IFFT transform is performed directly. Because the FFT/IFFT implementation technology of the integral power of 2 is very mature, for example, the method can directly call IP provided by an FPGA manufacturer or implement by applying a mature implementation framework;

the larger transform point numbers (1024, 1536, 2048, that is, N is greater than 512) are all realized based on 512-point FFT or IFFT and a radix r operation unit, the structure is simple, and the required multiplier and adder resources are few.

In addition, only 512 first twiddle factors are needed to be stored during 1024-point and 1536-point transformation respectively, 1024 first twiddle factors are needed during 2048-point transformation, 512 first twiddle factors can be shared with 1024 first twiddle factors, only 512 first twiddle factors need to be stored additionally, only 1536 twiddle factors need to be stored in total when three transformation points are executed, and the use of storage resources is saved.

When the IFFT is realized by the FFT or the FFT is realized by the IFFT, the input and the output are respectively conjugated, and the intermediate calculation processes are all FFT or IFFT processing, thereby simplifying the realization mode.

The use of the block floating point processing unit and the 512-point FFT/IFFT processing unit enables the six bandwidths required by the LTE system to be performed with block floating point FFT/IFFT.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.

The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.

Claims (8)

1. An FFT/IFFT conversion device based on LTE is characterized by comprising an input ping-pong buffer unit, a first conjugate processing unit, a 512-point FFT/IFFT processing unit, an input control unit, a radix r operation unit, a second conjugate processing unit and an output end;

wherein the input control unit is configured to:

receiving configuration data and a first sequence p (m), m being 0,1,2.. N-1, N representing the number of transform points or the length of the sequence; the configuration data comprises at least N and a transformation flag; the first value of the transformation mark is used for representing that the first sequence needs to be subjected to forward transformation, and the second value of the transformation mark is used for representing that the first sequence needs to be subjected to inverse transformation;

when the N is not more than 512, directly inputting the first sequence p (m) to the 512-point FFT/IFFT processing unit;

when the N is larger than 512 and the transformation flag is a first value, inputting the first sequence p (m) into the input ping-pong buffer unit;

when the N is larger than 512 and the transformation flag is a second value, the first sequence p (m) is input to the first conjugate processing unit, and the first conjugate processing unit performs conjugation processing to obtain a second sequence p^*(m) and outputting to the input ping-pong buffer unit;

when the N is larger than 512, reading out p (m) or p from the input ping-pong buffer unit r times^*(m) sending to the 512-point FFT/IFFT processing unit; r is N/512; the data read out from the input ping-pong buffer unit at the ith time are as follows: p (m) or p^*(m) 512 point data located at the position where the positive integer of r is multiplied by r-i, wherein i is more than or equal to 1 and less than or equal to r;

the 512-point FFT/IFFT processing unit is used for executing FFT/IFFT conversion with the number of the transform points being 2 to the nth power, n is more than or equal to 1 and less than or equal to 9, wherein:

when the N is not more than 512, performing corresponding FFT/IFFT transformation on the input data according to the transformation mark, and outputting a transformation result to the output end; or,

when the N is larger than 512, performing r times of FFT (fast Fourier transform) on data input by the input control unit for r times to obtain r groups of transform results, and sending the r groups of transform results to the radix r operation unit; wherein the 512 point data in the ith group of transformation results is p (m) or p^*(m) the transform result of FFT transform of 512 point data located at the position where r is a positive integer multiple minus r-i;

the base r operation unit is configured to:

when the N is larger than 512 and the transformation flag is a first value, performing a base r operation on the r group transformation results to obtain a third sequence Y (m), and outputting the third sequence Y (m) to the output end, wherein the third sequence Y (m) is a sequence obtained by performing forward transformation on the first sequence p (m); or,

when the N is larger than 512 and the transformation mark is a second value, carrying out primary r operation on the r groups of transformation results to obtain a fourth sequence yy^*(m) and mixing yy^*(m) multiplying by 1/N to obtain a fifth sequence y^*(m) adding said y^*(m) output to the second conjugation processing unit;

the second conjugation processing unit is configured to perform conjugation processing on input data to obtain a sixth sequence y (m), and output the sixth sequence y (m) to the output end, where the sixth sequence y (m) is a sequence obtained by performing inverse transformation on the first sequence p (m);

the FFT/IFFT transformation, the radix r operation and the multiplication by 1/N are operated in a block floating point mode; the block floating point mode represents data by using block floating point factors and mantissas, and the block floating point factors of 512 point data in the ith group of transformation results are the same;

the output end is a third multiplexer;

the radix-r operation unit comprises a write control unit, a first ping-pong cache unit, a second ping-pong cache unit, a first twiddle factor storage unit, a second twiddle factor storage unit, a third twiddle factor storage unit, a read control unit, a first twiddle factor read control unit, a first multiplexer, a twiddle factor multiplication unit, a block floating point processing unit, a first complex multiplication unit, a second complex multiplication unit, a third complex multiplication unit, a first complex addition unit, a third complex addition unit and a second multiplexer, wherein:

the write control unit is to: the ith group of conversion results in the r groups of conversion results are output to the ith ping-pong cache unit in the first to fourth ping-pong cache units, and i is more than or equal to 1 and less than or equal to r;

the twiddle factor first storage unit is used for storing 512 first twiddle factors

The second storage unit for storing 512 first twiddle factors

The third storage unit of twiddle factors is used for storing 512 first twiddle factors

The read control unit is to: the read instruction is sent to the same address space of the first ping-pong cache unit to the r ping-pong cache unit r times to read the r group conversion result, the read r group conversion result is sent to the block floating point processing unit, and the time when the first twiddle factor read control unit reads the first twiddle factor each time is controlled; r sets of transform results read out in the j-th read for calculating Y (m) or Y^*(m) data at the 512(j-1) + 1-512 j position, wherein j is more than or equal to 1 and less than or equal to r;

the first twiddle factor read control unit is to: controlling the reading of the first twiddle factor in the twiddle factor first storage unit, the twiddle factor second storage unit and the twiddle factor third storage unit, and outputting the read first twiddle factor to the twiddle factor multiplying unit;

the first multiplexer is used for selecting one second twiddle factor from a plurality of second twiddle factors and outputting the second twiddle factor to the twiddle factor multiplying unit; the second twiddle factor comprises W₂ ⁰、W₂ ¹、W₃ ⁰、W₃ ¹、W₃ ²、W₄ ⁰、W₄ ¹、W₄ ²、W₄ ³、W₂ ²And W₂ ³；

The twiddle factor multiplying unit is used for carrying out complex multiplication operation on the first twiddle factor and the second twiddle factor to obtain a first calculation result G and a second calculation result H, and respectively outputting the first calculation result G and the second calculation result H to the first complex multiplying unit and the second complex multiplying unit;

a block floating point processing unit: the device comprises a first complex multiplication unit, a first complex addition unit, a second complex addition unit and a first and second complex addition units, wherein the first complex multiplication unit is used for performing block floating point processing on the input r groups of conversion results to obtain r groups of processing results, and the r groups of processing results are sent to the first complex multiplication unit and the first and second complex addition units; when N is 1024, the first output end of the block floating point processing unit outputs a first group of processing results, the fourth output end outputs a second group of processing results, and the second output end and the third output end output 0; when N is 1536, the second output terminal of the block floating point processing unit outputs 0, and the first output terminal, the third output terminal, and the fourth output terminal respectively output the first to third groups of processing results; when N is 2048, the first to fourth output ends of the block floating point processing unit respectively output a first to fourth set of processing results;

the first complex multiplication unit is configured to perform complex multiplication on the first calculation result G output by the twiddle factor multiplication unit and the processing results output by the second output end and the fourth output end of the block floating point processing unit, respectively, to obtain a first complex multiplication result and a second complex multiplication result, send the first complex multiplication result to the first complex addition unit, and send the second complex multiplication result to the second complex addition unit;

the first complex addition unit is configured to perform complex addition on the processing result output by the first output end of the block floating point processing unit and the first complex multiplication result output by the first complex multiplication unit to obtain a first complex addition result, and send the first complex addition result to the third complex addition unit;

the second complex addition unit is configured to perform complex addition on the processing result output by the third output terminal of the block floating point processing unit and the second complex multiplication result output by the first complex multiplication unit to obtain a second complex addition result, and send the second complex addition result to the second complex multiplication unit;

the second complex multiplication unit is configured to complex-multiply the second complex addition result output by the second complex addition unit with the second calculation result H output by the twiddle factor multiplication unit to obtain a third complex multiplication result, and send the third complex multiplication result to the third complex addition unit;

the third complex addition unit is configured to perform complex addition on the first complex addition result output by the first complex addition unit and the third complex multiplication result output by the second complex multiplication unit to obtain a third complex addition result, and send the third complex addition result to the third complex multiplication unit;

the second multiplexer is configured to send 1 to the third complex multiplication unit when N is 1024, 1536, or 2048 and a transform flag is a first value; when N is 1536 and the transformation flag is the second value, sending 1/3 to the third complex multiplication unit; when N is 1024 or 2048 and a transform flag is a second value, sending 1 to the third complex multiplication unit;

the third complex multiplication unit is configured to complex-multiply the output data of the second multiplexer with a third complex addition result output by the third complex addition unit to obtain a fourth complex multiplication result, and when N is 1024, 1536, or 2048 and a transform flag is a first value, send the fourth complex multiplication result to the third multiplexer; when N is 1024, 1536, or 2048 and a transform flag is a second value, sending a fourth complex multiplication result to the second conjugation processing unit;

the second conjugation processing unit is used for performing conjugation processing on input data and outputting the conjugated data to the third multiplexer;

the third multiplexer is used for outputting the output result of the 512-point FFT/IFFT processing unit when N is 128, 256 or 512; when N is 1024, 1536 or 2048 and the transformation flag is the first value, outputting the output result of the third complex multiplication unit; and when the N is 1024, 1536 or 2048 and the transformation flag is the second value, outputting the output result of the second conjugation processing unit.

2. The apparatus of claim 1, wherein in performing a radix r operation in block floating point mode, the radix r operation unit is to:

taking any one of the block floating point factors corresponding to the r groups of conversion results as a reference block floating point factor, and performing corresponding left shift or right shift on the conversion results corresponding to other block floating point factors so that each group of conversion results corresponds to the reference block floating point factor;

and under the fixed word length, adjusting the floating point factor of the reference block according to the difference of the conversion points.

3. The apparatus of claim 1, wherein the radix-r operation unit, in terms of multiplying by 1/N, is to:

when N is 1024 and the conversion mark is a second value, the difference between the reference block floating point factor and 10 is made to obtain a final block floating point factor;

when N is 1536 and the conversion mark is the second value, the difference is made between the reference block floating point factor and 9 to obtain a final block floating point factor, and each group of conversion results is multiplied by 1/3;

and when the N is 2048 and the conversion flag is the second value, subtracting the reference block floating point factor from 11 to obtain a final block floating point factor.

4. The apparatus of claim 1, wherein if N1024, H0, Y (m) or Y is being calculated^*(m) at the 512(j-1) + 1-512 j position

If N is 1536, then Y (m) or Y is calculated^*At 512(j-1) -512 j positions in (m)

If N is 2048, then Y (m) or Y is calculated^*(m) at the 512(j-1) + 1-512 j position,

5. an FFT/IFFT conversion device based on LTE is characterized by comprising an input ping-pong buffer unit, a first conjugate processing unit, a 512-point FFT/IFFT processing unit, an input control unit, a radix r operation unit, a second conjugate processing unit and an output end;

wherein the input control unit is configured to:

receiving configuration data and a first sequence p (m), m being 0,1,2.. N-1, N representing the number of transform points or the length of the sequence; the configuration data comprises at least N and a transformation flag; the first value of the transformation mark is used for representing that the first sequence needs to be subjected to forward transformation, and the second value of the transformation mark is used for representing that the first sequence needs to be subjected to inverse transformation;

when the N is not more than 512, directly inputting the first sequence p (m) to the 512-point FFT/IFFT processing unit;

when the N is larger than 512 and the transformation flag is a second value, inputting the first sequence p (m) into the input ping-pong buffer unit;

when the N is larger than 512 and the transformation flag is a first value, inputting the first sequence p (m) to the first conjugate processing unit, and performing conjugate processing by the first conjugate processing unit to obtain a second sequence p^*(m) and outputting to the input ping-pong buffer unit;

when the N is larger than 512, reading out p (m) or p from the input ping-pong buffer unit r times^*(m) sending to the 512-point FFT/IFFT processing unit; r is N/512; the data read out from the input ping-pong buffer unit at the ith time are as follows: p (m) or p^*(m) 512 point data located at the position where the positive integer of r is multiplied by r-i, wherein i is more than or equal to 1 and less than or equal to r;

the 512-point FFT/IFFT processing unit is used for executing FFT/IFFT conversion with the number of the transform points being 2 to the nth power, n is more than or equal to 1 and less than or equal to 9, wherein:

when the N is not more than 512, performing corresponding FFT/IFFT transformation on the input data according to the transformation mark, and outputting a transformation result to the output end; or,

when the N is larger than 512, performing r-time IFFT transformation on data input by the input control unit for r times to obtain r groups of transformation results, and sending the r groups of transformation results to the base r operation unit; wherein the 512 point data in the ith group of transformation results is p (m) or p^*(m) a transform result of IFFT-transforming 512 point data located at a positive integer multiple-minus r-i position of r;

the base r operation unit is configured to:

when the N is larger than 512 and the transformation flag is a second value, performing a base r operation on the r groups of transformation results to obtain a third sequence Y (m), and outputting the third sequence Y (m) to the output end, wherein the third sequence Y (m) is a sequence obtained by performing inverse transformation on the first sequence p (m); or,

when the N is larger than 512 and the transformation mark is a first value, carrying out primary r operation on the r groups of transformation results to obtain a fourth sequence yy^*(m) and mixing yy^*(m) multiplying by 512 to obtain a fifth sequence y^*(m) adding said y^*(m) output to the second conjugation processing unit;

the second conjugation processing unit is configured to perform conjugation processing on input data to obtain a sixth sequence y (m), and output the sixth sequence y (m) to the output end, where the sixth sequence y (m) is a sequence obtained by performing forward transformation on the first sequence p (m);

the FFT/IFFT transformation, the radix r operation and the multiplication are carried out in a block floating point mode;

the block floating point mode represents data by block floating point factors and mantissas, and the 512-point data in the ith group of transformation results have the same block floating point factor.

6. The apparatus of claim 5, wherein the radix-r operation unit, in terms of multiplying by 512, is to:

and when the N is 1024, 1536 or 2048 and the transformation flag is the first value, adding the reference block floating point factor and 9 to obtain a final block floating point factor.

7. The apparatus of claim 6,

the output end is a third multiplexer;

the radix-r operation unit comprises a write control unit, a first ping-pong cache unit, a second ping-pong cache unit, a first twiddle factor storage unit, a second twiddle factor storage unit, a third twiddle factor storage unit, a read control unit, a first twiddle factor read control unit, a first multiplexer, a twiddle factor multiplication unit, a block floating point processing unit, a first complex multiplication unit, a second complex multiplication unit, a third complex multiplication unit, a first complex addition unit, a third complex addition unit, a second multiplexer, a third conjugate processing unit and a fourth conjugate processing unit, wherein:

the write control unit is to: the ith group of conversion results in the r groups of conversion results are output to the ith ping-pong cache unit in the first to fourth ping-pong cache units, and i is more than or equal to 1 and less than or equal to r;

the twiddle factor first storage unit is used for storing 512 first twiddle factors

The second storage unit for storing 512 first twiddle factors

The third storage unit of twiddle factors is used for storing 512 first twiddle factors

The read control unit is to: the read instructions are sent to the same address space of the first ping-pong cache unit to the r-th ping-pong cache unit r times to read the r groups of conversion results, the read r groups of conversion results are sent to the block floating point processing unit, and the moment when the first twiddle factor read control unit reads the first twiddle factor each time is controlled; r sets of transform results read out in the j-th read for calculating Y (m) or Y^*(m) data at 512(j-1) + 1-512 j positions，1≤j≤r；

The first twiddle factor read control unit is to: controlling the reading of the first twiddle factor in the twiddle factor first storage unit, the twiddle factor second storage unit and the twiddle factor third storage unit, and outputting the read first twiddle factor to the third conjugation processing unit;

the third conjugation processing unit is configured to perform conjugation processing on the input first twiddle factor to obtain a first twiddle factor subjected to conjugation processing, and output the first twiddle factor subjected to conjugation processing to the twiddle factor multiplication unit;

the first multiplexer is configured to select one second twiddle factor from a plurality of second twiddle factors and output the second twiddle factor to the fourth conjugate processing unit; the second twiddle factor comprises W₂ ⁰、W₂ ¹、W₃ ⁰、W₃ ¹、W₃ ²、W₄ ⁰、W₄ ¹、W₄ ²、W₄ ³、W₂ ²And W₂ ³；

The fourth conjugation processing unit is configured to perform conjugation processing on the input second twiddle factor to obtain a second twiddle factor subjected to conjugation processing, and output the second twiddle factor subjected to conjugation processing to the twiddle factor multiplication unit;

the twiddle factor multiplying unit is used for carrying out complex multiplication operation on the first twiddle factor subjected to conjugation processing and the second twiddle factor subjected to conjugation processing to obtain a first calculation result G and a second calculation result H, and respectively outputting the first calculation result G and the second calculation result H to the first complex multiplying unit and the second complex multiplying unit;

a block floating point processing unit: the device comprises a first complex multiplication unit, a first complex addition unit, a second complex addition unit and a first and second complex addition units, wherein the first complex multiplication unit is used for performing block floating point processing on the input r groups of conversion results to obtain r groups of processing results, and the r groups of processing results are sent to the first complex multiplication unit and the first and second complex addition units; when N is 1024, the first set of processing results output by the first output terminal of the block floating point processing unit, the second set of processing results output by the fourth output terminal, and 0 is output by the second output terminal and the third output terminal; when N is 1536, the second output terminal of the block floating point processing unit outputs 0, and the first output terminal, the third output terminal, and the fourth output terminal respectively output the first to third groups of processing results; when N is 2048, the first to fourth output ends of the block floating point processing unit respectively output a first to fourth set of processing results;

the first complex multiplication unit is configured to perform complex multiplication on the first calculation result G output by the twiddle factor multiplication unit and the processing results output by the second output end and the fourth output end of the block floating point processing unit, respectively, to obtain a first complex multiplication result and a second complex multiplication result, send the first complex multiplication result to the first complex addition unit, and send the second complex multiplication result to the second complex addition unit;

the first complex addition unit is configured to perform complex addition on the processing result output by the first output end of the block floating point processing unit and the first complex multiplication result output by the first complex multiplication unit to obtain a first complex addition result, and send the first complex addition result to the third complex addition unit;

the second complex addition unit is configured to perform complex addition on the processing result output by the third output terminal of the block floating point processing unit and the second complex multiplication result output by the first complex multiplication unit to obtain a second complex addition result, and send the second complex addition result to the second complex multiplication unit;

the second complex multiplication unit is configured to complex-multiply the second complex addition result output by the second complex addition unit with the second calculation result H output by the twiddle factor multiplication unit to obtain a third complex multiplication result, and send the third complex multiplication result to the third complex addition unit;

the third complex addition unit is configured to perform complex addition on the first complex addition result output by the first complex addition unit and the third complex multiplication result output by the second complex multiplication unit to obtain a third complex addition result, and send the third complex addition result to the third complex multiplication unit;

the second multiplexer is configured to send 1 to the third complex multiplication unit when the transform flag is the first value; when N is 1024, 1536, or 2048 and the transform flag is the second value, 1/2, 1/3, 1/4 is sent to the third complex multiplication unit, respectively, or,

when the transformation flag is a first value, sending 1 to the third complex multiplication unit; when N is 1024 or 2048 and a transform flag is a second value, sending 1 to the third complex multiplication unit; when N is 1536 and the transformation flag is the second value, sending 1/3 to the third complex multiplication unit;

the third complex multiplication unit is configured to complex-multiply the output data of the second multiplexer with a third complex addition result output by the third complex addition unit to obtain a fourth complex multiplication result, and when N is 1024, 1536, or 2048 and a transform flag is a second value, send the fourth complex multiplication result to the third multiplexer; when N is 1024, 1536, or 2048 and a transform flag is a first value, sending a fourth complex multiplication result to the second conjugation processing unit;

the second conjugation processing unit is used for performing conjugation processing on input data and outputting the conjugated data to the third multiplexer;

the third multiplexer is used for outputting the output result of the 512-point FFT/IFFT processing unit when N is 128, 256 or 512; when N is 1024, 1536 or 2048 and a transformation flag is a second value, outputting a fourth complex multiplication result of the third complex multiplication unit; and when N is 1024, 1536 or 2048 and a transformation flag is a first value, outputting an output result of the second conjugation processing unit.

8. An FFT/IFFT transform method based on LTE is characterized by comprising the following steps:

receiving a first sequence p (m); n-1, N representing the number of transform points or the length of a sequence, the first sequence being intended to be transformed into a forward transform or an inverse transform;

directly carrying out corresponding FFT/IFFT transformation on the first sequence p (m) with N not more than 512;

performing first transformation processing on a first sequence p (m) to be subjected to inverse transformation, wherein N is greater than 512 points;

the first sequence p (m) with N larger than 512 points and to be subjected to forward transformation is subjected to conjugation processing to obtain a second sequence p^*(m) for the second sequence p^*(m) performing the first transform process, and performing a second transform process on the sequence obtained after the first transform process;

the first transform process includes:

for p (m) or p^*(m) carrying out 512-point IFFT for r times to obtain r groups of transformation results, wherein the ith 512-point IFFT comprises p (m) or p^*(m) performing IFFT on 512 point data located at a positive integer multiple of r minus r-i position; the 512 point data in the ith group of transformation results is p (m) or p^*(m) a transform result of IFFT transform of 512 points located at the position where r is a positive integer multiplied by r-i; r is N/512, i is more than or equal to 1 and less than or equal to r;

performing a base r operation on the r groups of transformation results;

the second transform process includes: multiplying by 512 and then performing conjugation treatment, or performing conjugation treatment and then multiplying by 512;

the 512-point FFT/IFFT transformation, the radix r operation and the multiplication by 512 are operated in a block floating point mode;

the block floating point mode represents data by block floating point factors and mantissas, and the 512-point data in the ith group of transformation results have the same block floating point factor.