CN105575820A - Square-plane pin-free packaging structure and packaging method thereof - Google Patents
Square-plane pin-free packaging structure and packaging method thereof Download PDFInfo
- Publication number
- CN105575820A CN105575820A CN201410541249.3A CN201410541249A CN105575820A CN 105575820 A CN105575820 A CN 105575820A CN 201410541249 A CN201410541249 A CN 201410541249A CN 105575820 A CN105575820 A CN 105575820A
- Authority
- CN
- China
- Prior art keywords
- conducting circuit
- pin
- chip
- pedestal
- packing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention relates to a square-plane pin-free packaging structure comprising a thin-film layer, a conductive layer, a chip, a packaging colloid, and a plurality of metal bumps. A plurality of through holes are formed in the thin-film layer; the pedestal of the conductive layer and all conductive lines are arranged on the thin-film layer without any connection; and all conductive lines are arranged in all through holes. The chip is fixedly arranged on the pedestal and is connected to all conductive lines electrically. The packaging colloid covers the conductive layer and the chip. All metal bumps are arranged in the through holes and one end of each metal bump is connected to the conductive line electrically and the other end protrudes from the through hole. Therefore, objective of pin shedding prevention and surface adhesive force enhancement can be achieved. In addition, the invention also provides a packaging method for a square-plane pin-free packaging structure.
Description
Technical field
The present invention, about a kind of encapsulating structure and method for packing thereof, refers to the encapsulating structure of a kind of square surface without pin and the method for packing of this structure especially.
Background technology
Along with science and technology is maked rapid progress, high-tech electronic industry is delivered rapidly and is variously comprised multi-functional, more humane electronic product, therefore, semiconductor package is contained in size reduction process also has and develops fast, such as four directions is without pin package (QuadFlatNon-leadPackage, or Wafer-level Chip Scale Package (WaferLevelChipSizePackage QFN), WLCSP), its object is except reducing component size, effectively can also reduce production cost, and obtain preferably electrical.
Existing QFN method for packing is that above for chip sheet processing procedure is arranged at lead frame, and is electrically connected to lead frame by many bonding wires, then forms packing colloid and completes QFN encapsulating structure with coated wire frame, chip and bonding wire.
Summary of the invention
The encapsulating structure that main purpose of the present invention is to provide a kind of square surface without pin and method for packing thereof, it not only can solve the problem that lead foot flies off, and more can strengthen the adhesion of surface mount technology (SurfaceMountTechnology).
In order to reach above-mentioned purpose, square surface provided by the present invention is without the method for packing of pin, and it comprises the following step:
One thin layer is provided;
There is provided a conductting layer in the surface of this thin layer;
Make this conductting layer form a pedestal and multiple conducting circuit through circuit layout means, and respectively this conducting circuit is adjacent to this pedestal and mutually not conducting;
One chip is provided and with fixing means, this chip is arranged at this pedestal;
Electric connection means are utilized to make this chip be electrically connected respectively this conducting circuit;
Form a packing colloid to cover this chip and each this conducting circuit;
Make this thin layer form multiple through hole through boring means, be exposed to respectively this through hole for each this conducting circuit; And
There is provided multiple metal coupling in each this through hole and be electrically connected respectively this conducting circuit respectively.
Wherein, laying one tool viscolloid is also included in this thin layer, in order to stick together this conductting layer.
Wherein, this fixing means is upper slice processing procedure (DieAttached).
Wherein, these electric connection means are bonding wire processing procedure (WireBonding).
Wherein, these boring means are laser drill processing procedure (LaserDrillHole).
Wherein, this packing colloid formed in mold pressing (Molding) mode.
In order to reach above-mentioned purpose, the square surface that the present invention separately provides is without the encapsulating structure of pin, it includes a thin layer, one conductting layer, one chip, one packing colloid and multiple metal coupling, wherein this thin layer has multiple through hole, this conductting layer is located at this thin layer and is had a pedestal and multiple conducting circuit, this pedestal is not mutually connected with each this conducting circuit, and respectively this conducting circuit is positioned at respectively this through hole, this chip is fixedly arranged on this pedestal and is electrically connected at respectively this conducting circuit, this packing colloid covers this conductting layer and this chip, respectively this metal coupling lays respectively at respectively in this through hole, respectively this metal coupling one end is electrically connected at respectively this conducting circuit, the other end protrudes from respectively this through hole.
Wherein also include at least one bonding wire, be electrically connected this chip and each this conducting circuit.
Wherein this thin layer is provided with colloid, this colloid this pedestal cemented and respectively this conducting circuit.
Thus, square surface of the present invention not only can solve without the encapsulating structure of pin and method for packing thereof the problem that lead foot flies off, and more can strengthen the adhesion of surface mount technology simultaneously.
Accompanying drawing explanation
Below by by cited embodiment, coordinate enclose graphic, describe technology contents of the present invention and feature in detail, wherein:
Fig. 1 is structural representation of the present invention.
Fig. 2 a to Fig. 2 g is the flow chart of square surface of the present invention without the method for packing of pin.
[symbol description]
10 encapsulating structures
20 thin layer 21 colloids
23 through holes
30 conductting layer 31 pedestals
33 conducting circuits
40 chips
50 packing colloids
60 metal couplings
70 bonding wires
F1 horizontal force F2 longitudinal force
Embodiment
For formation of the present invention can be understood further, feature and object thereof, be below for some embodiments of the present invention, and coordinate graphic being described in detail as follows, allow simultaneously and be familiar with this those skilled in the art and can specifically implement, but the following stated person, only to technology contents of the present invention and feature are described and the execution mode provided, all have commonly knowledge in field of the present invention, after understanding technology contents of the present invention and feature, with without prejudice under spirit of the present invention, the all simple modification of doing, the economization of replacement or component, all should belong to the category that the invention is intended to protect.
In order to describe structure of the present invention, feature and effect place in detail, hereby enumerate a preferred embodiment and coordinate following graphic explanation as after, wherein:
Refer to shown in Fig. 1, a kind of square surface of the present invention includes thin layer 20, conductting layer 30, chip 40, packing colloid 50 without the encapsulating structure 10 of pin, and multiple metal coupling 60.
This thin layer 20 is provided with colloid 21 and has multiple through hole 23 running through this thin layer 20 and this colloid 21.In this preferred embodiment of the present invention, this thin layer 20 not only as the aforementioned film being an one side and being provided with viscose, can also can be a kind of adhesive tape.
This conductting layer 30 is located at this thin layer 20 and is had a pedestal 31 and multiple conducting circuit 33, and this pedestal 31 is not mutually connected with each this conducting circuit 33, and respectively this conducting circuit 33 lays respectively at respectively this through hole 23.In present pre-ferred embodiments, this pedestal 31 and respectively this conducting circuit 33 are Copper Foil (Cufoil), this pedestal 31 is cemented on this colloid 21, and respectively the most area of this conducting circuit 33 is identical with this pedestal 31 cemented on this colloid 21, the area only having small part to be positioned at respectively this through hole 23 is not cemented by colloid 21 institute.
This chip 40 is fixedly arranged on this pedestal 21, and this chip 40 and each this conducting circuit 33 is electrically connected through a bonding wire 70.In this preferred embodiment of the present invention, the quantity of this bonding wire 70 is not limited to one, and its quantity can increase according to the demand of actual use, and such as, shown in Fig. 1, the quantity of this bonding wire 70 is two, and two bonding wires 70 are electrically connected at two conducting circuits 33 respectively.
This packing colloid 50 covers this conductting layer 30 and this chip 40, in order to protect this chip 40, respectively this conducting circuit 33 and each this bonding wire 70.
Respectively this metal coupling 60 lays respectively at respectively in this through hole 23, and respectively this metal coupling 60 one end is electrically connected at respectively this conducting circuit 33, and the other end protrudes from respectively this through hole 23.Thus, the signal of this chip 40 then can pass through respectively this bonding wire 70 and conducts to respectively this conducting circuit 33, and is thoroughly electrically connected at respectively this metal coupling 60 of respectively this conducting circuit 33 and externally exports.In addition, because of each this metal coupling 60 horizontal force F1 limit by each through hole 23 of this thin layer 20, again respectively the longitudinal force F2 of this metal coupling 60 fix by each this conducting circuit 33, therefore when the cubic encapsulating structure 10 without pin of the present invention is subject to each side's force, respectively this metal coupling 60 still firmly and securely can be fixed on each this conducting circuit 33 and can not to produce the problem that lead foot flies off, and this also can strengthen the adhesion of surface mount technology.
Refer to shown in Fig. 2 a-Fig. 2 g again, the square surface provided for this preferred embodiment of the present invention is without the method for packing of pin, and it comprises the following step:
Steps A: as shown in Figure 2 a, first in this conductting layer 30 of formation in the surface of this thin layer 20.In present pre-ferred embodiments, the surface of this thin layer 20 is equipped with the colloid 21 of tool stickiness, can make this conductting layer 30 easily and firmly stick together at this thin layer 20.
Step B: as shown in Figure 2 b, make this conductting layer 30 form this pedestal 31 and each this conducting circuit 33, and respectively this conducting circuit 33 is adjacent to this pedestal 31 and mutually not conducting through circuit layout means.In present pre-ferred embodiments, these circuit layout means utilize rerouting (Re-Distribution) technology to make this conductting layer 30 form predetermined each conducting circuit 33, be the redistribution layer (Re-DistributionLayer, RDL) alleged by industry.
Step C: as shown in Figure 2 c, utilizes a fixing means that this chip 40 is arranged at this pedestal 31, and wherein this fixing means is upper slice processing procedure (DieAttached).
Step D: as shown in Figure 2 d, electric connection means are utilized to make this chip 40 be electrically connected respectively this conducting circuit 33, wherein these electric connection means are bonding wire processing procedure (WireBonding), and utilize this bonding wire 70 to be used as this chip 40 and the electrical conductivity medium respectively between this conducting circuit 33.
Step e: as shown in Figure 2 e, this packing colloid 50 is covered this chip 40, respectively this conducting circuit 33 and this bonding wire 70, wherein this packing colloid 50 formed in mold pressing (Molding) mode, make this chip 40 break in order to reduce external factor, respectively this conducting circuit 33 open circuit or short circuit, or the problem such as this bonding wire 70 fracture.
Step F: as shown in figure 2f, makes this thin layer 20 form multiple through hole 23 through boring means, and be exposed to respectively this through hole 23 for each this conducting circuit 33, wherein these boring means are laser drill processing procedure (LaserDrillHole).
Step G: as shown in Figure 2 g, there is provided multiple metal coupling 60 in each this through hole 23 and be electrically connected respectively this conducting circuit 33 respectively, it is worth mentioning that at this, respectively this metal coupling 60 is formed at respectively this through hole 23 for planting ball (BallMounting) mode, in order to promote the quality and efficiency of producing.
In sum, square surface of the present invention is simple and can reduce effect of packaging cost compared to having structure prior art without the encapsulating structure 10 of pin and square dress method thereof, the more important thing is, encapsulating structure 10 of the present invention because of each this metal coupling 60 by each this through hole 23 and respectively this conducting circuit 33 in structural restriction, and effectively can reduce horizontal force F1 and longitudinal force F2 to the impact of this encapsulating structure 10, make this encapsulating structure 10 when being subject to each side's force, respectively this metal coupling 60 still firmly and securely can be fixed on each this conducting circuit 33 and can not to produce the problem that lead foot flies off, and this also can strengthen the adhesion of surface mount technology, to reach object of the present invention.
The composed component that the present invention is disclosed in front exposure embodiment, is only and illustrates, be not used for limiting the scope of this case, substituting or change of other equivalence elements, the claim that also should be this case contained.
Claims (9)
1. square surface is without a method for packing for pin, and it comprises the following step:
One thin layer is provided;
There is provided a conductting layer in the surface of this thin layer;
Make this conductting layer form a pedestal and multiple conducting circuit through circuit layout means, and respectively this conducting circuit is adjacent to this pedestal and mutually not conducting;
One chip is provided and with fixing means, this chip is arranged at this pedestal;
Electric connection means are utilized to make this chip be electrically connected respectively this conducting circuit;
Form a packing colloid to cover this chip and each this conducting circuit;
Make this thin layer form multiple through hole through boring means, be exposed to respectively this through hole for each this conducting circuit; And
There is provided multiple metal coupling in each this through hole and be electrically connected respectively this conducting circuit respectively.
2. square surface according to claim 1 is without the method for packing of pin, it is characterized in that, also includes laying one tool viscolloid in this thin layer, in order to stick together this conductting layer.
3. square surface according to claim 1 is without the method for packing of pin, it is characterized in that, this fixing means is upper slice processing procedure.
4. square surface according to claim 1 is without the method for packing of pin, it is characterized in that, these electric connection means are bonding wire processing procedure.
5. square surface according to claim 1 is without the method for packing of pin, it is characterized in that, these boring means are laser drill processing procedure.
6. square surface according to claim 1 is without the method for packing of pin, it is characterized in that, this packing colloid formed with press moulding mode.
7. square surface is without an encapsulating structure for pin, it is characterized in that including:
One thin layer, has multiple through hole;
One conductting layer, has a pedestal and multiple conducting circuit, and this pedestal and respectively this conducting circuit are located at this thin layer respectively and are not mutually connected, and respectively this conducting circuit is positioned at respectively this through hole;
One chip, is fixedly arranged on this pedestal and is electrically connected at respectively this conducting circuit;
One packing colloid, covers this conductting layer and this chip; And
Multiple metal coupling, lay respectively at respectively in this through hole, respectively this metal coupling one end is electrically connected at respectively this conducting circuit, and the other end protrudes from respectively this through hole.
8. square surface as claimed in claim 7 is without the encapsulating structure of pin, it is characterized in that, also includes at least one bonding wire, is electrically connected this chip and each this conducting circuit.
9. square surface as claimed in claim 7 is without the encapsulating structure of pin, and it is characterized in that, this thin layer is provided with colloid, this colloid this pedestal cemented and respectively this conducting circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410541249.3A CN105575820A (en) | 2014-10-14 | 2014-10-14 | Square-plane pin-free packaging structure and packaging method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410541249.3A CN105575820A (en) | 2014-10-14 | 2014-10-14 | Square-plane pin-free packaging structure and packaging method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105575820A true CN105575820A (en) | 2016-05-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410541249.3A Pending CN105575820A (en) | 2014-10-14 | 2014-10-14 | Square-plane pin-free packaging structure and packaging method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105575820A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008042063A (en) * | 2006-08-09 | 2008-02-21 | Renesas Technology Corp | Semiconductor device |
| CN101131979A (en) * | 2006-08-22 | 2008-02-27 | 南茂科技股份有限公司 | Non-exterior pin semiconductor packaging construction plated in sealing glue and method of manufacturing the same |
| CN101186792A (en) * | 2006-11-24 | 2008-05-28 | 日东电工株式会社 | Heat-resistant adhesive tape for manufacturing semiconductor device |
| CN101308832A (en) * | 2007-05-17 | 2008-11-19 | 南茂科技股份有限公司 | Lead frame for leadless encapsulation, encapsulation construction and manufacture method thereof |
-
2014
- 2014-10-14 CN CN201410541249.3A patent/CN105575820A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008042063A (en) * | 2006-08-09 | 2008-02-21 | Renesas Technology Corp | Semiconductor device |
| CN101131979A (en) * | 2006-08-22 | 2008-02-27 | 南茂科技股份有限公司 | Non-exterior pin semiconductor packaging construction plated in sealing glue and method of manufacturing the same |
| CN101186792A (en) * | 2006-11-24 | 2008-05-28 | 日东电工株式会社 | Heat-resistant adhesive tape for manufacturing semiconductor device |
| CN101308832A (en) * | 2007-05-17 | 2008-11-19 | 南茂科技股份有限公司 | Lead frame for leadless encapsulation, encapsulation construction and manufacture method thereof |
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| PB01 | Publication | ||
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| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160511 |
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| WD01 | Invention patent application deemed withdrawn after publication |