CN105573812A - Simulation system - Google Patents

Abstract

The invention discloses a simulation system, which comprises a processor chip simulator and an integrated development environment installed on a computer, wherein the processor chip simulator comprises a simulation chip, a management module and an SRAM (Static Random Access Memory); after the simulator is electrified, the management module controls the simulation chip to enter a reset state through control signals; the management module writes the model and version information of the simulation chip into the SRAM through a standard data/address bus; after the writing completion, the simulation chip is controlled to exit the reset state through control signals; a user sends out data region reading instruction to the simulation chip through a communication interface on the integrated development environment; the simulation chip reads data from the SRAM, and returns the read data region data value to the integrated development environment; and the integrated development environment displays data in a data storage device observing window. The simulation system has the advantage that on the premise that the complexity and the workload of a system structure are not increased, the requirement that customers can conveniently and intuitively obtain the model and the version information of the simulation chip is met.

Description

A kind of analogue system

Technical field

The present invention relates to emulator field, particularly relate to a kind of processor chips analogue system.

Background technology

Have the user program of User Exploitation in processor chips, in the writing and debug of user program, the instrument used is generally processor chips emulator.The emulation chip comprising product treatment device chip various functions is used in emulator, for the work behavior of analog equipment chip processor, emulation chip and emulator miscellaneous part (deposit the program storage of user program, the data-carrier store of store data, and the Integrated Development Environment etc. on user computer) coordinate and realize the simulation run of user program and every debug function.

Because the memory characteristics of the same family chip product of chip manufacturer and size may be different, consider mainly to pay close attention to function debugging when using emulator debug user program simultaneously, the performance of storer is close, and the existing emulator for same family chip is same emulator systems normally.Usually SRAM (StaticRandomAccessMemory is adopted in emulator, static RAM) carry out the XRAM (on-chipexpandedRandomAccessMemory being used as data-carrier store in equivalent substitution product chips, expansion static RAM in sheet), when writing, reading data, functional performance is all equivalent.

Due to the normally same emulator systems of the emulator for same family chip, so user has, directly perceived what understand the simulation of existing emulator is the demand of which version chip of which model.In order to meet this demand, need in existing emulator additionally to increase model and the version that a block part deposits institute's emulation chip, need extra increase access path to read described model and version information for Integrated Development Environment, need to revise the module that general IDE increases the described model of display and version information.Add complexity and the workload of structure.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of analogue system, under the prerequisite of the complexity and workload that do not increase system architecture, meets the model of client convenient, directly perceived acquisition institute emulation chip and the demand of version information.

For solving the problems of the technologies described above, analogue system of the present invention, the Integrated Development Environment comprising processor chips emulator and install on computers; Described processor chips emulator, comprises emulation chip, administration module, SRAM memory;

Described emulation chip carries out read-write operation by normal data/address bus to SRAM memory, is received instruction by communication interface, returns response data from Integrated Development Environment; Described administration module carries out read-write operation by described normal data/address bus to SRAM memory;

After emulator powers on, described administration module enters reset mode by control signal control imitation chip, and administration module writes model and the version information of institute's emulation chip to SRAM memory by normal data/address bus; After having write, administration module exits reset mode by control signal control imitation chip; After emulation chip enters reset mode, not by described normal data/address bus operation SRAM memory, after emulation chip exits reset mode, emulation chip is by described normal data/address bus operation SRAM memory;

User sends reading data field (XDATA by communication interface to emulation chip in Integrated Development Environment, XRAM region on corresponding chip makes physical) instruction, emulation chip reads data from SRAM memory, return the Data Area data value that reads to Integrated Development Environment, Integrated Development Environment is presented at data in data-carrier store watch window.

Adopt emulator of the present invention, continue to use SRAM to substitute the XRAM of chip.In emulator, do not need extra increase to deposit the parts of institute's emulation chip model and version information, extra increase access path is not needed to read described model and version information for Integrated Development Environment, do not need to revise the module that general IDE increases the described model of display and version information, user directly can read model and the version information of emulator institute emulation chip after emulator powers on.Under the prerequisite of the complexity and workload that do not increase system architecture, meet the model of client convenient, directly perceived acquisition institute emulation chip and the demand of version information.Facilitate the exploitation of user program, debugging and test, reduce the complexity of emulator with development amount.

Accompanying drawing explanation

Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:

Accompanying drawing is described processor chips emulator structural representation.

Embodiment

As shown in the figure, described processor chips emulator 1, comprises emulation chip 2, administration module 3, SRAM memory 4, and the Integrated Development Environment 7 on computer.Described SRAM memory 4 is connected with emulation chip 2 and administration module 3 respectively by normal data/address bus 5, emulation chip 2 carries out communication by communication interface 8 and the Integrated Development Environment 7 on computer, and described administration module 3 is by control signal 6 and the described emulation chip 2 of control.

Emulation chip 2 carries out read-write operation by normal data/address bus 5 pairs of SRAM memory 4; Emulation chip 2 receives instruction by communication interface 8 from Integrated Development Environment 7 and returns response data.Administration module 3 carries out read-write operation by normal data/address bus 5 pairs of SRAM memory 4; Administration module 3 is entered by control signal 6 control imitation chip 2 or is exited reset mode.Administration module 3 can use general processor chip to realize.

After described processor chips emulator 1 powers on, administration module 3 enters reset mode by control signal 6 control imitation chip 2, and after entering reset mode, emulation chip 2 does not operate SRAM memory 4 by normal data/address bus 5.Administration module 3 by normal data/address bus 5 to the model of 0 address area write institute emulation chip of SRAM memory 4 and version information.After having write, administration module 3 exits reset mode by control signal 6 control imitation chip 2, and after emulation chip 2 exits reset mode, emulation chip 2 reads and writes SRAM memory 4 by normal data/address bus 5 by the mode in chip operation XDATA region.

Now, user can send reading data field (XDATA by communication interface 8 to emulation chip 2 in Integrated Development Environment 7, XRAM region on corresponding chip makes physical) instruction, such as open the watch window in the region that XDATA0 address starts, emulation chip 2 presses the corresponding region of mode from 0 address reading SRAM memory 4 in chip operation XDATA region, then emulation chip 2 returns the data value that reads to Integrated Development Environment 7, Integrated Development Environment 7 is presented at data in data-carrier store watch window, user just intuitively can arrive the model of emulator 1 emulation chip and version information.

Like this, after emulator powers on, user only needs the data field window opening Integrated Development Environment 7 just can observe model and the version information of emulator 1 emulation chip intuitively.Realizing in this function course, emulator and Integrated Development Environment do not increase extra parts, module, access path.In addition, lose because XRAM has power failure data, it is the feature of random data value after re-powering, although so emulator 1 after powering on described administration module 3 write model in the SRAM memory 4 of equivalent substitution XRAM and version information, these information datas also can be regarded as a kind of random data, emulator 1 can not be affected and emulate operation to XRAM, and the function of XRAM and characteristic.

The foregoing is only the specific embodiment of the present invention and embodiment, scope is not limited thereto.

Claims (1)

1. an analogue system, is characterized in that: the Integrated Development Environment comprising processor chips emulator and install on computers; Described processor chips emulator, comprises emulation chip, administration module, SRAM memory;

Described emulation chip carries out read-write operation by normal data/address bus to SRAM memory, is received instruction by communication interface, returns response data from Integrated Development Environment; Described administration module carries out read-write operation by described normal data/address bus to SRAM memory;

After emulator powers on, described administration module enters reset mode by control signal control imitation chip, and administration module writes model and the version information of institute's emulation chip to SRAM memory by normal data/address bus; After having write, administration module exits reset mode by control signal control imitation chip; After emulation chip enters reset mode, not by described normal data/address bus operation SRAM memory, after emulation chip exits reset mode, emulation chip is by described normal data/address bus operation SRAM memory;

User sends reading data field instruction by communication interface to emulation chip in Integrated Development Environment, emulation chip reads data from SRAM memory, return the Data Area data value that reads to Integrated Development Environment, Integrated Development Environment is presented at data in data-carrier store watch window.