CN105553470B - A kind of serializer based on half rate clock restoring circuit - Google Patents
A kind of serializer based on half rate clock restoring circuit Download PDFInfo
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- CN105553470B CN105553470B CN201610061974.XA CN201610061974A CN105553470B CN 105553470 B CN105553470 B CN 105553470B CN 201610061974 A CN201610061974 A CN 201610061974A CN 105553470 B CN105553470 B CN 105553470B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
A kind of serializer based on half rate clock restoring circuit, the present invention relates to signal conversion arts, it aims to solve the problem that existing serializer mismatches there are clock generator different in identical serializer acquisition clock frequency and causes output data error larger, exist simultaneously logic circuit output level burr, the technical problems such as clock jitter and data distortion.The structure includes mainly the first clock generator：The first clock signal is exported, for building signal acquisition time window；First multiplex electronics：Its sampling clock port receives the first clock signal of the first clock generator output, and input terminal receives parallel source signal and output end exports mixed signal；Feedback clock generator；Second multiplex electronics；Phase discriminator.The present invention is used for the high speed serialization of signal.
Description
Technical field
The present invention relates to signal conversion arts, and in particular to a kind of serializer based on half rate clock restoring circuit.
Background technology
Serializer receives parallel data and is converted into serial bit stream；Input signal is usually 8 bit parallel datas, is led to
Often also 8 data can be converted into 10 data using certain encoding scheme when upper serial output link transmits.Deserializer is then
It is an opposite process.It receives serial data, is decoded when necessary, is reconverted into the data of parallel form.Deserializer
Also to restore data clock, and clock and data are transmitted to subsequent element together.2 complementary elements of this in SerDes carry
Supplied it is a kind of by original parallel data conversion at serial data to carry out the effective means of high efficiency of transmission；Also have in SerDes
One phaselocked loop (PLL) module, it receives System Clock Reference, and by its frequency multiplication to corresponding data rate.Independent sampling
The serial data that device module inputs the clock lock for using this frequency multiplication to cross.
Existing serializer affects operating rate, and consume in particular, using some optocouplers in integrated circuit
Electricity can also rise；And optocoupler serial line unit service life is not grown, and interim card is be easy to cause；There are clock jitters and data to tremble
It is dynamic；Lack detection check interface.
Invention content
For the above-mentioned prior art, a kind of based on the serial of half rate clock restoring circuit present invention aims at providing
Device aims to solve the problem that existing serializer is mismatched and led there are clock generator different in identical serializer acquisition clock frequency
It causes output data error larger, exists simultaneously logic circuit output level burr, the technical problems such as clock jitter and data distortion.
In order to achieve the above objectives, the technical solution adopted by the present invention is as follows：
A kind of serializer based on half rate clock restoring circuit, including parallel source signal further include that the first clock occurs
Device：The first clock signal is exported, for building signal acquisition time window；First multiplex electronics：Its sampling clock port
The feedback clock signal of feedback clock generator output is received, input terminal receives parallel source signal and output end output mixing letter
Number；Feedback clock generator：The first clock signal of the first clock generator output is received to obtain reference clock, output feedback
Clock signal, for building time delayed signal acquisition time window；Second multiplex electronics：Its sampling clock port receives first
First clock signal of clock generator output, input terminal receive the mixed signal and output end of the first multiplex electronics output
Export serial signal；Second clock generator：Second clock signal is exported, restores signal acquisition time window for building；When
Clock data recovery circuit：With Semi-digital inside and outside ring structure, inner ring road receives the second clock of second clock generator output
Signal receives serial signal, parallel signal of the output phase for half frequency of serial signal.
In said program, it is preferable that the clock data recovery circuit, including inner ring road：Including phaselocked loop, lock
Phase ring exports multi-phase clock signal；The outer ring being connect with phaselocked loop：Including the phase discriminator for constituting clock recovery loop, number
Word filter and phase interpolator, serial signal is inputted by phase discriminator input terminal and multi-phase clock signal is defeated by phase interpolator
Enter.Serial signal is converted into two parallel datas after the clock sampling of half rate, then compares generation phase through phase discriminator
Position discriminative information.Phase discriminative information gives the ratio and integral element of digital filter simultaneously, finally generates phase controlling letter
Breath gives phase interpolator.The parallel signal of half frequency is the characterization of serial signal, realizes feedback and the detection of output signal.
The phase discriminator, including it is sample circuit trigger circuit, decision circuit, double along trigger circuit；Sample circuit triggers
Circuit respectively under the control of four roads orthogonal each other clock pulses clk0, clk90, clk180, clk270 to input data into
Row sampling, exports the sampled data under clock pulses clk0, the sampled data under clock pulses clk90, clock pulses respectively
The sampled data under sampled data, clock pulses clk270 under clk180；The rising edge of the clock pulses clk90 relative to
Clock pulses clk0 delays T/4 arrives, and the rising edge of the clock pulses clk180 postpones T/4 relative to clock pulses clk90
It arrives, the rising edge of the clock pulses clk270 arrives relative to clock pulses clk180 delays T/4, and T is clock pulses
The period of clk0, clk90, clk180, clk270；
The phase discriminator further includes re-synchronization trigger circuit, by sample circuit under clock pulses clk180 controls
Sampled data under the clock pulses clk0 of trigger circuit output, the sampled data under clock pulses clk90 synchronize output,
Sampled data, clock under the clock pulses clk 180 for exporting sample circuit trigger circuit under clock pulses clk0 controls
Sampled data under pulse clk270 synchronizes output；Decision circuit will be through re-synchronization trigger circuit treated clock arteries and veins
It rushes the sampled data under clk0 and carries out exclusive or with the sampled data under clock pulses clk90, synchronous trigger circuit again will be come from
Clock pulses clk90 under the clock pulses clk180 that directly exports of sampled data and sample circuit trigger circuit under sampling
Data carry out exclusive or, will be through the sampled data and clock pulses under re-synchronization trigger circuit treated clock pulses clk180
Sampled data under clk270 carries out exclusive or, by the sampled data under the clock pulses clk270 of synchronous trigger circuit again
Exclusive or is carried out with the sampled data under the clock pulses clk0 of sample circuit trigger circuit, respectively obtains judgement indication signal
Up1、Up2、Dn1、Dn2；It is double to receive enabled pair of judgement indication signal Up1, Up2 along trigger circuit output UP letters along trigger circuit
Number, judgement indication signal Dn1, Dn2 is enabled double along trigger circuit output DN signals；It is double along tactile under clock pulses clk270 controls
Power Generation Road receive judgement indication signal Up1, judgement indication signal Dn1 it is enabled it is double along trigger circuit synchronism output matching UP signals with
DN signals, it is double along trigger circuit receives judgement indication signal Up2, judgement indication signal Dn2 makes under clock pulses clk90 controls
It can be double along trigger circuit synchronism output matching UP signals and DN signals.
In said program, third multiplex electronics：Its sampling clock port receives the anti-of feedback clock generator output
Clock signal is presented, input terminal receives high low logic level and output end output difference signal.In feedback clock signal generating process
Can have larger loss, third multiplexer is clamped down on input signal and difference so that feedback clock signal for
The next circuit has higher resolution, increases response device speed.
In said program, the feedback clock generator, including phase detecting circuit：Reception and more reversed first
Clock signal and differential signal export the first comparison signal；Voltage boosting-reducing circuit：Receive the first comparison signal, output control electricity
Press signal；Reset circuit：Output switching signal is to voltage boosting-reducing circuit；Frequency dividing circuit：Receive the first clock signal, output half
First clock signal of frequency；Delay circuit：Control voltage signal is received to adjust delay time, and receives frequency dividing circuit output
Clock signal, export feedback clock signal.Phase detecting circuit compares the first clock signal of the reversion in a phase
Third multiplex electronics output end differential signal, specifically, by the rising edge of the first clock signal of reversion and third multichannel
The edge of the differential signal of multiplex circuit.When phase detecting circuit output comparison signal be logic high, that is, illustrate to invert
The differential signals of the first clock signal and third multiplex electronics mismatch.The reference time delay of delay circuit can be to control electricity
Pressure range impacts, and specifically, reduces the order of delay circuit, reduces delay time range, can reduce circuit complexity
And electric quantity consumption, and further decrease noise and shake；After shake reduces, it can increase and multiplex electronics application is adopted
Collect time window, data can more pass through more quickly switching device.
In said program, it is preferable that the reset circuit, including first comparator：Export the second comparison signal；Second
Comparator：Export third comparison signal；First or door：Receive the first comparison signal and the second comparison signal；With first or door according to
Secondary concatenated first phase inverter, the second phase inverter and buffer；Second or door：Its input terminal is connected with the output end of first or door
With the output end of the second phase inverter；Third phase inverter：The output end of its input terminal connection second or door；First triode：Base stage
The output end of third phase inverter is connected, emitter connects the high electric end of circuit；Second triode：Base stage connection second or the output of door
End, emitter connect the low electric end of circuit；First node is the output end of first or door, is connected to delay circuit；Second node is
The output end of buffer is connected to the output end of voltage boosting-reducing circuit；Third node is the collector potential of the first triode
End, is connected to third multiplex electronics；Fourth node is reference voltage potential point.The switching signal of reset circuit output is based on
The control voltage level of voltage boosting-reducing circuit output.Voltage boosting-reducing circuit has high threshold voltage and low threshold voltage, works as control
Voltage level processed is less than low threshold voltage and is higher than high threshold voltage, and reset circuit closes voltage boosting-reducing circuit, and will control electricity
Voltage levels are reset between low threshold voltage and high threshold voltage, specifically, reset to the 50% of supply voltage.High threshold
Voltage range and low threshold voltage range are respectively supply voltage 0 to 30% and 85% to 100%.Reset circuit is to delay circuit
Control, can further control the sampling to the first multiplex electronics windowing the time, improve system to data waveform
Identification and judgement speed.
In said program, it is preferable that second clock signal rate is the half of the first clock signal.Clock number is provided
According to the system clock of restoring circuit.
Compared with prior art, beneficial effects of the present invention are：Acquisition clock is adjusted by data-signal self feed back
System obtains more rational parallel signal and turns serial signal self feed back modulation circuit structure to control acquisition window width；Data
Waveform rising time and failing edge time significantly reduce；The case where being inherently eliminated generation mistake pairing, greatly reduces
The burr that pure combinational logic generates.
Description of the drawings
Fig. 1 is module connection relationship diagram of the present invention；
Fig. 2 is the embodiment of reset circuit of the present invention；
Fig. 3 is the embodiment of delay circuit of the present invention；
Fig. 4 is the embodiment of phase discriminator of the present invention.
Specific implementation mode
All features disclosed in this specification or disclosed all methods or in the process the step of, in addition to mutually exclusive
Feature, other than step, can combine in any way.
The present invention will be further described below in conjunction with the accompanying drawings：
Fig. 1 be module connection relationship diagram of the present invention, a kind of serializer based on half rate clock restoring circuit, first
Clock generator and second clock generator consider specific implementation environment, the calibration pulse of processor in electronic system can be used
Output end is replaced.During signal conversion operation, the first clock signal and serial signal are in feedback clock generator
It is locked in equivalent delay locked loop, serial signal clock rate is the first clock of the first clock signal clock rate or reversion
The half of signal clock rate.
Embodiment 1
Fig. 2 is the embodiment of reset circuit of the present invention, and phase inverter U4 and phase inverter U5 is most simple delayer in the present embodiment
Part can be selected the delay circuit and replace phase inverter U4 and phase inverter U5 to obtain better function of initializing.After replacement, the
Four nodes are reference voltage input node, and size depends on the threshold value set required for the comparator selected and comparator electricity
Pressure or door U3 the second comparison signal, third comparison signal based on comparator U1 and comparator U2 outputs, generate the first control letter
Number or the first control signal of door U3 output be sent to first node.First control signal is delayed by delay circuit, and be delayed section
Depending on the reference voltage of fourth node input, specifically, delay time depends on the reference voltage difference of fourth node input
Size and reference voltage difference are loaded into the time used in first control signal.
Embodiment 2
Fig. 3 is the embodiment of delay circuit of the present invention, and concatenated buffer U9-U12, classification time is by access tunable capacitor
C1-C3；5th node and the 7th node are input node, and the 6th node is output node；7th node accesses voltage boosting-reducing electricity
Road, the capacitance of voltage boosting-reducing circuit control tunable capacitor, buffer U9-U12 generate phase delay.
Embodiment 3
The voltage boosting-reducing circuit, i.e. BOOST circuits, can according to actual use circuit shared by spatial volume situation into
Row, which reduces, to be replaced；Such as, when needing smaller circuit space volume, it can change and be selected as charge pump.Charge pump, energy storage device can
To be capacitance, output end is multiple series connection and about the collector and emitter of the complementary triode of the symmetrical raceway groove of output end,
Input terminal is the base stage of multiple triodes, and certain logic gate is added in base stage for the logic realized as needed, realizes charge pump；
Relative to BOOST circuits, charge pump cloth plate bulk is relatively small, and circuit structure does not need inductance, and response speed is exceedingly fast.
Embodiment 4
Fig. 4 is the embodiment of phase discriminator of the present invention, under the sampled data D0 under clock pulses clk0, clock pulses clk90
Sampled data D90, the sampled data D180 under clock pulses clk180 is the data sample point of continuous sampling three times, similarly
Under sampled data D270 under sampled data D180 under clock pulses clk180, clock pulses clk270, clock pulses clk0
Sampled data D0 also be the data sample point of continuous sampling three times (D0 at this time is D360).Because of a half rate clock
(it is equal to two data periods) in period, there is the data sample point of two groups of continuous samplings three times：(D0, D90, D180) and
(D180, D270, D0), therefore the subsequent processing situation of this two groups of data sample points is explained separately below, to be easier to understand
The operation principle of phase discriminator.
The data sample point of first group of continuous sampling three times：D0, D90, D180.Clock pulses clk0, clk90 and clk180
Trigger 301~303 is acted on successively, continuously samples input data data three times, therefore produce three data sample point D0,
D90, D180.Wherein D0 and D90 carries out xor operation and generates judgement indication signal Up1；D90 and D180 carries out xor operation generation
Adjudicate indication signal Dn1.To make signal Up1 and Dn1 in synchronization output and effectively, then requiring D0, D90 and D180 same
One moment exported and effectively, thus D0, D90 and D180 must re-synchronization in a clock signal.The present invention uses clk180
Trigger 311 and 312 is acted on, D0 and D90 of re-synchronization generates signal D0_1 and D90_1 after re-synchronization respectively,
In conjunction with D180, by XOR gate 321 and 322, judgement indication signal Up1 and Dn1 are produced respectively.It is next after clk180
A clock is along being clk270, therefore the present invention is acted on double along trigger 331 and 332 using clk270, resynchronizes primary judgement
Indication signal Up1 and Dn1, to generate final UP and DN signals.
The data sample point of second group of continuous sampling three times：D180, D270, D0.Similarly, clock pulses clk180,
Clk270 and clk0 (clk0 at this time is clk360) act on trigger 303,304 and 301 successively, continuously sample three times defeated
Enter data data, therefore produce three data sample point D180, D270, D0 (D0 at this time is D360).Wherein D180 and
D270 carries out xor operation and generates signal Up2；D270 and D0 carries out xor operation and generates signal Dn2.To make signal Up2 and
Dn2 is exported and effectively in synchronization, then requires D180, D270 and D0 in synchronization output and effectively, therefore D180, D270
With the necessary re-synchronizations of D0 in a clock signal.The present invention acts on trigger 313 and 314, re-synchronization one using clk0
Secondary D180 and D270 generates D180_1 and D270_1 and passes through XOR gate 323 in conjunction with D0 (D0 at this time is D360) respectively
With 324, Up2 and Dn2 signals are produced respectively.Next clock edge after clk0 (clk0 at this time is clk360) is
Clk90, thus the present invention using clk90 act on it is double resynchronize a Up2 and Dn2 signal along trigger 331 and 332, to
Generate final UP and DN signals.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Belong to those skilled in the art in the technical scope disclosed by the present invention, the change or replacement that can be readily occurred in all are answered
It is included within the scope of the present invention.
Claims (2)
1. a kind of serializer based on half rate clock restoring circuit, including parallel source signal, which is characterized in that further include
First clock generator：The first clock signal is exported, for building signal acquisition time window；
First multiplex electronics：Its sampling clock port receives the feedback clock signal of feedback clock generator output, input
End receives parallel source signal and output end exports mixed signal；
Second multiplex electronics：Its sampling clock port receives the first clock signal of the first clock generator output, input
End receives the mixed signal of the first multiplex electronics output and output end exports serial signal；
Feedback clock generator：The first clock signal of the first clock generator output is received to obtain reference clock, output is anti-
Clock signal is presented, for building time delayed signal acquisition time window；
Second clock generator：Second clock signal is exported, restores signal acquisition time window for building；
Clock data recovery circuit：With Semi-digital inside and outside ring structure, inner ring road receives the of second clock generator output
Two clock signals receive serial signal, parallel signal of the output phase for half frequency of serial signal；
The clock data recovery circuit, inner ring road include phaselocked loop, and phaselocked loop exports multi-phase clock signal, with phaselocked loop
The outer ring of connection includes the phase discriminator for constituting clock recovery loop, digital filter and phase interpolator, and serial signal is by reflecting
Phase device input terminal inputs and multi-phase clock signal is inputted by phase interpolator；
The phase discriminator, including sample circuit trigger circuit, decision circuit, it is double along trigger circuit and re-synchronization triggering electricity
Road, sample circuit trigger circuit respectively sample input data under the control of four roads clock pulses orthogonal each other；
Further include third multiplex electronics：Its sampling clock port receives the feedback clock letter of feedback clock generator output
Number, input terminal receives high low logic level and output end output difference signal；
The feedback clock generator, including
Phase detecting circuit：Reception and more reversed the first clock signal and differential signal export the first comparison signal；
Voltage boosting-reducing circuit：The first comparison signal is received, control voltage signal is exported；
Reset circuit：Output switching signal is to voltage boosting-reducing circuit；
Frequency dividing circuit：The first clock signal is received, the first clock signal of half frequency is exported；
Delay circuit：Control voltage signal is received to adjust delay time, and receives the clock signal of frequency dividing circuit output, output
Feedback clock signal.
2. a kind of serializer based on half rate clock restoring circuit according to claim 1, which is characterized in that it is described just
The clock pulses of friendship, is generated by voltage controlled oscillator or the signal generator by that can generate the orthogonal clock pulse each other of four roads generates.
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| CN107659392B (en) * | 2017-03-13 | 2019-12-13 | 广东高云半导体科技股份有限公司 | clock data recovery system |
| EP3415937A1 (en) * | 2017-06-15 | 2018-12-19 | Nagravision S.A. | Method for detecting at least one glitch in an electrical signal and device for implementing this method |
| CN108331577A (en) * | 2017-12-27 | 2018-07-27 | 北京六合伟业科技股份有限公司 | Through non magnetic drill collar and MWD wireless communication systems and method in oil drilling |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102801414A (en) * | 2012-08-23 | 2012-11-28 | 电子科技大学 | Bang-bang discriminator used for half speed rate clock data restoring circuit |
| CN205596095U (en) * | 2016-01-29 | 2016-09-21 | 成都科创谷科技有限公司 | Serializer based on half rate clock recovery circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7433442B2 (en) * | 2004-09-23 | 2008-10-07 | Standard Microsystems Corporation | Linear half-rate clock and data recovery (CDR) circuit |
| JP4533715B2 (en) * | 2004-10-07 | 2010-09-01 | 川崎マイクロエレクトロニクス株式会社 | Phase comparator |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102801414A (en) * | 2012-08-23 | 2012-11-28 | 电子科技大学 | Bang-bang discriminator used for half speed rate clock data restoring circuit |
| CN205596095U (en) * | 2016-01-29 | 2016-09-21 | 成都科创谷科技有限公司 | Serializer based on half rate clock recovery circuit |
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