CN105553449B - Slew Rate self calibration driving circuit, driver Slew Rate calibration circuit and its calibration method - Google Patents
Slew Rate self calibration driving circuit, driver Slew Rate calibration circuit and its calibration method Download PDFInfo
- Publication number
- CN105553449B CN105553449B CN201511019634.2A CN201511019634A CN105553449B CN 105553449 B CN105553449 B CN 105553449B CN 201511019634 A CN201511019634 A CN 201511019634A CN 105553449 B CN105553449 B CN 105553449B
- Authority
- CN
- China
- Prior art keywords
- time delay
- comparator
- slew rate
- driver
- oscillation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
- Electronic Switches (AREA)
Abstract
The invention discloses a kind of Slew Rate self calibration driving circuit, driver Slew Rate calibration circuit and its calibration methods.The Slew Rate of driver output signal is determined by the difference of the starting voltage and final voltage that set and the delay inequality of two oscillation/time delay modules, i.e. the Slew Rate of driver output signal can be adaptively adjusted to target Slew Rate, effectively overcome the deviation that technique, temperature and power source change are brought to the Slew Rate of driver output signal, so that electronic device is more stablized, efficiently works.Wherein, oscillation/time delay module is in addition to for signal delay, also it is multiplexed with ring oscillator, output frequency by adjusting ring oscillator carries out accurate calibration to the retardation of signal, the actuator unit quantity opened by counter adjustment, and then the driving intensity of adjust drivers, Slew Rate is dynamically adjusted during driver output signal rise/fall, it is accurately adjusted to the precision that Slew Rate calibration greatly improved to target Slew Rate.
Description
Technical field
The invention belongs to electronic circuit technology fields, more particularly, to a kind of Slew Rate self calibration driving circuit, driver
Slew Rate calibrates circuit and its calibration method, and the output signal Slew Rate of electronics driver can be made adaptive and be accurately adjusted to
Desired value.
Background technology
Electronics driver is normally used for the transmission of the signal between device, and the signal to be transmitted has wanting for Slew Rate
It asks, i.e., the rate that signal is converted between different components, driver needs are designed according to the requirement of Slew Rate.Electronics device
The performance of part is by technique, and clearly, in real work, the Slew Rate of driver may be with design for the influence of temperature and supply voltage
It is required that value have prodigious deviation.When the practical Slew Rate of driver output signal is more than the Slew Rate of design requirement, driver hair
The high speed signal gone out can give out more electromagnetic radiation, these electromagnetic interferences (EMI) can influence other elements or circuit just
Often work causes data degradation or performance during other element manipulations to decline；And when the practical pendulum of driver output signal
When rate is less than the Slew Rate of design requirement, conversion time of the signal between unlike signal level may be extended, and influence device
Working frequency.Therefore, the driver all to transmitter etc. such as high-speed data communication agreement, such as USB3.0, SATA3, PCIE2
Slew Rate proposes requirement.Therefore, it is necessary to propose it is a kind of can adjust automatically driver output signal Slew Rate circuit, so that output is believed
Number Slew Rate it is consistent with target Slew Rate.
Invention content
For the disadvantages described above or Improvement requirement of the prior art, the present invention provides a kind of Slew Rate self calibration driving circuit,
Driver Slew Rate calibrates circuit and its calibration method, and the Slew Rate of driver output signal can be made to be adaptively adjusted to target and put
Rate, and the precision of Slew Rate calibration is high, the Slew Rate for effectively overcoming technique, temperature and power source change to driver output signal is brought
Deviation, make electronic device more stablize, efficiently work.
To achieve the above object, according to one aspect of the present invention, a kind of driver Slew Rate calibration circuit is provided, it is special
Sign is, including first comparator, the second comparator, the first oscillation/time delay module, the second oscillation/time delay module, phase discriminator and
Counter；Wherein, the first input end of the first comparator is used to connect the output end of driver, the first comparator
Second input terminal connects institute for inputting the first datum REF1, the output end of the first comparator by the first transmission gate
State the input terminal of the first oscillation/time delay module；The first input end of second comparator is used to connect the output end of driver,
Second input terminal of second comparator passes through for inputting the second datum REF2, the output end of second comparator
Second transmission gate connects the input terminal of second oscillation/time delay module；The output end of first oscillation/time delay module and institute
The output end for stating the second oscillation/time delay module connects the counter by the phase discriminator, and the output end of the counter is used
In connection driver；
First oscillation/time delay module include by odd number inverse delayed unit the first time delay chain in series and with
The third transmission gate of the first time delay chain parallel connection, second oscillation/time delay module include by odd number inverse delayed unit
Second time delay chain in series and the 4th transmission gate in parallel with second time delay chain；First oscillation/time delay module
For making the output signal of the first comparator generate retardation T1, it is additionally operable to be multiplexed with first annular oscillator, passes through tune
The output frequency of first annular oscillator is saved to retardation T1It is calibrated, second oscillation/time delay module is described for making
The output signal of second comparator generates retardation T2, it is additionally operable to be multiplexed with the second ring oscillator, by adjusting the second annular
The output frequency of oscillator is to retardation T2It is calibrated.
Preferably, the first datum REF1 is preset as the starting voltage of the target Slew Rate of the output signal of driver, the
Two datum REF2 are preset as the final voltage of the target Slew Rate of the output signal of driver；The phase discriminator is used for described
The output signal of first oscillation/time delay module and first oscillation/time delay module is there are when phase difference, according to the big of phase difference
It is small, control the counter incremental count or countdown；The driver Slew Rate calibrates meter of the circuit according to the counter
The output signal Slew Rate of driver is adjusted to desired value by the driving intensity of numerical value adjust drivers
Preferably, when first saltus step occurs for the first comparator second comparator, retardation T is set1It is more than
Retardation T2；When first saltus step occurs for the second comparator first comparator, retardation T is set2More than retardation
T1。
Preferably, it by adjusting the size of current of the power port for the inverse delayed unit for flowing into the first time delay chain, adjusts
The output frequency of first annular oscillator；By adjusting the electric current of the power port for the inverse delayed unit for flowing into the second time delay chain
Size adjusts the output frequency of the second ring oscillator.
It is another aspect of this invention to provide that providing a kind of Slew Rate self calibration driving circuit, which is characterized in that including driving
Device and above-mentioned driver Slew Rate calibrate circuit.
Preferably, the driver includes multi-phase clock generator and multiple actuator units in parallel, the parallel connection
The input terminals of multiple actuator units be used as the input terminal of the driver, it is described for input the signal source that transmits of needs
The output end of multiple actuator units in parallel is used as the output end of the driver, described in the output end connection of the counter
Multiple output ends of the input terminal of multi-phase clock generator, the multi-phase clock generator are separately connected the multiple driving
The Enable Pin of device unit；The multi-phase clock generator be used for according to the count value of the counter generate out of phase when
Clock signal is turned on and off with controlling the multiple actuator unit.
Preferably, the quantity of the clock signal of the out of phase generated by the control of the count value of the counter, in turn
The quantity for controlling the actuator unit opened, makes corresponding actuator unit open successively, to adjust the defeated of the driver
Go out signal swing rate.
Another aspect according to the invention, provide it is a kind of with above-mentioned driver Slew Rate calibration circuit carry out Slew Rate calibration
Method, which is characterized in that include the following steps：
(1) the first transmission gate is made to turn off, third transmission gate conducting, the first oscillation/time delay module constitutes first annular oscillation
Device makes the second transmission gate turn off, and the 4th transmission gate conducting, the second oscillation/time delay module constitutes the second ring oscillator, passes through tune
The output frequency for saving first annular oscillator and the second ring oscillator is poor, calibrates the delay of the first time delay chain and the second time delay chain
Difference；
(2) by the output signal of driver be separately input into first comparator first input end and the second comparator
One input terminal inputs the first datum REF1, the second input terminal of the second comparator to the second input terminal of first comparator
Input the second datum；Wherein, the first datum REF1 is the starting voltage of the target Slew Rate of driver output signal, the
Two datum REF2 are the final voltage of the target Slew Rate of driver output signal；
(3) make the first transmission gate and the second transmission gate conducting, third transmission gate and the shutdown of the 4th transmission gate, prolong using first
When chain so that the output signal of first comparator is generated retardation T1, so that the output signal of the second comparator is produced using the second time delay chain
Raw retardation T2；
(4) it, according to phase difference size, is controlled there are when phase difference in the output signal of the first time delay chain and the second time delay chain
Counter incremental count or countdown；
(5) according to the driving intensity of the count value adjust drivers of counter, the output signal Slew Rate of driver is adjusted
Extremely
Another aspect according to the invention provides a kind of side of above-mentioned Slew Rate self calibration driving circuit progress Slew Rate calibration
Method, which is characterized in that include the following steps：
(1) the first transmission gate is made to turn off, third transmission gate conducting, the first oscillation/time delay module constitutes first annular oscillation
Device makes the second transmission gate turn off, and the 4th transmission gate conducting, the second oscillation/time delay module constitutes the second ring oscillator, passes through tune
The output frequency for saving first annular oscillator and the second ring oscillator is poor, calibrates the delay of the first time delay chain and the second time delay chain
Difference；
(2) by the output signal of driver be separately input into first comparator first input end and the second comparator
One input terminal inputs the first datum REF1, the second input terminal of the second comparator to the second input terminal of first comparator
Input the second datum；Wherein, the first datum REF1 is the starting voltage of the target Slew Rate of driver output signal, the
Two datum REF2 are the final voltage of the target Slew Rate of driver output signal；
(3) make the first transmission gate and the second transmission gate conducting, third transmission gate and the shutdown of the 4th transmission gate, prolong using first
When chain so that the output signal of first comparator is generated retardation T1, so that the output signal of the second comparator is produced using the second time delay chain
Raw retardation T2；
(4) it, according to phase difference size, is controlled there are when phase difference in the output signal of the first time delay chain and the second time delay chain
Counter incremental count or countdown；
(5) number of the clock signal for the out of phase that multi-phase clock generator is generated according to the adjustment of the count value of counter
Amount, so that the actuator unit of corresponding number is opened successively, to by the output signal Slew Rate of driver adjust to
In general, through the invention it is contemplated above technical scheme is compared with the prior art, have below beneficial to effect
Fruit：Pass through the starting voltage and final voltage of the target Slew Rate of setting driver output signal and two oscillation/time delay modules
Delay inequality, make the Slew Rate of driver output signal by the difference of starting voltage and final voltage set and two oscillations/
The delay inequality of time delay module determines that is, the Slew Rate of driver output signal can be adaptively adjusted to target Slew Rate, effectively be overcome
The deviation that technique, temperature and power source change are brought to the Slew Rate of driver output signal makes electronic device more stablize, efficiently
Ground works.Wherein, oscillation/time delay module is also multiplexed with ring oscillator in addition to for signal delay, by adjusting ring oscillation
The output frequency of device carries out accurate calibration to the retardation of signal, the actuator unit quantity opened by counter adjustment, into
And the driving intensity of adjust drivers, Slew Rate is dynamically adjusted during driver output signal rise/fall, it is accurate
Ground adjusts the precision that Slew Rate calibration greatly improved to target Slew Rate.
Description of the drawings
Fig. 1 is the structural schematic diagram of the Slew Rate self calibration driving circuit of the embodiment of the present invention；
Fig. 2 is the method flow diagram that Slew Rate calibration is carried out with the driver Slew Rate of embodiment of the present invention calibration circuit.
Specific implementation mode
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.As long as in addition, technical characteristic involved in the various embodiments of the present invention described below
It does not constitute a conflict with each other and can be combined with each other.
As shown in Figure 1, the Slew Rate self calibration driving circuit of the embodiment of the present invention includes driver 101 and driver Slew Rate school
Quasi- circuit.
Wherein, driver Slew Rate calibration circuit includes first comparator 301, the second comparator 302, the first oscillation/delay
Module 401, the second oscillation/time delay module 402, phase discriminator 500 and counter 600.Wherein, the first of first comparator 301 is defeated
Enter output end 20 of the end for connecting driver 101, the second input terminal 31 of first comparator 301 is for inputting first with reference to electricity
Flat REF1, the output end of first comparator 301 connect the input of the first oscillation/time delay module 401 by the first transmission gate 4014
End；The first input end of second comparator 302 is used to connect the output end 20 of driver 101, and the second of the second comparator 302 is defeated
Enter end 32 for inputting the second datum REF2, the output end of the second comparator 302 passes through the second transmission gate 4024 connection the
The input terminal of two oscillations/time delay module 402；The output end of first oscillation/time delay module 401 and the second oscillation/time delay module 402
Output end be separately connected the first input end and the second input terminal of phase discriminator 500, the first output end of phase discriminator 500 and second
Output end is separately connected the first input end and the second input terminal of counter 600, and the output end of counter 600 drives for connecting
Device 101.
Further, the first oscillation/time delay module 401 includes in series by odd number inverse delayed unit 4012
First time delay chain 4015 and the third transmission gate 4013 in parallel with the first time delay chain 4015, the second oscillation/time delay module 402 include
By odd number inverse delayed unit 4,022 second time delay chain 4025 in series and the in parallel with the second time delay chain 4025 the 4th
Transmission gate 4023.First oscillation/time delay module 401 and the second oscillation/time delay module 402 are multiplexed with oscillator and time delay chain.
When work, the first datum REF1 is preset as the starting voltage of the target Slew Rate of the output signal of driver 100,
Second datum REF2 is preset as the final voltage of the target Slew Rate of the output signal of driver 100；First transmission gate 4014
It is connected and third transmission gate 4013 turns off, the first oscillation/time delay module 401 is used as time delay chain, makes the output of first comparator 301
Signal generates retardation T1, the second transmission gate 4024 is connected and the 4th transmission gate 4023 turns off, the second oscillation/time delay module 402
As time delay chain, the output signal of the second comparator 302 is made to generate retardation T2；The signal of the first input end of phase discriminator 500
When having phase difference with the signal of the second input terminal, phase discriminator 500 passes through the first output of phase discriminator 500 according to phase difference size
600 incremental count of control counter is held, 600 countdown of second output terminal control counter of phase discriminator 500 is passed through；Counter
600 export count value to driver 101, according to the driving intensity of count value adjust drivers 101, thus by driver 101
Output signal Slew Rate be adjusted to desired value, even if the output signal Slew Rate of driver 101
Specifically, when compared with the second comparator 302 first saltus step occurs for first comparator 301, the first time delay chain 4015 prolongs
When amount more than the second time delay chain 4025 amount of delay；When compared with first comparator 301 first saltus step occurs for the second comparator 302, the
The amount of delay of two time delay chains 4025 is more than the amount of delay of the first time delay chain 4015.
Due to being influenced by factors such as technique, supply voltage and temperature, the first time delay chain 4015 and the second time delay chain 4025
Delay have larger difference on the chip of different batches, therefore, it is necessary to the first time delay chain 4015 and the second time delay chain
4025 amount of delay is calibrated, it is made to generate required amount of delay.Specifically, make the shutdown of the first transmission gate 4014 and third passes
Defeated door 4013 is connected, and the first oscillation/time delay module 401 constitutes first annular oscillator, by accurately adjusting first annular oscillation
The output frequency of device carries out accurate calibration to the amount of delay of the first time delay chain 4015；Similarly, the second transmission gate 4024 is made to turn off
And the 4th transmission gate 4023 be connected, the second oscillation/time delay module 402 constitute the second ring oscillator, by accurately adjusting second
The output frequency of ring oscillator carries out accurate calibration to the amount of delay of the second time delay chain 4025.Preferably, pass through control first
Current source 4011, adjustment flow into the size of current of the power port of inverse delayed unit 4012, adjust first annular oscillator
Output frequency；By controlling the second current source 4021, adjustment flows into the size of current of the power port of inverse delayed unit 4022,
Adjust the output frequency of the second ring oscillator.
As shown in Figure 1, in one embodiment of the invention, driver 101 includes 1011 He of multi-phase clock generator
Multiple actuator units 1012 in parallel, the input terminal of multiple actuator units 1012 in parallel are used as the input of driver 101
End 10, for inputting the signal source for needing to transmit, the output end of multiple actuator units 1012 in parallel is used as driver 101
Output end 20, the input terminal of the output end connection multi-phase clock generator 1011 of counter 600, multi-phase clock generator
1011 multiple output ends are separately connected the Enable Pin of multiple actuator units 1012.Multi-phase clock generator 1011 is for producing
The clock signal of raw out of phase, and respectively from multiple output ends of multi-phase clock generator 1011 by these outs of phase
Clock signal is sent to the Enable Pin of corresponding actuator unit 1012, and corresponding actuator unit 1012 is made to open successively.It is more
The bit rate of the clock signal for the out of phase that phase clock generator 1011 generates is identical as the signal source that needs transmit.
Specifically, the out of phase of the generation of multi-phase clock generator 1011 is controlled by the count value of counter 600
The quantity of clock signal, and then the quantity for the actuator unit 1012 opened is controlled, to adjust the output end 20 of driver 101
Output signal Slew Rate.In one embodiment of the invention, controller is set between counter 600 and driver 101, is used for
According to the count value of counter 600, one group of control code is generated, 1011 each cycle of multi-phase clock generator is controlled by control code
The quantity of the clock signal of the out of phase of output.
Specifically, in one timing of the output of counter 100, multiple actuator units 1012 are in multi-phase clock generator
It is opened successively under the action of the clock signal of 1011 outs of phase generated, can make the output of the output end 20 of driver 101
The Slew Rate variation that on off state variation of the variation of signal swing rate less than single driver unit 1012 is brought, thus can significantly carry
The degree of regulation of the output signal Slew Rate of the output end 20 of high driver 101.
Further, as shown in Fig. 2, including such as with the method that above-mentioned Slew Rate self calibration driving circuit carries out Slew Rate calibration
Lower step：
(1) the first transmission gate 4014 is made to turn off, third transmission gate 4013 is connected, and the first oscillation/time delay module 401 constitutes the
One ring oscillator makes the second transmission gate 4024 turn off, and the 4th transmission gate 4023 conducting, the second oscillation/time delay module 402 is constituted
Second ring oscillator, accurate calibration the poor by the output frequency for adjusting first annular oscillator and the second ring oscillator
The delay inequality of one time delay chain 4015 and the second time delay chain 4025.
(2) output signal of driver 101 first input end of first comparator 301 and second is separately input into compare
The first input end of device 302 inputs the first datum REF1 to the second input terminal 31 of first comparator 301, and second compares
Second input terminal 32 of device 302 inputs the second datum REF2；Wherein, the first datum REF1 is the defeated of driver 100
Go out the starting voltage of the target Slew Rate of signal, the second datum REF2 is the target Slew Rate of the output signal of driver 100
Final voltage.
(3) the first transmission gate 4014 and the second transmission gate 4024 is made to be connected, third transmission gate 4013 and the 4th transmission gate
4023 shutdowns make the output signal of first comparator 301 generate retardation T using the first time delay chain 40151, utilize the second delay
Chain 4025 makes the output signal of the second comparator 302 generate retardation T2。
(4) in the output signal of the first time delay chain 4015 and the second time delay chain 4025 there are when phase difference, phase discriminator 500
According to phase difference size, 600 incremental count of control counter or countdown.
(5) clock for the out of phase that multi-phase clock generator 1011 is generated according to the adjustment of the count value of counter 600
The quantity of signal makes the actuator unit 1012 of corresponding number open successively, thus by the output signal Slew Rate tune of driver 101
It is whole extremely
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, all within the spirits and principles of the present invention made by all any modification, equivalent and improvement etc., should all include
Within protection scope of the present invention.
Claims (2)
1. a kind of with the driver Slew Rate calibration circuit method that carries out Slew Rate calibration, the driver Slew Rate calibration circuit includes the
One comparator, the second comparator, the first oscillation/time delay module, the second oscillation/time delay module, phase discriminator and counter；Wherein,
The first input end of the first comparator is used to connect the output end of driver, and the second input terminal of the first comparator is used
In inputting the first datum REF1, the output end of the first comparator by the first transmission gate connect first oscillation/
The input terminal of time delay module；The first input end of second comparator is used to connect the output end of driver, second ratio
The second input terminal compared with device passes through the second transmission gate for inputting the second datum REF2, the output end of second comparator
Connect the input terminal of second oscillation/time delay module；The output end of first oscillation/time delay module and described second shakes
Swing/output end of time delay module connects the counter by the phase discriminator, the output end of the counter drives for connecting
Dynamic device；First oscillation/time delay module include by odd number inverse delayed unit the first time delay chain in series and with institute
The third transmission gate of the first time delay chain parallel connection is stated, second oscillation/time delay module includes by odd number inverse delayed unit string
Join the second time delay chain constituted and fourth transmission gate in parallel with second time delay chain；First oscillation/time delay module is used
Retardation T is generated in making the output signal of the first comparator1, it is additionally operable to be multiplexed with first annular oscillator, passes through adjusting
The output frequency of first annular oscillator is to retardation T1It is calibrated, second oscillation/time delay module is for making described the
The output signal of two comparators generates retardation T2, it is additionally operable to be multiplexed with the second ring oscillator, is shaken by adjusting the second annular
The output frequency of device is swung to retardation T2It is calibrated；It is characterized in that, described method includes following steps：
(1) the first transmission gate is made to turn off, third transmission gate conducting, the first oscillation/time delay module constitutes first annular oscillator, makes
Second transmission gate turns off, the 4th transmission gate conducting, and the second oscillation/time delay module constitutes the second ring oscillator, by adjusting the
The output frequency of one ring oscillator and the second ring oscillator is poor, calibrates the delay inequality of the first time delay chain and the second time delay chain；
(2) by the output signal of driver be separately input into first comparator first input end and the second comparator it is first defeated
Enter end, the first datum REF1, the second input terminal input of the second comparator are inputted to the second input terminal of first comparator
Second datum；Wherein, the first datum REF1 is the starting voltage of the target Slew Rate of driver output signal, the second ginseng
Examine the final voltage for the target Slew Rate that level REF2 is driver output signal；
(3) make the first transmission gate and the second transmission gate conducting, third transmission gate and the shutdown of the 4th transmission gate, utilize the first time delay chain
The output signal of first comparator is set to generate retardation T1, so that the output signal of the second comparator is generated using the second time delay chain and prolong
Amount T late2；
(4) in the output signal of the first time delay chain and the second time delay chain there are when phase difference, according to phase difference size, control counts
Device incremental count or countdown；
(5) according to the driving intensity of the count value adjust drivers of counter, by the output signal Slew Rate of driver adjust to
2. a kind of method that Slew Rate self calibration driving circuit carries out Slew Rate calibration, the Slew Rate self calibration driving circuit includes driving
Device and driver Slew Rate calibrate circuit, and the driver Slew Rate calibration circuit includes first comparator, the second comparator, first shakes
Swing/time delay module, the second oscillation/time delay module, phase discriminator and counter；Wherein, the first input end of the first comparator
Output end for connecting driver, the second input terminal of the first comparator is for inputting the first datum REF1, institute
The output end for stating first comparator connects the input terminal of first oscillation/time delay module by the first transmission gate；Described second
The first input end of comparator is used to connect the output end of driver, and the second input terminal of second comparator is for inputting the
The output end of two datum REF2, second comparator connect the second oscillation/time delay module by the second transmission gate
Input terminal；The output end of the output end of first oscillation/time delay module and second oscillation/time delay module passes through described
Phase discriminator connects the counter, and the output end of the counter is for connecting driver；First oscillation/time delay module packet
It includes by odd number inverse delayed unit the first time delay chain in series and the third transmission gate in parallel with first time delay chain,
Second oscillation/time delay module includes by odd number inverse delayed unit the second time delay chain in series and with described second
4th transmission gate of time delay chain parallel connection；First oscillation/time delay module is for making the output signal of the first comparator produce
Raw retardation T1, it is additionally operable to be multiplexed with first annular oscillator, by adjusting the output frequency of first annular oscillator to delay
Measure T1It is calibrated, second oscillation/time delay module is used to make the output signal of second comparator to generate retardation T2,
It is additionally operable to be multiplexed with the second ring oscillator, by adjusting the output frequency of the second ring oscillator to retardation T2Carry out school
It is accurate；The driver includes multi-phase clock generator and multiple actuator units in parallel, multiple drivers of the parallel connection
The input terminal of unit is used as the input terminal of the driver, for inputting the signal source for needing to transmit, multiple drives of the parallel connection
The output end of dynamic device unit is used as the output end of the driver, and the output end of the counter connects the multiphase clock production
Multiple output ends of the input terminal of raw device, the multi-phase clock generator are separately connected the enabled of the multiple actuator unit
End；The multi-phase clock generator is used to generate the clock signal of out of phase according to the count value of the counter, with control
The multiple actuator unit is made to be turned on and off；It is characterized in that, described method includes following steps：
(1) the first transmission gate is made to turn off, third transmission gate conducting, the first oscillation/time delay module constitutes first annular oscillator, makes
Second transmission gate turns off, the 4th transmission gate conducting, and the second oscillation/time delay module constitutes the second ring oscillator, by adjusting the
The output frequency of one ring oscillator and the second ring oscillator is poor, calibrates the delay inequality of the first time delay chain and the second time delay chain；
(2) by the output signal of driver be separately input into first comparator first input end and the second comparator it is first defeated
Enter end, the first datum REF1, the second input terminal input of the second comparator are inputted to the second input terminal of first comparator
Second datum；Wherein, the first datum REF1 is the starting voltage of the target Slew Rate of driver output signal, the second ginseng
Examine the final voltage for the target Slew Rate that level REF2 is driver output signal；
(3) make the first transmission gate and the second transmission gate conducting, third transmission gate and the shutdown of the 4th transmission gate, utilize the first time delay chain
The output signal of first comparator is set to generate retardation T1, so that the output signal of the second comparator is generated using the second time delay chain and prolong
Amount T late2；
(4) in the output signal of the first time delay chain and the second time delay chain there are when phase difference, according to phase difference size, control counts
Device incremental count or countdown；
(5) quantity of the clock signal for the out of phase that multi-phase clock generator is generated according to the adjustment of the count value of counter,
So that the actuator unit of corresponding number is opened successively, to by the output signal Slew Rate of driver adjust to
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511019634.2A CN105553449B (en) | 2015-12-31 | 2015-12-31 | Slew Rate self calibration driving circuit, driver Slew Rate calibration circuit and its calibration method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511019634.2A CN105553449B (en) | 2015-12-31 | 2015-12-31 | Slew Rate self calibration driving circuit, driver Slew Rate calibration circuit and its calibration method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105553449A CN105553449A (en) | 2016-05-04 |
| CN105553449B true CN105553449B (en) | 2018-09-07 |
Family
ID=55832421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201511019634.2A Active CN105553449B (en) | 2015-12-31 | 2015-12-31 | Slew Rate self calibration driving circuit, driver Slew Rate calibration circuit and its calibration method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105553449B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108566196B (en) * | 2018-04-17 | 2020-07-28 | 西安交通大学 | CMOS driver applied to output signal slew rate control |
| CN109257042B (en) * | 2018-09-20 | 2022-08-12 | 西安空间无线电技术研究所 | VCO (voltage controlled oscillator) ring oscillator circuit for relieving SET (Single event) effect |
| CN111162449B (en) * | 2020-02-26 | 2021-08-20 | 歌尔光学科技有限公司 | Laser working circuit and 3D camera |
| TWI808464B (en) * | 2021-08-10 | 2023-07-11 | 強弦科技股份有限公司 | Modulation circuit of power drive stage |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW483256B (en) * | 1998-06-09 | 2002-04-11 | Siemens Ag | Clock latency compensation circuit for DDR timing |
| US6777974B2 (en) * | 2000-01-20 | 2004-08-17 | Infineon Technologies Ag | Arrangement and method for adjustment of the slope times for one or more drivers and a driver circuit |
| CN101478306A (en) * | 2008-01-03 | 2009-07-08 | 南亚科技股份有限公司 | Driving circuit slew rate compensation apparatus and method |
| CN102684650A (en) * | 2011-03-11 | 2012-09-19 | 苏州芯动科技有限公司 | Automatic calibration control method for slew rate |
-
2015
- 2015-12-31 CN CN201511019634.2A patent/CN105553449B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW483256B (en) * | 1998-06-09 | 2002-04-11 | Siemens Ag | Clock latency compensation circuit for DDR timing |
| US6777974B2 (en) * | 2000-01-20 | 2004-08-17 | Infineon Technologies Ag | Arrangement and method for adjustment of the slope times for one or more drivers and a driver circuit |
| CN101478306A (en) * | 2008-01-03 | 2009-07-08 | 南亚科技股份有限公司 | Driving circuit slew rate compensation apparatus and method |
| CN102684650A (en) * | 2011-03-11 | 2012-09-19 | 苏州芯动科技有限公司 | Automatic calibration control method for slew rate |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105553449A (en) | 2016-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105553449B (en) | Slew Rate self calibration driving circuit, driver Slew Rate calibration circuit and its calibration method | |
| CN104299640B (en) | Slew rate adaptive adjustment output circuit | |
| US9413370B2 (en) | Anti process variation self-adjustable on-chip oscillator | |
| CN104124945B (en) | Duty ratio calibrating circuit | |
| CN105577142A (en) | Clock duty cycle adjusting device and method | |
| CN102983842A (en) | Duty ratio adjusting circuit | |
| CN102394643A (en) | Digital pulse width modulator based on digital delayed-locked loop (DLL) | |
| WO2018121358A1 (en) | On-chip clock circuit and on-chip clock signal generation method | |
| CN108922571A (en) | A kind of the reading data signal processing circuit and reading data processing method of DDR memory | |
| CN104753499A (en) | Duty ratio calibrating circuit | |
| US8451064B2 (en) | Voltage-controlled oscillator module having adjustable oscillator gain and related operating methods | |
| CN105656461A (en) | Delay line circuit | |
| CN112711296A (en) | Calibration system | |
| CN103427798A (en) | Multiphase clock generation circuit | |
| CN104094524B (en) | Dutyfactor adjustment circuit | |
| CN104822197A (en) | Analog dimming control method, control circuit and LED drive circuit using the analog dimming control method and control circuit | |
| CN202364200U (en) | Digital pulse width modulator based on digital delay phase-locked loop | |
| CN105227257A (en) | A kind of modified clock synchronous mirror delay circuit | |
| CN104935325B (en) | Output circuit in interface circuit | |
| CN104124964A (en) | Delay phase-locked loop and method for improving accuracy of delay phase-locked loop | |
| CN104135282B (en) | Multiphase clock generator realizes high-resolution method | |
| CN102638225A (en) | On-chip clock frequency regulating circuit and regulating method | |
| CN102522966A (en) | Programmable nanosecond pulse signal generator | |
| CN202634363U (en) | Trimming circuit used for oscillator | |
| CN105141295B (en) | The self-calibration circuit of embedded clock |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201210 Address after: Room 9011, 9 / F, South Tower, international business center (ICC), 3000 Huandao East Road, Hengqin New District, Zhuhai City, Guangdong Province Patentee after: Core microelectronics technology (Zhuhai) Co., Ltd Address before: 215123 D 608, science and Technology Park, West Jiaotong University, 99 Ren Yan Road, Suzhou Industrial Park, Jiangsu Patentee before: INNOSILICON TECHNOLOGIES Co.,Ltd. |
|
| TR01 | Transfer of patent right |