CN105548995A - Method for improving distance measurement precision of responder - Google Patents
Method for improving distance measurement precision of responder Download PDFInfo
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- CN105548995A CN105548995A CN201510885880.XA CN201510885880A CN105548995A CN 105548995 A CN105548995 A CN 105548995A CN 201510885880 A CN201510885880 A CN 201510885880A CN 105548995 A CN105548995 A CN 105548995A
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- dds
- frame synchronization
- answering machine
- frequency control
- control word
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S11/00—Systems for determining distance or velocity not using reflection or reradiation
- G01S11/02—Systems for determining distance or velocity not using reflection or reradiation using radio waves
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- Mobile Radio Communication Systems (AREA)
Abstract
The invention provides a method for improving distance measurement precision of a responder and aims to provide a simple and reliable method for improving downlink frame synchronization trailing edge pulse precision. According to the method, in a noncoherent mode, after an uplink signal is received by the responder, the uplink frame synchronization information is extracted after de-spreading, demodulation frame synchronization processing, an uplink frame synchronization signal is sampled by utilizing the downlink frame synchronization trailing edge pulse, the sampling value after re-framing is sent to a ground station through a downlink, and distance measurement is carried out by the ground station through calculating time delay between sending frame synchronization and receiving frame synchronization. The method for improving distance measurement precision of the responder is advantaged in that the compensation function is realized through programming in an FPGA chip of a responder hardware platform, a system clock of the responder is used as a modulation clock of the downlink, a 32-bit frequency control word accumulator DDS is utilized to generate a code sending clock, and the code sending clock is utilized to generate the downlink frame synchronization trailing edge pulse.
Description
Technical field
The present invention relates to a kind of implementation method improving answering machine distance accuracy under non-coherent mode.
Background technology
Under current main-stream TT & C architecture non-coherent mode, external instrumentation system will obtain high-precision ranging data, be unable to do without the precision distance measurement answering machine of collaborative work, only define the high accuracy data chain in large loop, the world, just may realize high-precision range finding and location.In range measurement system, the error introduced by answering machine mainly comprise answering machine itself null value offset error, measure the null value measuring error introduced and the null value variation error caused due to environmental condition change.Answering machine null value offset error and null value measuring error will be introduced directly among system accuracy, but all by improving the margin of error that answering machine performance and measuring accuracy are introduced to reduce these two kinds of factors.
Current raising aircraft carries the method for answering machine distance accuracy and thinking has two kinds.One: by improving the hardware performance of answering machine, improving the stability of answering machine zero-range set constant, reducing the range finding offset error of answering machine.Along with the maturing of hardware device and application circuit, there is not very large room for promotion in this method.Its two: on the hardware platform of answering machine maturation, by the stability adopting new software algorithm to improve accuracy data.Method two all has the incomparable advantage of method one in cost, dirigibility, extensibility etc.
Under non-coherent mode, the range measurement principle of answering machine is: extract frame synchronization information through signal transacting such as despreading, demodulation, frame synchronization after answering machine receiving uplink signal, along sampling to upward signal after utilizing the frame synchronization of downlink, utilize downlink to be sent to land station by after sampled value again framing, land station by calculate the synchronous and received frame of transmission frame synchronous between time delays carry out range observation.The clocking error of answering machine downlink frame synchronization trailing edge directly affects the distance accuracy of TT&C system.Answering machine downlink frame synchronization trailing edge is by signaling clock generating, signaling clock is the modulating clock being done downlink by system clock, frequency of utilization control word totalizer DDS produces, and therefore the distance accuracy of precision on TT&C system of frequency control word accumulator brings direct impact.At present, the frequency control word accumulator of answering machine generally gets 32, and its frequency control word computing formula is:
Wherein F
ddsfor the clock frequency control word of generation signaling, F
dds integerfor the integral part of frequency control word, F
dds decimalfor the fraction part of frequency control word.Its implementation procedure realizes in FPGA inside, and fractional part branch is rejected, and DDS is constantly cumulative causes residual error, causes the signaling clock produced to there is error, finally causes downlink frame synchronization trailing edge not accurate.
The method of current reduction residual error mainly contains the integral multiple that system clock to be set to signaling clock by three kinds: first, takes this method to make answering machine very restricted in Clock Design, substantially cannot realize; Second improves system clock, takes this method can cause the problems such as designed reliability reduction, power consumption increase; 3rd increases frequency control word accumulator DDS figure place, take this method can cause the problems such as design resource increases, and latter two method just will produce the time lengthening of same distance saltus step, does not all tackle the problem at its root.
Summary of the invention
Producing the above-mentioned defect of downlink frame synchronization trailing edge in order to overcome current answering machine, the invention provides a kind of method of more simple and reliable raising answering machine distance accuracy, to improve the precision of downlink frame synchronization trailing edge.
The technical solution adopted for the present invention to solve the technical problems is: a kind of raising method of answering machine distance accuracy, it is characterized in that comprising the steps: under non-coherent mode, through the frame synchronization information of despreading, demodulation, frame synchronization process extraction up-link after answering machine receiving uplink signal, the frame synchronization trailing edge of downlink is utilized to sample to upward signal afterwards, and utilize downlink to be sent to land station by after sampled value again framing, land station by calculate the synchronous and received frame of transmission frame synchronous between time delays carry out range observation; The following compensate function of programming realization in the fpga chip of answering machine hardware platform, the modulating clock of downlink is made of the system clock of answering machine, 32 bit frequency control word totalizer DDS are used to produce signaling clock, with signaling clock generating downlink frame synchronization trailing edge, in each frame data time T, the fraction part producing the frequency control word that signaling clock is given up is compensated, the distance saltus step r=c/ (2*clk) that optimization system clock causes, wherein, c is the light velocity, c=3*10
8m/s, clk are the system clock of FPGA, and the order of magnitude is MHz, r is meter level.
The invention has the beneficial effects as follows: the production method of the present invention to answering machine downlink frame synchronization trailing edge improves and optimize, in each frame data time T, the fraction part producing the frequency control word that signaling clock is given up is compensated, the clock jitter that the cumulative residual error reducing DDS causes.After the fraction part given up signaling clock in each frame data time T compensates, the distance accuracy of system can optimize the distance saltus step r=c/ (2*clk) that a system clock causes, and improves the precision of downlink frame synchronization trailing edge.
The FPGA that the present invention is applied to answering machine hardware platform on bullet is inner, by improving and optimize the production method of answering machine downlink frame synchronization trailing edge on bullet, improve distance accuracy, solve that prior art DDS is constantly cumulative causes residual error, cause producing signaling clocking error and downlink frame synchronization trailing edge not problem accurately.
The invention provides a kind of frequency control word based on clock to compensate, improve the precision of the frame synchronization trailing edge of downlink, the final method improving answering machine distance accuracy.Be applied to the fpga chip of answering machine hardware platform, by improving and optimize the generation of answering machine downlink frame synchronization trailing edge, improve distance accuracy.Answering machine downlink frame synchronization trailing edge adopts 32 bit accumulators to produce in FPGA inside, this implementation method do not increase totalizer figure place, do not improve FPGA system clock prerequisite under, the fraction part of frequency control word is compensated within the frame data time, improves the precision of downlink frame synchronization trailing edge.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and example, the present invention is further described.
Fig. 1 is method schematic diagram of the present invention.
Embodiment
Consult Fig. 1.According to the present invention, at non-coherent mode, through the frame synchronization information of despreading, demodulation, frame synchronization process extraction up-link after answering machine receiving uplink signal, the frame synchronization trailing edge of downlink is utilized to sample to upward signal afterwards, and utilize downlink to be sent to land station by after sampled value again framing, land station by calculate the synchronous and received frame of transmission frame synchronous between time delays carry out range observation; The following compensate function of programming realization in the fpga chip of answering machine hardware platform, the modulating clock of downlink is made of the system clock of answering machine, 32 bit frequency control word totalizer DDS are used to produce signaling clock, with signaling clock generating downlink frame synchronization trailing edge, in each frame data time T, the fraction part producing the frequency control word that signaling clock is given up is compensated, optimize the distance saltus step r=c/ (2*clk) that a system clock causes, wherein, c is the light velocity, c=3*10
8m/s, clk are the system clock of FPGA, and the order of magnitude is MHz, r is meter level.
FPGA inside on a hardware platform generates answering machine signaling clock, its implementation is: the system clock of selecting does debug clock, 32 bit frequency control word totalizer DDS are used to generate signaling clock, wherein frequency control word calculates according to formula (2), the frequency control word of totalizer generally comprises integer and decimal two parts, carry out only having integral part effective when frequency control word adds up in FPGA inside, fraction part is rejected.Wherein frequency control word computing formula is:
Be F according to the cumulative errors of fraction part in a frame data time T that formula (2) is rejected
dds decimal* T*clk, compensated frequency control word in the downlink frame synchronization trailing edge Tn moment.Compensation method is as follows:
If F
dds decimal> 0.5, the integral part of frequency control word and fraction part calculate according to formula (3)
F
dds=F1
dds integer-F1
dds decimal
F1
dds integer=F
dds integer+ 1
F1
dds decimal=1-F
dds decimal(3)
If F
dds decimal≤ 0.5, integral part and the fraction part of frequency control word remain unchanged,
F
dds=F1
dds integer+ F1
dds decimal
F1
dds integer=F
dds integer
F1
dds decimal=F
dds decimal(4)
Inner at the FPGA of answering machine hardware platform, get F1
dds integersend into 32 bit frequency control word totalizer DDS to add up, at downlink frame synchronization trailing edge T
nmoment compensates frequency control word, and compensation formula is as formula (5), and wherein T is each frame data time of answering machine downlink on bullet in Fig. 1,
F2=T*clk*F1
dds decimal(5)
Formula (3), (4) are brought in formula (5) and are obtained:
Claims (5)
1. the raising method of an answering machine distance accuracy, it is characterized in that comprising the steps: under non-coherent mode, through the frame synchronization information of despreading, demodulation, frame synchronization process extraction up-link after answering machine receiving uplink signal, the frame synchronization trailing edge of downlink is utilized to sample to upward signal afterwards, and utilize downlink to be sent to land station by after sampled value again framing, land station by calculate the synchronous and received frame of transmission frame synchronous between time delays carry out range observation; The following compensate function of programming realization in the fpga chip of answering machine hardware platform, the modulating clock of downlink is made of the system clock of answering machine, 32 bit frequency control word totalizer DDS are used to produce signaling clock, with signaling clock generating downlink frame synchronization trailing edge, in each frame data time T, the fraction part producing the frequency control word that signaling clock is given up is compensated, the distance saltus step r=c/ (2*clk) that optimization system clock causes, wherein, c is the light velocity, c=3*10
8m/s, clk are the system clock of FPGA, and the order of magnitude is MHz, r is meter level.
2. the raising method of answering machine distance accuracy as claimed in claim 1, is characterized in that: answering machine compensated the fraction part that frequency control word is given up in the downlink frame synchronization trailing edge Tn moment.
3. the raising method of answering machine distance accuracy as claimed in claim 1, is characterized in that: the frequency control word accumulator of answering machine gets 32, by following formulae discovery frequency control word:
Wherein, F
ddsfor the clock frequency control word of generation signaling, F
dds integerfor the integral part of frequency control word, F
dds decimalfor the fraction part of frequency control word.
4. the raising method of answering machine distance accuracy as claimed in claim 3, is characterized in that: work as F
dds decimal> 0.5, the integral part of frequency control word and fraction part calculate according to formula (3)
F
dds=F1
dds integer-F1
dds decimal
F1
dds integer=F
dds integer+ 1
F1
dds decimal=1-F
dds decimal(3)
Work as F
dds decimal≤ 0.5, integral part and the fraction part of frequency control word remain unchanged,
F
dds=F1
dds integer+ F1
dds decimal
F1
dds integer=F
dds integer
F1
dds decimal=F
dds decimal(4)
5. the raising method of answering machine distance accuracy as claimed in claim 1, is characterized in that: inner at the FPGA of answering machine hardware platform, gets F1
dds integersend into 32 bit frequency control word totalizer DDS to add up, in the downlink frame synchronization trailing edge Tn moment, frequency control word is compensated, compensation formula is as formula (5) and (6), and wherein T is each frame data time of answering machine downlink
F2=T*clk*F1
dds decimal(5)
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107271967A (en) * | 2016-11-26 | 2017-10-20 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | pulse coherent transponder co-channel interference processing system |
| CN109581447A (en) * | 2018-12-06 | 2019-04-05 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | More Radio Link Combined Calculation Spread Spectrum TT&C equipment zero methods |
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| EP0940691A2 (en) * | 1998-03-05 | 1999-09-08 | Matsushita Electric Industrial Co., Ltd. | Distance detecting method and its apparatus |
| WO2004074865A1 (en) * | 2003-02-18 | 2004-09-02 | Cambridge Silicon Radio Limited | Distance estimation |
| CN103297218A (en) * | 2013-05-28 | 2013-09-11 | 中国电子科技集团公司第十研究所 | Distance measuring data processing method under incoherent measuring system |
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2015
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| EP0940691A2 (en) * | 1998-03-05 | 1999-09-08 | Matsushita Electric Industrial Co., Ltd. | Distance detecting method and its apparatus |
| WO2004074865A1 (en) * | 2003-02-18 | 2004-09-02 | Cambridge Silicon Radio Limited | Distance estimation |
| CN103297218A (en) * | 2013-05-28 | 2013-09-11 | 中国电子科技集团公司第十研究所 | Distance measuring data processing method under incoherent measuring system |
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| 李永波: "一种提高应答机伪码非相干测距精度的方法", 《电讯技术》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107271967A (en) * | 2016-11-26 | 2017-10-20 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | pulse coherent transponder co-channel interference processing system |
| CN107271967B (en) * | 2016-11-26 | 2020-03-31 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Pulse coherent transponder same-frequency interference processing system |
| CN109581447A (en) * | 2018-12-06 | 2019-04-05 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | More Radio Link Combined Calculation Spread Spectrum TT&C equipment zero methods |
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