CN105548819A - High-voltage direct current transmission line internal fault and external fault identification method based on backward traveling waves - Google Patents

Abstract

The invention discloses a high-voltage direct current transmission line internal fault and external fault identification method based on backward traveling waves. The high-voltage direct current transmission line internal fault and external fault identification method comprises the following steps that firstly, a voltage transformer and a current transformer installed on the rectification station line side and an inversion station line side of a direct current transmission system collect voltage and current across the two ends of a positive electrode line and voltage and current across the two ends of a negative electrode line respectively; secondly, the voltage leap amount and current leap amount of the two ends of the positive electrode line and the voltage leap amount and current leap amount of the two ends of the negative electrode line are calculated; thirdly, the voltage leap amount and current leap amount of each electrode line are transformed into corresponding line mode voltage component and line mode current component; fourthly, the voltage backward waves at the two ends of the direct current line are worked out according to the line mode voltage component and the line mode current component, and integration of backward wave amplitude values is conducted in specific time; fifthly, a specific value of the backward wave amplitude value integral on the rectification side of the direct current line to the backward wave amplitude value integral on the inversion side of the direct current line is calculated, and faults are judged according to the specific value. By means of the method, the internal faults and the external faults can be quickly and accurately recognized, correct actions can still be conducted under the high-resistance faults at the line tail end and the noise interferences, and reliability and sensitivity are high.

Description

A kind of HVDC (High Voltage Direct Current) transmission line internal fault external fault recognition methods based on anti-row ripple

Technical field

The present invention relates to field of power, specifically a kind of HVDC (High Voltage Direct Current) transmission line internal fault external fault recognition methods based on anti-row ripple.

Background technology

At present, DC line, using traveling-wave protection as the main protection of circuit, protects to identify whether DC line breaks down in support with differential under-voltage protection, electric current longitudinal differential protection etc.Wherein, traveling-wave protection and differential under-voltage protection form Protection criteria according to voltage change ratio, when circuit generation high resistive fault, because voltage change ratio can not reach definite value and easily tripping.

Electric current longitudinal differential protection is as the back-up protection of traveling-wave protection and differential under-voltage protection; effectively can detect high resistive fault; but differential protection is the line distribution capacitance charging and discharging currents of avoiding AC fault outside district to cause and sampled value to fluctuate the malfunction caused; its responsiveness is slow; actuation time is level second; likely before differential protection action; under-voltage protection in the control of rectification side pole or maximum Trigger Angle protection act, by the locking of fault pole, make differential protection usually not have back-up protection effect to circuit.Meanwhile, current differential protection, for ensureing reliability, needs circuit two end data precise synchronization, requires higher to communication apparatus.

Summary of the invention

The object of the invention is the weak point overcoming existing DC transmission line area inside/outside failure recognition methods, propose a kind of HVDC (High Voltage Direct Current) transmission line internal fault external fault recognition methods based on anti-row ripple, the method reliably can identify the internal fault external fault of circuit rapidly, also can rapid reaction for high resistance earthing fault.

For achieving the above object, the present invention realizes by the following technical solutions: a kind of HVDC (High Voltage Direct Current) transmission line internal fault external fault recognition methods based on anti-row ripple, comprises the following steps:

Voltage, electric current that a () is arranged on the voltage in DC transmission system converting plant and Inverter Station line side, current transformer gathers positive pole and negative pole circuit two ends respectively;

B () utilizes the electric current and voltage at the circuit two ends collected, calculate voltage jump amount and the jump-value of current at positive pole circuit and negative pole circuit two ends;

C () utilizes phase-model transformation method, the voltage jump amount on each the polar curve road obtained and jump-value of current are converted to corresponding line mode voltage component and line mould current component;

D () utilizes line mode voltage component and line mould galvanometer to calculate the anti-row ripple of voltage at DC line two ends, and carry out integration to anti-row wave amplitude within the specific time;

E () calculates the ratio of DC line rectification side and inverter side anti-row wave amplitude integral result, if this ratio is greater than threshold value, failure judgement occurs in outside circuit; If this ratio is less than threshold value, failure judgement occurs on the line.

Further, preferably, the detailed process of described step (b) is:

(b1) through type (1), calculates voltage jump amount and the jump-value of current of positive pole circuit and negative pole circuit rectification side,

$\left\{\begin{array}{c}{\mathrm{\Δu}}_{Rp}=u_{Rp}\left(N\right)-u_{Rp}(N-n)\\ {\mathrm{\Δi}}_{Rp}=i_{Rp}\left(N\right)-i_{Rp}(N-n)\end{array}\right.---\left(1\right)$

In formula (1), Δ u _rp, Δ i _rpbe respectively voltage jump amount and the jump-value of current of positive pole circuit and negative pole circuit rectification side; u _rpfor the voltage of positive pole circuit and negative pole circuit rectification side, wherein p=1,2,1 represents positive pole circuit, and 2 represent negative pole circuit; N is sampled point number, and n is the sampling number in 10ms, u _rp(N) sampled value of positive pole circuit and negative pole circuit rectification side voltage is represented, i _rp(N) sampled value of positive pole circuit and negative pole circuit rectification side electric current is represented.

(b2) in like manner, adopt formula (1), calculate voltage jump amount and the jump-value of current of positive pole circuit and negative pole circuit inverter side.

Further, preferably, the detailed process of described step (c) is:

(c1) through type (2), calculates line mode voltage and the line mould current component of DC line rectification side,

$\left\{\begin{array}{c}{\mathrm{\Δu}}_{R11}=\frac{{\mathrm{\Δu}}_{R1}-{\mathrm{\Δu}}_{R2}}{\sqrt{2}}\\ {\mathrm{\Δi}}_{R11}=\frac{{\mathrm{\Δi}}_{R1}-{\mathrm{\Δi}}_{R2}}{\sqrt{2}}\end{array}\right.---\left(2\right)$

In formula, Δ u _r11with Δ i _r11be respectively line mode voltage and the line mould electric current of DC line rectification side.

(c2) in like manner, through type (2), calculates the line mode voltage Δ u of DC line inverter side _i11with line mould electric current Δ i _i11.

Further, preferably, the detailed process of described step (d) is:

(d1) utilize line mode voltage component and line mould electric current, calculate the anti-row ripple of voltage of DC line rectification side and inverter side.

$\left\{\begin{array}{c}{u}_{Rb}={\mathrm{\Δu}}_{R11}-Z_C{\mathrm{\Δi}}_{R11}\\ u_{Ib}={\mathrm{\Δu}}_{I11}-Z_C{\mathrm{\Δi}}_{I11}\end{array}\right.---\left(3\right)$

In formula, u _rbwith u _ibbe respectively the anti-row ripple of voltage of DC line rectification side and inverter side, Z _cfor DC line wave impedance;

(d2) at specific time T _din integration is carried out, shown in (4) to anti-row wave amplitude

$\left\{\begin{array}{c}{b}_R={\∫}_{t_1}^{t_1+T_d}\left|u_{Rb}\right|dt\\ b_I={\∫}_{t_2}^{t_2+T_d}\left|u_{Ib}\right|dt\end{array}\right.---\left(4\right)$

In formula (4), b _rand b _ithe amplitude integration of DC line rectification side and the anti-row ripple of inverter side in a period of time respectively, t ₁and t ₂be respectively the time that DC line rectification side and inverter side detect fault, T _dscope value be wherein, l is line length, and v is row velocity of wave propagation.

(d3) discretize is carried out to formula (4), can obtain

$\left\{\begin{array}{c}{b}_R=\underset{i=1}{\overset{Ns}{\Σ}}\left|u_{Rb}\left(i\right)\right|\mathrm{\Δ}t\\ b_I=\underset{i=1}{\overset{Ns}{\Σ}}\left|u_{Ib}\left(i\right)\right|\mathrm{\Δ}t\end{array}\right.---\left(5\right)$

In formula (5), i=1 represents after fault being detected first sampled point, and Ns is the sampling number in an integration window length, and Δ t is sampling interval.

Further, preferably, the detailed process of described step (e) is:

(e1) by the amplitude integrated value of DC line rectification side and the anti-row ripple of inverter side, larger integrated value is than upper less integrated value, and obtaining integration ratio R atio is:

$Ratio=\frac{max(b_R,b_I)}{min(b_R,b_I)}<\mathrm{\&epsiv;}---\left(6\right)$

In formula (6), ε is the threshold value of internal fault external fault identical criterion;

(e2) when integration ratio R atio is less than threshold value ε, failure judgement occurs on the line, otherwise failure judgement occurs in outside circuit.

Further, preferably, described threshold value ε is 5.

Further, preferably, after described step (d), also comprise step (f) before step (e), the detailed process of described step (f) is: circuit Inverter Station obtained anti-row wave amplitude integral result is passed to converting plant.

Compared with prior art, the present invention has following beneficial effect:

One, data window required for the present invention is short, the impact of uncontrolled systemic effect, can quick and precisely cog region internal and external fault, also can correct operation under line end high resistive fault and noise, and reliability and sensitivity is high.

Two, the present invention only needs the result of anti-row wave amplitude integration transmitting inverter side, need not transfer overvoltage, current sampling data in real time, to communication speed and the requirement of two ends data syn-chronization low, existing means of communication can be adapted to.

Three, than the existing internal fault external fault recognition methods based on transient, the sample frequency that the present invention extracts anti-row ripple is 10kHz, identical with the sampling rate of actual DC system control protection device, facilitates engineering construction.

Figure of description

Fig. 1 is the bipolar line mode of connection in DC transmission engineering.

Embodiment

Clearly understand for making the object, technical solutions and advantages of the present invention, below in conjunction with embodiment and accompanying drawing, the present invention is described in further detail, and exemplary embodiment of the present invention and explanation thereof are only for explaining the present invention, not as a limitation of the invention.

Embodiment

A kind of HVDC (High Voltage Direct Current) transmission line internal fault external fault recognition methods based on anti-row ripple of the present invention, comprises the following steps:

Voltage, electric current that a () is arranged on the voltage in DC transmission system converting plant and Inverter Station line side, current transformer gathers positive pole and negative pole circuit two ends respectively; The mode of connection that DC transmission engineering adopts usually is bipolar line mode, carries out delivery of electrical energy by the wire of two opposed polarities (i.e. positive and negative electrode), and these two wires are referred to as positive pole circuit and negative pole circuit.Wherein, current conversion station leading-out terminal above earth potential is positive be called positive pole, for negative is called negative pole, as shown in Figure 1.

B () utilizes the electric current and voltage at the circuit two ends collected, calculate voltage jump amount and the jump-value of current at positive pole circuit and negative pole circuit two ends;

C () utilizes phase-model transformation method, the voltage jump amount on each the polar curve road obtained and jump-value of current are converted to corresponding line mode voltage component and line mould current component, here each polar curve road refers to positive pole circuit and negative pole circuit, phase-model transformation is prior art conventional in a kind of transmission line of electricity, does not repeat them here.

D () utilizes line mode voltage component and line mould galvanometer to calculate the anti-row ripple of voltage at DC line two ends, and carry out integration to anti-row wave amplitude within the specific time, and DC line two ends here refer to the rectification side of circuit and the inverter side of circuit.

E () calculates the ratio of DC line rectification side and inverter side anti-row wave amplitude integral result, if this ratio is greater than threshold value, failure judgement occurs in outside circuit; If this ratio is less than threshold value, failure judgement occurs on the line.

Particularly, the detailed process of step (b) is:

(b1) through type (1), calculates voltage jump amount and the jump-value of current of positive pole circuit and negative pole circuit rectification side,

$\left\{\begin{array}{c}{\mathrm{\&Delta;u}}_{Rp}=u_{Rp}\left(N\right)-u_{Rp}(N-n)\\ {\mathrm{\&Delta;i}}_{Rp}=i_{Rp}\left(N\right)-i_{Rp}(N-n)\end{array}\right.---\left(1\right)$

In formula (1), Δ u _rp, Δ i _rpbe respectively voltage jump amount and the jump-value of current of positive pole circuit and negative pole circuit rectification side; u _rpfor the voltage of positive pole circuit and negative pole circuit rectification side, wherein p=1,2,1 represents positive pole circuit, and 2 represent negative pole circuit; N is sampled point number, and n is the sampling number in 10ms, u _rp(N) sampled value of positive pole circuit and negative pole circuit rectification side voltage is represented, i _rp(N) sampled value of positive pole circuit and negative pole circuit rectification side electric current is represented.

(b2) in like manner, adopt formula (1), calculate voltage jump amount and the jump-value of current of positive pole circuit and negative pole circuit inverter side.

Particularly, the detailed process of step (c) is:

(c1) through type (2), calculates line mode voltage and the line mould current component of DC line rectification side,

$\left\{\begin{array}{c}{\mathrm{\&Delta;u}}_{R11}=\frac{{\mathrm{\&Delta;u}}_{R1}-{\mathrm{\&Delta;u}}_{R2}}{\sqrt{2}}\\ {\mathrm{\&Delta;i}}_{R11}=\frac{{\mathrm{\&Delta;i}}_{R1}-{\mathrm{\&Delta;i}}_{R2}}{\sqrt{2}}\end{array}\right.---\left(2\right)$

In formula, Δ u _r11with Δ i _r11be respectively line mode voltage and the line mould electric current of DC line rectification side.

(c2) in like manner, through type (2), calculates the line mode voltage Δ u of DC line inverter side _i11with line mould electric current Δ i _i11.

Particularly, the detailed process of step (d) is:

(d1) utilize line mode voltage component and line mould electric current, calculate the anti-row ripple of voltage of DC line rectification side and inverter side.

$\left\{\begin{array}{c}{u}_{Rb}={\mathrm{\&Delta;u}}_{R11}-Z_C{\mathrm{\&Delta;i}}_{R11}\\ u_{Ib}={\mathrm{\&Delta;u}}_{I11}-Z_C{\mathrm{\&Delta;i}}_{I11}\end{array}\right.---\left(3\right)$

In formula, u _rbwith u _ibbe respectively the anti-row ripple of voltage of DC line rectification side and inverter side, Z _cfor DC line wave impedance;

(d2) at specific time T _din integration is carried out, shown in (4) to anti-row wave amplitude

$\left\{\begin{array}{c}{b}_R={\&Integral;}_{t_1}^{t_1+T_d}\left|u_{Rb}\right|dt\\ b_I={\&Integral;}_{t_2}^{t_2+T_d}\left|u_{Ib}\right|dt\end{array}\right.---\left(4\right)$

In formula (4), b _rand b _ithe amplitude integration of DC line rectification side and the anti-row ripple of inverter side in a period of time respectively, t ₁and t ₂be respectively the time that DC line rectification side and inverter side detect fault, T _dscope value be wherein, l is line length, and v is row velocity of wave propagation.

(d3) discretize is carried out to formula (4), can obtain

$\left\{\begin{array}{c}{b}_R=\underset{i=1}{\overset{Ns}{\&Sigma;}}\left|u_{Rb}\left(i\right)\right|\mathrm{\&Delta;}t\\ b_I=\underset{i=1}{\overset{Ns}{\&Sigma;}}\left|u_{Ib}\left(i\right)\right|\mathrm{\&Delta;}t\end{array}\right.---\left(5\right)$

In formula (5), i=1 represents after fault being detected first sampled point, and Ns is the sampling number in an integration window length, and Δ t is sampling interval.

Particularly, the detailed process of step (e) is:

(e1) by the amplitude integrated value of DC line rectification side and the anti-row ripple of inverter side, larger integrated value is than upper less integrated value, and obtaining integration ratio R atio is:

$Ratio=\frac{max(b_R,b_I)}{min(b_R,b_I)}<\mathrm{\&epsiv;}---\left(6\right)$

In formula (6), ε is the threshold value of internal fault external fault identical criterion, and the large I of threshold value is determined as required;

(e2) when integration ratio R atio is less than threshold value ε, failure judgement occurs on the line, otherwise failure judgement occurs in outside circuit.

Particularly, the preferred threshold value ε of the present embodiment is 5, and namely when integration ratio R atio is less than 5, failure judgement occurs on the line, otherwise failure judgement occurs in outside circuit.

Particularly, after step (d), before step (e), also comprise step (f), the detailed process of described step (f) is: circuit Inverter Station obtained anti-row wave amplitude integral result is passed to converting plant, in DC transmission system, the logic that restarts of DC line completes in rectification side, only need inverter side to provide anti-row wave amplitude integration information to rectification side, do not need the anti-row wave amplitude integral result of converting plant to pass to Inverter Station.

In conjunction with the content of the inventive method, provide following emulation embodiment for a certain DC transmission system model:

The inventive method builds ± 500kV DC transmission system realistic model, and model parameter is with reference to Three Gorges-Changzhou DC transmission engineering.Wherein, power transmission power is 3000MW, and rated voltage and rated current are respectively 500kV and 3kA.Transmission line length is set to 2000km.Circuit model adopts frequency dependent model, and tower structure adopts DC2.Sample frequency is 10kHz.The line mould wave impedance of getting under 5kHz calculates anti-row ripple, and the wave impedance obtained under 5kHz by route parameter calculation is 213 Ω.Arranging F1 ~ F5 is trouble spot, and wherein, F1 represents positive pole line fault, and F2 represents negative pole line fault, and F3 represents fault outside converting plant smoothing reactor, and F4 represents Inverter Station AC fault, and F5 represents bipolar line fault.

Table 1 gives positive pole F1 fault, negative pole F2 fault in different faults Distance geometry transition resistance inferior segment, the Fault Identification result under bipolar F5 fault.

Fault Identification result under the different troubles inside the sample space condition of table 1

As shown in Table 1, during the internal fault of generating region, although along with the increase of transition resistance, the amplitude integration of the anti-row ripple at circuit two ends reduces, but the anti-row wave amplitude integration ratio at circuit two ends is substantially constant, and in different faults pole, fault distance situation, the ratio of anti-row wave amplitude integration is all no more than 1.5, be less than threshold value, be judged as troubles inside the sample space.

Table 2 gives the Fault Identification result outside converting plant smoothing reactor under F3 fault and Inverter Station AC F4 fault.

The test result of protection algorism under the different external area error condition of table 2

As shown in Table 2, when there is external area error, the anti-row wave amplitude integration of circuit one end, much larger than the anti-row wave amplitude integration of the other end, utilizes the notable difference of the anti-row wave amplitude integration at circuit two ends accurately can identify external area error.

More than test and do not consider noise effect, for verifying the adaptability of this invention in practical engineering application, adding signal to noise ratio (S/N ratio) is in simulations that the noise of 20dB is to simulate the signal disturbing that may occur in practical application.Fault Identification the results are shown in Table 3.

Fault Identification result in table 3 noise situation

From table 3 simulation result, during troubles inside the sample space, the impact of noise on protection is less; During external area error, due to the existence of noise, increase the error of calculation of the anti-row ripple in one end, the ratio of circuit two ends anti-row wave amplitude integration is declined, but still has enough nargin accurately to identify external area error.

Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only the specific embodiment of the present invention; the protection domain be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (7)

1., based on a HVDC (High Voltage Direct Current) transmission line internal fault external fault recognition methods for anti-row ripple, it is characterized in that: comprise the following steps:

Voltage, electric current that a () is arranged on the voltage in DC transmission system converting plant and Inverter Station line side, current transformer gathers positive pole and negative pole circuit two ends respectively;

B () utilizes the electric current and voltage at the circuit two ends collected, calculate voltage jump amount and the jump-value of current at positive pole circuit and negative pole circuit two ends;

C () utilizes phase-model transformation method, the voltage jump amount on each the polar curve road obtained and jump-value of current are converted to corresponding line mode voltage component and line mould current component;

D () utilizes line mode voltage component and line mould galvanometer to calculate the anti-row ripple of voltage at DC line two ends, and carry out integration to anti-row wave amplitude within the specific time;

E () calculates the ratio of DC line rectification side and inverter side anti-row wave amplitude integral result, if this ratio is greater than threshold value, failure judgement occurs in outside circuit; If this ratio is less than threshold value, failure judgement occurs on the line.

2. a kind of HVDC (High Voltage Direct Current) transmission line internal fault external fault recognition methods based on anti-row ripple according to claim 1, is characterized in that: the detailed process of described step (b) is:

(b1) through type (1), calculates voltage jump amount and the jump-value of current of positive pole circuit and negative pole circuit rectification side,

$\left\{\begin{array}{c}{\mathrm{\&Delta;u}}_{Rp}=u_{Rp}\left(N\right)-u_{Rp}(N-n)\\ {\mathrm{\&Delta;i}}_{Rp}=i_{Rp}\left(N\right)-i_{Rp}(N-n)\end{array}\right.---\left(1\right)$

In formula (1), Δ u _rp, Δ i _rpbe respectively voltage jump amount and the jump-value of current of positive pole circuit and negative pole circuit rectification side; u _rpfor the voltage of positive pole circuit and negative pole circuit rectification side, wherein p=1,2,1 represents positive pole circuit, and 2 represent negative pole circuit; N is sampled point number, and n is the sampling number in 10ms, u _rp(N) sampled value of positive pole circuit and negative pole circuit rectification side voltage is represented, i _rp(N) sampled value of positive pole circuit and negative pole circuit rectification side electric current is represented.

(b2) in like manner, adopt formula (1), calculate voltage jump amount and the jump-value of current of positive pole circuit and negative pole circuit inverter side.

3. a kind of HVDC (High Voltage Direct Current) transmission line internal fault external fault recognition methods based on anti-row ripple according to claim 2, is characterized in that: the detailed process of described step (c) is:

(c1) through type (2), calculates line mode voltage and the line mould current component of DC line rectification side,

$\left\{\begin{array}{c}{\mathrm{\&Delta;u}}_{R11}=\frac{{\mathrm{\&Delta;u}}_{R1}-{\mathrm{\&Delta;u}}_{R2}}{\sqrt{2}}\\ {\mathrm{\&Delta;i}}_{R11}=\frac{{\mathrm{\&Delta;i}}_{R1}-{\mathrm{\&Delta;i}}_{R2}}{\sqrt{2}}\end{array}\right.---\left(2\right)$

In formula, Δ u _r11with Δ i _r11be respectively line mode voltage and the line mould electric current of DC line rectification side.

(c2) in like manner, through type (2), calculates the line mode voltage Δ u of DC line inverter side _i11with line mould electric current Δ i _i11.

4. a kind of HVDC (High Voltage Direct Current) transmission line internal fault external fault recognition methods based on anti-row ripple according to claim 3, is characterized in that: the detailed process of described step (d) is:

(d1) utilize line mode voltage component and line mould electric current, calculate the anti-row ripple of voltage of DC line rectification side and inverter side.

$\left\{\begin{array}{c}{u}_{Rb}={\mathrm{\&Delta;u}}_{R11}-Z_C{\mathrm{\&Delta;i}}_{R11}\\ u_{Ib}={\mathrm{\&Delta;u}}_{I11}-Z_C{\mathrm{\&Delta;i}}_{I11}\end{array}\right.---\left(3\right)$

In formula, u _rbwith u _ibbe respectively the anti-row ripple of voltage of DC line rectification side and inverter side, Z _cfor DC line wave impedance;

(d2) at specific time T _din integration is carried out, shown in (4) to anti-row wave amplitude

$\left\{\begin{array}{c}{b}_R={\&Integral;}_{t_1}^{t_1+T_d}\left|u_{Rb}\right|dt\\ b_I={\&Integral;}_{t_2}^{t_2+T_d}\left|u_{Ib}\right|dt\end{array}\right.---\left(4\right)$

In formula (4), b _rand b _ithe amplitude integration of DC line rectification side and the anti-row ripple of inverter side in a period of time respectively, t ₁and t ₂be respectively the time that DC line rectification side and inverter side detect fault, T _dscope value be wherein, l is line length, and v is row velocity of wave propagation.

(d3) discretize is carried out to formula (4), can obtain

$\left\{\begin{array}{c}{b}_R=\underset{i=1}{\overset{Ns}{\&Sigma;}}\left|u_{Rb}\left(i\right)\right|\mathrm{\&Delta;}t\\ b_I=\underset{i=1}{\overset{Ns}{\&Sigma;}}\left|u_{Ib}\left(i\right)\right|\mathrm{\&Delta;}t\end{array}\right.---\left(5\right)$

In formula (5), i=1 represents after fault being detected first sampled point, and Ns is the sampling number in an integration window length, and Δ t is sampling interval.

5. a kind of HVDC (High Voltage Direct Current) transmission line internal fault external fault recognition methods based on anti-row ripple according to claim 4, is characterized in that: the detailed process of described step (e) is:

(e1) by the amplitude integrated value of DC line rectification side and the anti-row ripple of inverter side, larger integrated value is than upper less integrated value, and obtaining integration ratio R atio is:

$Ratio=\frac{max(b_R,b_I)}{min(b_R,b_I)}<\mathrm{\&epsiv;}---\left(6\right)$

In formula (6), ε is the threshold value of internal fault external fault identical criterion;

(e2) when integration ratio R atio is less than threshold value ε, failure judgement occurs on the line, otherwise failure judgement occurs in outside circuit.

6. a kind of HVDC (High Voltage Direct Current) transmission line internal fault external fault recognition methods based on anti-row ripple according to claim 5, is characterized in that: described threshold value ε is 5.

7. a kind of HVDC (High Voltage Direct Current) transmission line internal fault external fault recognition methods based on anti-row ripple according to claim 1, it is characterized in that: after described step (d), also comprise step (f) before step (e), the detailed process of described step (f) is: circuit Inverter Station obtained anti-row wave amplitude integral result is passed to converting plant.