CN105548681A - Method and device for measurement of power factors - Google Patents

Method and device for measurement of power factors Download PDF

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CN105548681A
CN105548681A CN201610071457.0A CN201610071457A CN105548681A CN 105548681 A CN105548681 A CN 105548681A CN 201610071457 A CN201610071457 A CN 201610071457A CN 105548681 A CN105548681 A CN 105548681A
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CN105548681B (en
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林纪秋
林琳
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R21/00—Arrangements for measuring electric power or power factor
    • G01R21/06—Arrangements for measuring electric power or power factor by measuring current and voltage

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  • Power Engineering (AREA)
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  • Measuring Phase Differences (AREA)
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Abstract

The present invention discloses a method and device for measurement of power factors. The method provided by the invention is a new method for directly obtaining power factors in corresponding storage units of a memory through adoption of sinusoidal voltage wave signals being converted from secondary current of a voltage transformer and a current transformer for measurement, which have the same phase, through a resistor and being processed by filtering harmonic wave interference of an electronic circuit and the like, namely by using the time difference when the sinusoidal voltage wave signals of the voltage transformer and the current transformer cross zero and taking the time difference as a memory address; and moreover, three devices for measurement of single-phase power factors are introduced, which utilize the method, are suitable for different occasions and have advance or time-delay instructions.

Description

A kind of measuring method of power factor and device thereof
Technical field
The present invention relates to a kind of measuring method and measurement mechanism thereof of power factor, particularly relate to a kind of power frequency single-phase power factor measuring method and measurement mechanism thereof of numerical monitor.
Background technology
Power factor it is one of important parameter in AC electric power systems.Immediately the power factor value, measuring each cycle is exactly the top priority of electric measurement equipment.Existing to be applied to the instrument and meter that electric power factor measures be two large classes substantially, and a class is the traditional pointer-type of employing, dial insrument carries out measuring and showing, and not only there is larger error, is also significantly not suitable with the requirement of modern digital; Another kind of is the instrument and meter adopting semiconductor components and devices, integrated circuit or single-chip microcomputer to form, and according to the different formation basic theory of signal, data processing method, the modernization measurement mechanism of configurations, be current application trend and the direction of digital development.But, in the measuring method of these modern instrument and meters, measurement mechanism, have plenty of by converting two-way input signal to square-wave signal through shaping circuit, square-wave signal is obtained a row pulse after XOR process, the DC voltage be directly proportional to phase differential is obtained again after rectifying and wave-filtering, complete phase-detection, then phase signal is carried out analog-digital conversion (ADC) and cos operation, obtain power factor value; Have plenty of and obtain power factor value with look-up table (cosine table) after trying to achieve phase difference angle; What have is then draw the powerfactorcosφ value of circuit by simulation multiplication and division circuit computing; Many methods in the employing phase detection techniques also had, the complexity of its application conditions, measurement range, measuring accuracy and hardware, software is all had nothing in common with each other, but final that obtain is all phase differential between electric current, voltage two signals and phase angle difference φ, to phase differential be converted to powerfactorcosφ value, one-chip computer is also needed to be undertaken calculating could really obtain concrete power factor value by the software program calling rated output factor again, this increases the calculated amount of single-chip microcomputer undoubtedly, take the service time of single-chip microcomputer more, reduce its work efficiency.In brief, at present power-factor measurement method or device all need the phase differential obtained by again changing into power factor value as aforesaid various indirectly mode, and this measurement result of power factor value cannot be obtained with directly settling at one go.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of power-factor measurement method directly, to settle at one go and measurement mechanism are provided, and need not carry out calculating by indirectly mode or by the software program that single-chip microcomputer calls rated output factor the net result obtaining power-factor measurement again, make the measurement of power frequency single-phase power factor more fast, accurately.
The technical solution used in the present invention is:
A kind of measuring method of power factor, it is applied to power-factor measurement device, and the voltage of this measurement mechanism input and electric current two signals are respectively the measurement voltage of same phase, the secondary current of current transformer converts to through resistance, and the sinusoidal voltage waveform signal of the process such as the humorous wave interference of filtering through electronic circuit, referred to as voltage transformer (VT), the quadratic sine waveform signal of current transformer, described measuring method comprises a power factor and calculates formula, data are obtained by this formulae discovery, and the storage to these data, application process, it comprises the following steps:
(1) power factor calculates formula:
In formula, f rthe rated frequency of electric system, the time value that mistiming during sine wave-shaped signal zero passage to the voltage of same phase, electric current when t is rated frequency counts to get, its unit is microsecond (us);
(2) single-phase power factor of usual power frequency in get 0 ~ 90 °, it corresponds to radian is rated frequency f rtime one-period T r1/4th, namely in formula, T rperiod time value when being rated frequency; Setting electric system rated frequency is f rtime in change to by 0 need the Hus time, then wherein H gets positive integer, and unit is us; Time t value by 1us, by increasing progressively 1us, until till Hus, substitute into the power factor t calculated in formula respectively one by one and calculate H at every turn value, this H value all comprise the numerical value of after radix point four; The H obtained value Data becomes time t value and power factor value conversion table according to the ascending sequential organization of time t value, is called for short " conversion table ";
(3) represent with 16 bits respectively till time t value being played Hus from 1us, the address successively as storer is also individual the H in conversion table correspondingly after the radix point of value, 4 bit digital adopt four binary-decimal binary-coded decimals stored in the storage unit of storer, storer adopts electrically erasable programmable ROM EEPROM, storage address capacity should be greater than 5K, each storage unit of a storer is a byte, can deposit 2 four binary-decimal binary-coded decimals namely 2 decimal numbers, the storage unit of two bytes deposits 4 decimal numbers, namely uses two 8K × 8 storeies, in order, first storer deposits one front two after the radix point of value in 4 tens digits, second storer deposits one latter two after the radix point of value in 4 tens digits; Wherein, corresponding 0th ~ 31 of t value in conversion table value is 1.0000, all to change into after 0.9999 4-digit number after radix point stored in the storage unit of appropriate address;
(4) mistiming during voltage and current two the signal zero passages obtained or perhaps time counting value are directly read the power factor value in storer respective memory unit as storage address and export.
A kind of measurement mechanism of power factor, a kind of power-factor measurement method described in application, the voltage of this measurement mechanism input and electric current two signals are respectively the measurement voltage of same phase, the secondary current of current transformer converts to through resistance, and the sinusoidal voltage waveform signal of the process such as the humorous wave interference of filtering through electronic circuit, referred to as voltage transformer (VT), the quadratic sine waveform signal of current transformer, the measurement mechanism of described power factor comprises first, two, three, four circuit units, 12 circuit unit and a time data application module, H in conversion table is stored with binary-coded decimal form the electrically erasable programmable ROM of two address wire parallel connections of value is connected in time data application module,
Wherein, the circuit structure of first and second circuit unit, components and parts and parameter thereof are identical, are the circuit that the square-wave signal that the voltage of input, Current Transformer Secondary sine wave-shaped signal convert Transistor-Transistor Logic level respectively to is exported,
First circuit unit comprises forward voltage follower U 1, there is the voltage comparator U of open-loop gain 4, resistance R 4, R 5, R 8, R 9, electric capacity C 1, diode D 1, diode D 2, have the Sheffer stroke gate U of Schmidt trigger 6and U 8, its connection is, the quadratic sine waveform signal access U of voltage transformer (VT) 1in-phase input end, U 1inverting input and U 1output terminal be connected, U 1output terminal and R 4one end be connected, R 4the other end and U 4in-phase input end be connected, R 5the other end and U 4inverting input be connected, U 4output terminal and R 8one end be connected, R 8the other end and R 9one end be connected, R 9the other end connecting analog ground, C 1and R 9parallel connection, R 8the other end and U 6two input ends be connected, diode D 1input end and U 6two input ends be connected, D 1output terminal connection+5V, D 2output terminal connect D 1input end, D 2input end connect digitally, U 6output terminal and U 8two input ends be connected, U 8output terminal be the output terminal of the first circuit unit, it exports the rectangular wave pulse signal of high level;
Second circuit unit comprises forward voltage follower U 3, there is the voltage comparator U of open-loop gain 5, resistance R 6, R 7, R 10, R 11, electric capacity C 2, diode D 3, diode D 4, have the Sheffer stroke gate U of Schmidt trigger 7and U 9, its connection is, the quadratic sine waveform signal access U of current transformer 3in-phase input end, U 3inverting input and U 3output terminal be connected, U 3output terminal and R 6one end be connected, R 6the other end and U 5in-phase input end be connected, R 7the other end and U 5inverting input be connected, U 5output terminal and R 10one end be connected, R 10the other end and R 11one end be connected, R 11the other end connecting analog ground, C 2and R 11parallel connection, R 10the other end and U 7two input ends be connected, diode D 3input end and U 7two input ends be connected, D 3output terminal connection+5V, D 4output terminal connect D 3input end, D 4input end connect digitally, U 7output terminal and U 9two input ends be connected, U 9output terminal be the output terminal of second circuit unit, it exports the rectangular wave pulse signal of high level;
Tertiary circuit unit is a zero-point voltage Circuit tuning unit, and it comprises voltage follower U 2, adjustable resistance R 1, resistance R 2, R 3, its connection is, adjustable resistance R 1one end connection+15V, other end connection-15V, adjustable resistance R 1adjustable end connect R 2one end, R 2the other end connect R 3one end, R 3the other end connecting analog ground, R 2the other end and U 2in-phase input end be connected, U 2inverting input and U 2output terminal be connected, U 2the output of output terminal be divided into two-way, the R of a road and the first circuit unit 5one end be connected, R 5the other end and U 4inverting input be connected, the R of another road and second circuit unit 7one end be connected, R 7the other end and U 5inverting input be connected;
4th circuit unit is by AND circuit U 10with OR circuit U 11form, its connection is, U 8output terminal connect U 10input end 1 iNand U 11input end 4 end pin; U 9output terminal connect U 11input end 2 iNand U 10input end 3 end pin;
12 circuit unit is one and carrys out advanced, the delayed circuit of indicated power factor by LED, and it comprises 4 bidirectional shift register U 16, two gate circuit U in hex inverter 13, U 14, resistance R 12, R 13, the green LED lamp D that an instructed voltage is advanced 5, the red LED lamp D that an indicator current is advanced 6with resistance R 14, electric capacity C 3and a pulse-delay unit; U 11the signal that exports of output terminal after the delay of this pulse-delay unit microsecond a little, be input to U 1611 pin, namely CP end, can judge with the precedence intercepted in voltage, both electric currents signal and make advanced or delayed red, green lamplight pointing, the components and parts of pulse-delay unit comprise an OR circuit U 21, two OR-NOT circuit U 23, U 24, a gate circuit U in hex inverter 22with resistance R 16, electric capacity C 5; The connection of pulse-delay unit is, U 11output terminal connect U respectively 21two input ends, U 21output terminal and R 16one end be connected, R 16the other end respectively with U 23an input end and C 5one end be connected, C 5the other end connect digitally, U 23another input end and U 24output terminal be connected, U 23output terminal and U 24an input end be connected, U 22input end and U 21output terminal be connected, U 22output terminal and U 24another input end be connected, U 24output terminal be the output terminal of pulse-delay unit, this output terminal is connected to U 1611 pin, namely CP end;
U in 12 circuit unit 163 pin and U 8output terminal be connected, U 165 pin and U 9output terminal be connected, U 161,9,10 pin and R 14one end be connected, R 14the other end be connected with+5V, R 14one end also and C 3one end be connected, C 3the other end connect digitally, U 1615 pin and U 13input end be connected, U 13output terminal and green LED lamp D 5negative pole be connected, D 5positive pole pass through R 12be connected with+5V, U 1613 pin and U 14input end be connected, U 14output terminal and red LED lamp D 6negative pole be connected, D 6positive pole pass through R 13be connected with+5V;
A time data application module, stores H in conversion table with binary-coded decimal form the electrically erasable programmable ROM of two address wire parallel connections of value is connected in this time data application module.This time data application module has two kinds of application forms: when the power-factor measurement device applying power-factor measurement method of the present invention is applied to the common survey occasion to accuracy of measurement requirement is lower, time data application module in measurement mechanism adopts measurement type time data application module, and device is called measurement type power-factor measurement device; When the power-factor measurement device applying power-factor measurement method of the present invention is applied to requiring that higher AC energy measures occasion to accuracy of measurement, time data application module in measurement mechanism adopts metering type time data application module, and device is called metering type power-factor measurement device;
When the power-factor measurement device applying power-factor measurement method of the present invention is applied to the common survey occasion to accuracy of measurement requirement is lower, time data application module in measurement mechanism adopts measurement type time data application module, it comprises the 5th, six, seven, eight, nine, ten, 11 circuit units;
5th circuit unit is 10MHZ pulses generation and very frequency circuit, and its 1MHZ Puled input exported is to the 6th circuit unit, and described 5th circuit unit comprises 10MHZ crystal oscillator, hex inverter U 30, decimal system synchronous counter U 29, resistance R 17, R 18, R 19, electric capacity C 6, its connection is, hex inverter U 30the 1st, contact resistance R between 2 pin 18, U 30the 3rd, connect R between 4 pin 19, U 30the 2nd, connect C between 3 pin 6, U 30the 1st, connect 10MHZ crystal oscillator, U between 4 pin 30the 2nd pin be connected with the 13rd pin, U 30the 12nd pin and decimal system synchronous counter U 29the 2nd pin CP end be connected, U 29the 1st, 7,9 and 10 pin by resistance R 17be connected with+5V power supply, U 29the 15th pin export the 1MHZ pulse of 10MHZ after very frequently, namely every microsecond is 1 pulse;
6th circuit unit is by four tetrad synchronous counter U 25, U 26, U 27, U 28one that is connected in sequence 16 binary time pulse counting circuits, what it exported is one by zero, increase progressively 16 bits of 1us, first, left side, i.e. U in these four counters at every turn 25the 14th pin be export 16 bits in lowest order, first, right side, i.e. U in these four counters 28the 11st pin be export 16 bits in most significant digit, its connection is, U 25the 15th pin connect U 26the 10th pin, U 26the 15th pin connect U 27the 10th pin, U 27the 15th pin connect U 28the 10th pin, four counters the 2nd pin CP hold and U 29the 15th pin be connected, four counters the 7th, 9 pin and U 25the 10th pin by resistance R 17be connected with+5V power supply, the 1st pin of four counters the U of end and the 4th circuit unit 11output terminal be connected;
7th circuit unit is a maintenance pulsing circuit, by 42 inputs and door U 35in AND circuit form; Described maintenance pulsing circuit is the time temporary sampling time data at least being kept 20ms, i.e. a cycle, and the condition of the setting of maintenance pulsing circuit is, keep pulse occur time should be in time counting circuit start counting after 5000us to 10ms between and as far as possible near this side of 5000us, hardware used when arranging this maintenance pulse is as far as possible few; After relatively, decimal number 5120 is selected according to aforementioned condition, its method to set up is, decimal number 5120 is converted to binary number, namely 0001,0100,0000,0000, represent that count value is decimal numeral 5120 when there is high level for the 11st, 13 of this binary number after time counting circuit starts simultaneously; Its connection is, U 351 pin and the 6th circuit unit in U 2712 pin be connected, U 352 pin and U 2814 pin be connected, U 353 pin are output terminals of the 7th circuit unit, the CP end of itself and the 9th circuit unit four registers is connected;
8th circuit unit be four being incorporated to-and go out 4 bidirectional shift register U of mode work 31, U 32, U 33, U 34the time data buffering circuit be in turn connected into, its connection is, four registers totally 16 data output ends are connected with 16 data input pin one_to_one corresponding of the 9th circuit unit; Four registers totally 16 data input pins are connected with 16 data output end one_to_one corresponding of the 6th circuit unit, four registers end and the 4th circuit unit U 11output terminal be connected, the CP of four registers end and the 4th circuit unit U 10output terminal be connected, the 9th, 10 pin contact resistance R of four registers 20one end, R 20the other end be connected with+5V power supply, R 20one end pass through C 7connect digitally;
9th circuit unit be four being incorporated to-and go out 4 bidirectional shift register U of mode work 36, U 37, U 38, U 39the time data holding circuit be in turn connected into, its connection is, 13 articles of address line end pin one_to_one corresponding of two storer parallel connections of four registers front 13 the sequentially with ten circuit units in totally 16 data output ends are connected, four registers totally 16 data input pins are connected with 16 data output end one_to_one corresponding of the 8th circuit unit, the CP end of four registers and the 7th circuit unit U 353 pin be connected, four registers the 1st, 9,10 pin and resistance R 20one end be connected, R 20the other end be connected with+5V power supply, R 20one end pass through C 7connect digitally;
Tenth circuit unit is the electrically erasable programmable ROM U of two 8K × 8 being arranged to read-only working method 40and U 41, in two Memory Storage Units, adopted the form of four binary-decimal binary-coded decimals stored in the H in conversion table value; Its connection is, U 40and U 41each 13 address wire A 0~ A 12in parallel and with front 13 data output ends of the 9th circuit unit sequentially one_to_one corresponding be connected, U 40and U 41the 20th, 22 pin pass through R 21connect digitally, U 40and U 41the 27th pin pass through R 22connect+5V power supply, U 40and U 41the data-out port line I/O of two storeies 0~ I/O 7totally 16 articles are connected with the 11 circuit unit correspondence;
11 circuit unit is used to show tested power factor value, it comprises BCD-seven-segment decoder/driver U 42, U 43, U 44, U 45; Current-limiting resistance R 23× 7, R 24× 7, R 25× 7, R 26× 7; Seven sections of common anode pole nixie display U 46, U 47, U 48, U 49; Wherein U 42, U 43, U 44, U 457,1,2,6 respective pin are totally 16 input ends holding pin to form the 11 circuit units, hold the data-out port line I/O of pin storer in parallel with two address wires of the tenth circuit unit respectively to connect one to one for these 16;
When the power-factor measurement device applying power-factor measurement method of the present invention is applied to requiring that higher AC energy (electric degree) measures occasion to accuracy of measurement, time data application module in measurement mechanism adopts metering type time data application module, and this module comprises an XOR gate U 101, its clock crystal oscillator frequency of a slice is the single-chip microcomputer 8031 i.e. U of 12MHZ 102, three eight rising edge d type flip flop U 103, U 104, U 105with the H stored with binary-coded decimal form in conversion table the storer U of two address wire parallel connections of value 40, U 41, single-chip microcomputer 8031 passes through P 0mouth expansion delivery outlet, utilize three eight rising edge d type flip flops to be connected with the storer of these two address wire parallel connections, the concrete connection of its circuit is: the U of the 4th circuit unit 10output terminal 1 oUTand U 101the 1st pin be connected, the U of the 4th circuit unit 11output terminal 2 oUTand U 101the 2nd pin and single-chip microcomputer U 102's i.e. U 102the 13rd pin and the 12 circuit unit in the U of pulse-delay unit 21two input ends be connected, U 101the 3rd pin and U 102's i.e. U 102the 12nd pin be connected, 8 end pin of single-chip microcomputer P0 mouth line are ascending by number, namely by P0.0 to P0.7 order sequentially correspondingly 8 data input pin 1D ~ 8D of eight rising edge d type flip flops individual with (1) be connected, 8 data input pin 1D ~ 8D of 8 data output end 1Q ~ 8Q of (1) individual eight rising edge d type flip flops, eight rising edge d type flip flops individual with (2) are correspondingly connected, 8 data input pin 1D ~ 8D sequentially 8 data input pin 1D ~ 8D parallel connection of eight rising edge d type flip flops individual with (1) correspondingly of (3) individual eight rising edge d type flip flops is connected, 8 data output end 1Q ~ 8Q of (3) individual eight rising edge d type flip flops and the address line end pin of low eight of (1) individual storer ascending by number, namely sequentially connect correspondingly by the order of A0 to A7,1Q ~ 5Q in 8 data output ends of (2) individual eight rising edge d type flip flops and the address line end pin of high five of (1) individual storer ascending by number, namely sequentially connect correspondingly by the order of A8 to A12,16th pin of single-chip microcomputer, namely end pin and the 11st pin of three eight rising edge d type flip flops, i.e. CP end pin are connected, the 1st pin of the 27th pin of single-chip microcomputer, i.e. P2.6 pin and (1) individual eight rising edge d type flip flops, namely end pin is connected, the 28th pin of single-chip microcomputer, i.e. P2.7 pin simultaneously and (2), the 1st pin of (3) individual eight rising edge d type flip flops, namely end pin is connected, and the address line end pin A0 ~ A12 of (2) individual storer and the address line end pin A0 ~ A12 of (1) individual storer carries out connection in parallel correspondingly, the address date of 16 bits of two bytes that setting single-chip microcomputer P0 mouth exports is arranged in order to most significant digit by lowest order, divide secondary, each byte delivers to 8 data input pins of eight rising edge d type flip flops, wherein first time delivers to the address that the data of (1) individual eight rising edge d type flip flops 8 data input pins are high bytes, till this address date plays sixteen bit from the 9th of this 16 bit, successively, 9th 1D corresponding to eight rising edge d type flip flops, 8 data input pins, tenth corresponds to 2D, sixteen bit corresponds to 8D, the data delivering to (3) individual eight rising edge d type flip flops 8 data input pins are for the second time addresses of low byte, this address date plays till the 8th from first of this 16 bit, successively first 1D corresponding to eight rising edge d type flip flops, 8 data input pins, second correspond to 2D ... 8th corresponds to 8D, 13 binary storage device address codes that the two byte address data sent of point secondary arrange from low to high in order at the data output end interruption-forming one of (3), (2) individual eight rising edge d type flip flops and the address end pin A0 ~ A12 of the storer of the data-out port 1Q ~ 8Q of (3) individual eight rising edge d type flip flops and data-out port 1Q ~ 5Q and two address wire parallel connection of (2) individual eight rising edge d type flip flops has annexation one to one.
Described metering type time data application module also comprises peripheral component and circuit, the circuit that the circuit that the clock crystal oscillator that the 8D latch 74LS373 that peripheral component and circuit comprise band ternary output is connected outer for the sheet of expansion program storage circuit with single-chip microcomputer 8031, frequency are 12MHZ is connected with single-chip microcomputer 8031, BCD-seven-segment decoder/driver, current-limiting resistance and seven sections of common anode pole LED nixie displaies for needed for instant playback power factor data connect.
Described metering type time data application module also comprises a simple computing formula and software program, carry out simple computation by the software in program storage to the time data sampled immediately to read the power factor value in respective memory unit as storage address to obtain more precise time data and to show, the steps include:
function and the using method of the gate control position GATE of application single-chip microcomputer timer measure XOR gate output terminal and U 1013 pin output to single-chip microcomputer U 10212 pin namely high level, i.e. positive pulse width and measure the U of the 4th circuit unit 11output terminal 2 oUToutput to single-chip microcomputer U 10213 pin namely high level, i.e. positive pulse width, and respectively read T0 and T1 count value after close T0 and T1 respectively;
the value of T0 and T1 is substituted into formula calculate, after the value later to the radix point in acquired results rounds up, obtain 16 bits of two bytes;
the high byte of 16 bits is delivered to the data output end of (1) individual eight rising edge d type flip flops;
the low byte of 16 bits is delivered to the data output end of (3) individual eight rising edge d type flip flops and the value on (1) individual eight rising edge d type flip flop data output ends is delivered on the data output end of (2) individual eight rising edge d type flip flops simultaneously, the address of 16 bits of this two byte as the storer of two address wire parallel connections is directly read out the power factor numerical value in its corresponding storage unit and give instant playback;
t0 and T1 is reset;
return after 1 is put to T0 and T1, wait for next test loop.
When adopting metering type time data application module in described device, an amendment is done to the interlock circuit of this metering type time data application module and then makes it become measurement type time data application module: namely, disconnect U 11output terminal 2 oUTwith single-chip microcomputer U 10213rd pin, namely between connecting line, simultaneously need not again according to the in claim 4 individual step calculates, as long as according to the in claim 4 after directly reading the count value of T0 step is carried out, and returns, wait for next test loop after finally only also putting 1 to T0 again to T0 clearing.This change makes the measurement type power-factor measurement device being applied to common survey occasion more simple and convenient.
The present invention adopts above technical scheme, use the secondary current of measurement voltage, current transformer through resistance convert to and through sinusoidal voltage waveform signal, the i.e. voltage transformer (VT) of process, the quadratic sine waveform signal input measurement device of current transformer such as the humorous wave interference of filtering of electronic circuit, eliminate wave form distortion and the noise of measured signal, ensure sine wave-shaped signal zero crossing accurately, calculate by calculating formula to power factor, the power factor numerical value obtained be compiled into table and the value storage in this table in memory, then voltage is passed through in using, the pulse collection produced during the accurate zero passage of electric current two signals is to the poor time counting value in other words conj.or perhaps of correct time, and the method directly reading the power factor value in storer respective memory unit using this mistiming or time counting value as storage address all needs to be calculated by indirectly mode again to overcome in current power factor measuring method, obtain the deficiency of power factor value, apply single-chip microcomputer the frequency of electrical network is carried out to instant tracing detection, implemented to correct to its minor shifts occurred simultaneously, guarantee that the single-phase power factor of each cycle is with numerical value output accurately, by numeral method, and instant indicated power factor is advanced or delayed, not only accurate but also facilitate.The present invention has obvious technical advantage, can promote further developing and producing significant social economic effect of power-factor measurement technology undoubtedly.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in further details;
The structured flowchart of measurement mechanism when Fig. 1 the present invention adopts measurement type time data application module;
One of circuit diagram of the measurement mechanism of a kind of power factor of Fig. 2 the present invention;
The circuit diagram two of the measurement mechanism of a kind of power factor of Fig. 3 the present invention;
The circuit diagram three of the measurement mechanism of a kind of power factor of Fig. 4 the present invention;
The circuit diagram four of the measurement mechanism of a kind of power factor of Fig. 5 the present invention;
The waveform schematic diagram of A, B, C, D, E, F, G each point in Fig. 6 measurement mechanism of the present invention;
The schematic flow sheet of singlechip application programs during metering type time data application module is adopted in Fig. 7 measurement mechanism of the present invention.
Embodiment
As shown in one of Fig. 1 to 7, the single-phase power factor measuring method of a kind of power frequency of the present invention, be applied to power-factor measurement device, and the voltage of this measurement mechanism input and electric current two signals be respectively the measurement voltage of same phase, the secondary current of current transformer through resistance convert to and the sinusoidal voltage waveform signal of the process such as the humorous wave interference of filtering through electronic circuit, referred to as the quadratic sine waveform signal of voltage transformer (VT), current transformer, it comprises, a kind of single-phase power factor measuring method of power frequency and the measurement mechanism of application the method.The single-phase power factor measuring method of its power frequency is comprised a power factor and calculates formula, obtained data by this formulae discovery and these data organizations are become conversion table, method stored in storer and application.The power-factor measurement device of its application the method comprises first, second, third and fourth circuit unit, the 12 circuit unit and a time data application module, stores H in conversion table with binary-coded decimal form the electrically erasable programmable ROM of two address wire parallel connections of value is connected in time data application module; This time data application module has two kinds of application forms: when the power-factor measurement device applying power-factor measurement method of the present invention is applied to the common survey occasion to accuracy of measurement requirement is lower, time data application module in measurement mechanism adopts measurement type time data application module, and device is called measurement type power-factor measurement device; When the power-factor measurement device applying power-factor measurement method of the present invention is applied to requiring that higher AC energy (electric degree) measures occasion to accuracy of measurement, time data application module in measurement mechanism adopts metering type time data application module, and device is called metering type power-factor measurement device; In order to sharpen understanding, the example being 50HZ below in conjunction with power system frequency is further described in detail.
The single-phase power factor measuring method of power frequency comprises the method that a power factor calculates formula, obtained data by this formulae discovery and data organization is become conversion table, applies stored in storer etc., its step:
(1) according to electrotechnics knowwhy, the voltage of same phase and the phase differential of electric current or phase angle difference with represent, as long as record mistiming t (us) and cycle T or f, just can obtain phasing degree, that is:
Phase differential or phase angle difference cosine be power factor, that is:
In (1) above, (2) two formulas, t (us) is the time difference that samples or perhaps mistiming count value; T is the cycle, f is mains frequency (hertz/sec);
F f during rated frequency r(hertz/sec) represents, T T rrepresent, t (us) still represents with t, then the voltage of same phase during rated frequency and the phase differential of electric current or phase angle difference for:
Phase differential during rated frequency or phase angle difference cosine also can be expressed as following formula, namely power factor calculate formula (time unification in formula is microsecond), when rated frequency is 50HZ, then have:
(2) single-phase power factor of usual power frequency in get 0 ~ 90 °, it corresponds to radian is rated frequency f rtime one-period T r1/4th, namely in formula, T rperiod time value when being rated frequency; Setting electric system rated frequency is f rtime in change to by 0 need the Hus time, then time t value by 1us, by increasing progressively 1us at every turn, until till 5000us, substitute into respectively the t that power factor calculates in formula (4) one by one and calculate 5000 value, these 5000 value be all comprise the numerical value of after radix point four; 5000 that obtain value Data becomes time t value and power factor value conversion table according to the ascending sequential organization of time t value, is called for short " conversion table ";
(3) till the time t value represented with 16 bits being played 5000us from 1us, successively as storer address and correspondingly 5000 in conversion table after the radix point of value, 4 bit digital adopt four binary-decimal binary-coded decimals stored in the storage unit of storer, storer adopts electrically erasable programmable ROM EEPROM2864, each storage unit of a storer is a byte, 2 four binary-decimal binary-coded decimals namely 2 decimal numbers can be deposited, the storage unit of two bytes deposits 4 decimal numbers, use the storer of two 8K × 8, in order, (1) individual storer deposits one front two after the radix point of value in 4 tens digits, (2) individual storer deposits one latter two after the radix point of value in 4 tens digits; Wherein, corresponding 0th ~ 31 of t value in conversion table value is 1.0000, all to change into after 0.9999 4-digit number after radix point stored in the storage unit of appropriate address; Final like this what show is all numerical value after radix point, just need not consider the setting of radix point again, simplify circuit; Although change 0.9999 into 1.0000 can bring error, this error can accept;
(4) mistiming during voltage and current two the signal zero passages obtained or perhaps time counting value are directly read the power factor value in storer respective memory unit as storage address and export.
The power-factor measurement device of an application the method, and the voltage of this measurement mechanism input and electric current two signals be respectively the measurement voltage of same phase, the secondary current of current transformer through resistance convert to and the sinusoidal voltage waveform signal of the process such as the humorous wave interference of filtering through electronic circuit, referred to as the quadratic sine waveform signal of voltage transformer (VT), current transformer, it comprises first, second, third and fourth circuit unit, 12 circuit unit and a time data application module, store 5000 in conversion table with binary-coded decimal form the electrically erasable programmable ROM of two address wire parallel connections of value is connected in time data application module; This time data application module has two kinds of application forms: when the power-factor measurement device applying power-factor measurement method of the present invention is applied to the common survey occasion to accuracy of measurement requirement is lower, time data application module in measurement mechanism adopts measurement type time data application module, and device is called measurement type power-factor measurement device; When the power-factor measurement device applying power-factor measurement method of the present invention is applied to requiring that higher AC energy (electric degree) measures occasion to accuracy of measurement, time data application module in measurement mechanism adopts metering type time data application module, and device is called metering type power-factor measurement device;
As shown in Figure 2, wherein, the circuit structure of first and second circuit unit, components and parts and parameter thereof are identical, the circuit that the square-wave signal that voltage, the Current Transformer Secondary sine wave-shaped signal of input convert Transistor-Transistor Logic level respectively to is exported, voltage of its input, Current Transformer Secondary sine wave-shaped signal respectively via the forward voltage follower access in first and second circuit unit have open-loop gain voltage comparator and after connect Transistor-Transistor Logic level conversion interface circuit.The quadratic sine waveform signal of measurement voltage transformer (VT) is input to 1 of the first circuit unit iNend, the quadratic sine waveform signal of Verification of Measuring Current Transformer is input to 1 of second circuit unit iNend; The output terminal of first and second circuit unit is then divided into three tunnels the square-wave signal of the Transistor-Transistor Logic level converted to respectively and exports: the signal of the first circuit unit exports and is divided into three tunnels, and a road is input to 1 of the 4th circuit unit iNend and U 101 iNend, a road is input to 4 pin and the U of the 4th circuit unit 114 pin, also have a road to be input to register U in the 12 circuit unit 16the 3rd pin; The signal of second circuit unit exports and is divided into three tunnels, and a road is input to 2 of the 4th circuit unit iNend and U 112 iNend, a road is input to 3 pin and the U of the 4th circuit unit 103 pin, also have a road to be input to register U in the 12 circuit unit 16the 5th pin;
First circuit unit comprises with amplifier OP-07 as forward voltage follower U 1, with OP-37 as the voltage comparator U with open-loop gain 4, resistance R 4, R 5, R 8, R 9, electric capacity C 1, diode D 1, D 2, also include U 6and U 8, U 6and U 8be the gate circuit had in 42 input nand gate 74LS132 of Schmidt trigger respectively, its connection is, the quadratic sine waveform signal access U of voltage transformer (VT) 1in-phase input end that is 1 iNend, U 1inverting input be connected with its output terminal, U 1output terminal and resistance R 4one end be connected, R 4the other end and U 4in-phase input end be connected, resistance R 5the other end and U 4inverting input that is 2 iNend pin is connected, U 4output terminal and resistance R 8one end be connected, R 8the other end and R 9one end be connected, R 9the other end connecting analog ground, electric capacity C 1and R 9parallel connection, C 1and R 9access in parallel uses the filter capacity of energy intensifier circuit, R 8the other end also and U 6two input ends be connected, diode D 1input end and U 6two input ends be connected, D 1output terminal connection+5V, D 2output terminal connect D 1input end, D 2input end connect digitally, U 6output terminal and U 8two input ends be connected, U 8output terminal be the output terminal of the first circuit unit, its output terminal the respectively with four circuit unit U 101 iNend, U 114 pin and the 12 circuit unit in U 16the 3rd pin be connected;
Second circuit unit comprises with amplifier OP-07 as forward voltage follower U 3, with OP-37 as the voltage comparator U with open-loop gain 5, resistance R 6, R 7, R 10, R 11, electric capacity C 2, diode D 3, D 4, also include U 7and U 9, U 7and U 9be the gate circuit had in 42 input nand gate 74LS132 of Schmidt trigger respectively, its connection is, the quadratic sine waveform signal access U of current transformer 3in-phase input end that is 1 iNend, U 3inverting input be connected with its output terminal, U 3output terminal and resistance R 6one end be connected, R 6the other end and U 5in-phase input end be connected, resistance R 7the other end and U 5inverting input that is 2 iNend pin is connected, U 5output terminal and resistance R 10one end be connected, R 10the other end and R 11one end be connected, R 11the other end connecting analog ground, electric capacity C 2and R 11parallel connection, C 2and R 11access in parallel uses the filter capacity of energy intensifier circuit, R 10the other end also and U 7two input ends be connected, diode D 3input end and U 7two input ends be connected, D 3output terminal connection+5V, D 4output terminal connect D 3input end, D 4input end connect digitally, U 7output terminal and U 9two input ends be connected, U 9output terminal be the output terminal of second circuit unit, its output terminal the respectively with four circuit unit U 112 iNend, U 103 pin and the 12 circuit unit in U 16the 5th pin be connected;
As shown in Figure 2, tertiary circuit unit is a zero-point voltage Circuit tuning unit, and it comprises with amplifier OP-07 as voltage follower U 2, adjustable resistance R 1, resistance R 2, R 3, its connection is, adjustable resistance R 1one end connection+15V, other end connection-15V, R 1adjustable end connect R 2one end, R 2the other end connect R 3one end, R 3the other end connecting analog ground, R 2the other end and U 2in-phase input end be connected, U 2inverting input and U 2output terminal be connected, U 2output terminal be divided into two-way, a road and the first circuit unit R 5one end be connected, R 5the other end and U 4inverting input that is 2 iNbe connected, another road and second circuit unit R 7one end be connected, R 7the other end and U 5inverting input that is 2 iNbe connected;
As shown in Figure 2, the 4th circuit unit is by 42 inputs and an AND circuit U in door integrated circuit 74LS08 10with an OR circuit U in 42 inputs or door integrated circuit 74LS32 11form, it has four input ends 1 iN, 2 iN, 3 pin, 4 pin and two output terminals 1 oUTwith 2 oUT, the 4th circuit unit input end 1 iNnamely be U 10input end 1 iN, namely the 4th circuit unit input end 3 pin is U 10input end 3 pin, the 4th circuit unit input end 2 iNnamely be U 11input end 2 iN, namely the 4th circuit unit input end 4 pin is U 11input end 4 pin, two output terminals are respectively U 10output terminal 1 oUTand U 11output terminal 2 oUT;
The connection of four input ends of the 4th circuit unit is, U 8output terminal and U 10input end 1 iNand U 114 pin be connected; U 9output terminal and U 11input end 2 iNand U 103 pin be connected;
As shown in Fig. 3 or Fig. 5, two output terminals of the 4th circuit unit have two kinds of connections, and as shown in Figure 3, when the 4th circuit unit is applied in the measurement mechanism adopting measurement type time data application module, its connection is, the 4th circuit unit U 10output terminal 1 oUTwith four U be connected successively in the 8th circuit unit 31, U 32, U 33, U 34the 11st pin, namely CP end be connected, the 4th circuit unit U 11output terminal 2 oUTbe divided into three tunnels, four U be connected successively in the respectively with six circuit unit 25, U 26, U 27, U 28the 1st pin, namely end is connected, with four U be connected successively in the 8th circuit unit 31, U 32, U 33, U 34the 1st pin, namely end is connected, and input end, the i.e. U of pulse-delay unit in the 12 circuit unit 211,2 pin be connected;
As shown in Figure 5, when the 4th circuit unit is applied in the measurement mechanism adopting metering type time data application module, its connection is, the 4th circuit unit U 10output terminal 1 oUTwith the gate circuit U of in 74LS86 XOR gate 1011 pin be connected, the 4th circuit unit U 11output terminal 2 oUTbe divided into three tunnels, respectively and U 1012 pin be connected, and single-chip microcomputer 8031, i.e. U 102's namely the 13rd pin is connected, and input end, the i.e. U of pulse-delay unit in the 12 circuit unit 211,2 pin be connected;
As shown in Figure 2, the 12 circuit unit is one and carrys out advanced, the delayed circuit of indicated power factor by LED, and it mainly comprises a U 16, i.e. 4 bidirectional shift register 74LS194, two gate circuit U in 74LS04 phase inverter 13, U 14, current-limiting resistance R 12, R 13, the green LED LED D that an instructed voltage is advanced 5, the red light emitting diodes LED D that an indicator current is advanced 6with resistance R 14, electric capacity C 3and a pulse-delay unit; This pulse-delay unit is the 4th circuit unit U 11output terminal 2 oUTu is input to again after the delay of the signal microsecond a little exported 1611 pin, namely CP end, can judge with the precedence intercepted in voltage, both electric currents signal and make advanced or delayed red, green lamplight pointing, the components and parts of pulse-delay unit comprise, 42 input or door integrated circuit 74LS32 in a gate circuit U 21, 74L,S02 42 inputs two gate circuit U in rejection gate integrated circuit 23, U 24, a gate circuit U in 74LS04 hex inverter integrated circuit 22with resistance R 16, electric capacity C 5; The connection of pulse-delay unit is, U 11output terminal 2 oUTand U 211,2 pin be connected, U 21output terminal 3 pin and phase inverter U 22input end and resistance R 16one end be connected, U 22output terminal and U 242 pin be connected, R 16the other end and U 231 pin and electric capacity C 5one end be connected, C 5the other end connect digitally, U 232 pin and U 24output terminal 3 pin be connected, U 23output terminal 3 pin and U 241 pin be connected, U 24output terminal 3 pin be the output terminal of pulse-delay unit, it is connected to U 1611 pin, namely CP end;
In addition, the U in the 12 circuit unit 163 pin and U 8output terminal be connected, U 165 pin and U 9output terminal be connected, U 161,9,10 pin and resistance R 14one end be connected, R 14the other end be connected with+5V, R 14one end also with electric capacity C 3one end be connected, C 3the other end connect digitally, U 1615 pin and U 13input end be connected, U 13output terminal and the advanced green LED LED D of instructed voltage 5negative pole be connected, D 5positive pole by resistance R 12be connected with+5V, U 1613 pin and U 14input end be connected, U 14output terminal and the advanced red light emitting diodes LED D of indicator current 6negative pole be connected, D 6positive pole by resistance R 13be connected with+5V;
The simplified process that 12 circuit unit uses LED to carry out advanced, the delayed work of indicated power factor is: as shown in the oscillogram of A, D, F point in Fig. 2 and Fig. 6, U 11output terminal 2 oUTexport voltage, electric current synthesis square wave after pulse-delay unit postpones a little at its output terminal and U 24output terminal 3 pin export be the square waveform postponing only to count microsecond, when advanced voltage rectangular waveform is by U 8output terminal arrive U 163 pin time, simultaneously by U 11output terminal 2 oUTthe square waveform exported outputs to U from its output terminal after pulse-delay unit postpones 1611 pin and CP hold pin, utilize the front rising edge of the square waveform of this slight delay the voltage rectangular waveform signal arrived slightly before by U 163 pin deliver to U 1615 pin, the voltage rectangular waveform signal of its high level makes phase inverter U 13output low level, thus lighted the advanced green LED LED D of instructed voltage 5although, electric current rectangular waveform signal may slightly late after just can by U 9output terminal arrive U 165 pin, but be later than U 16cP hold delayed pulse on pin, be delayed with regard to indicating current power factor like this; When electric current is ahead of voltage, this course of work is the same, but that light in circuit is red diode D 6, it is advanced for indicating current power factor;
When the power-factor measurement device applying power-factor measurement method of the present invention is applied to the common survey occasion to accuracy of measurement requirement is lower, time data application module in measurement mechanism adopts measurement type time data application module, it comprises the 5th, six, seven, eight, nine, ten, 11 circuit units;
As shown in Figure 3, the 5th circuit unit is 10MHZ pulses generation and very frequency circuit, and this circuit unit comprises 10MHZ crystal oscillator, 74LS04 hex inverter U 30, 74LS160 decimal system synchronous counter U 29, resistance R 17, R 18, R 19, electric capacity C 6, its connection is, U 30the 1st, contact resistance R between 2 pin 18, the 3rd, connect R between 4 pin 19, the 2nd, connect C between 3 pin 6, the 1st, connect 10MHZ crystal oscillator between 4 pin, the 2nd pin is connected with the 13rd pin, the 12nd pin and decimal system synchronous counter U 29the 2nd pin CP end be connected, U 29the 1st, 7,9 and 10 pin by resistance R 17be connected with+5V power supply, the 15th pin exports the 1MHZ pulse of 10MHZ after very frequently, and namely every microsecond is 1 pulse, U 29the output of the 15th pin be connected to the 2nd pin, i.e. the CP end of four synchronous counters of the 6th circuit unit;
As shown in Figure 3, the 6th circuit unit is by four 74LS161 tetrad synchronous counter U 25, U 26, U 27, U 28one that is connected in sequence 16 binary time pulse counting circuits, what it exported is one by zero, increase progressively 16 bits of 1us, first, left side, i.e. U in these four counters at every turn 25the 14th pin be export 16 bits in lowest order, first, right side, i.e. U in these four counters 28the 11st pin be export 16 bits in most significant digit, its connection is, U 25the 15th pin connect U 26the 10th pin, U 26the 15th pin connect U 27the 10th pin, U 27the 15th pin connect U 28the 10th pin, four counters the 2nd pin CP hold and U 29the 15th pin be connected, four counters the 7th, 9 pin and U 25the 10th pin by resistance R 17be connected with+5V power supply, the 1st pin of four counters end and the 4th circuit unit U 11output terminal 2 oUTbe connected, four counters totally 16 data output ends connect one to one 16 data input pins of the 8th circuit unit, namely U 25, U 26, U 27, U 28each counter the 14th, 13,12,11 pin successively one_to_one corresponding access U 31, U 32, U 33, U 34each register the 3rd, 4,5,6 pin;
As shown in Figure 3, the 7th circuit unit is a maintenance pulsing circuit, is inputted and door U by 74L,S08 42 35in AND circuit form; Described maintenance pulsing circuit is the time temporary sampling time data at least being kept 20ms, i.e. a cycle, and the condition of the setting of maintenance pulsing circuit is, keep pulse occur time should be in time counting circuit start counting after 5000us to 10ms between and as far as possible near this side of 5000us, hardware used when arranging this maintenance pulse is as far as possible few; After relatively, decimal number 5120 is selected according to aforementioned condition, its method to set up is, decimal number 5120 is converted to binary number, namely 0001,0100,0000,0000, represent that count value is decimal numeral 5120 when there is high level for the 11st, 13 of this binary number after time counting circuit starts simultaneously; Its connection is, U 351 pin and 16 bits that export of the 6th circuit unit in the 11st, i.e. U 2712 pin be connected, U 352 pin and 16 bits in the 13rd, i.e. U 2814 pin be connected, U 353 pin as the 7th circuit unit output terminal time counting circuit start counting after 5120us time produces and exports maintenance pulse, its Puled input to the 9th circuit unit four registers CP hold;
As shown in Figure 3, the 8th circuit unit be four being incorporated to-and go out 74LS194 i.e. 4 bidirectional shift register U of mode work 31, U 32, U 33, U 34the time data buffering circuit be in turn connected into, its 4 bidirectional shift registers also can adopt the integrated circuit (IC) chip such as eight d type flip flops to replace, its connection is, four counters of the 6th circuit unit totally 16 data output ends connect one to one 16 data input pins of the 8th circuit unit, namely U 25, U 26, U 27, U 28each counter the 14th, 13,12,11 pin successively one_to_one corresponding access U 31, U 32, U 33, U 34each register the 3rd, 4,5,6 pin; Totally 16 data output ends of four registers are connected, namely U with 16 data input pin one_to_one corresponding of the 9th circuit unit 31, U 32, U 33, U 34each register the 15th, 14,13,12 pin successively one_to_one corresponding access U 36, U 37, U 38, U 39each register the 3rd, 4,5,6 pin; Four register U 31, U 32, U 33, U 34the 9th, 10 pin contact resistance R 20one end, resistance R 20the other end be connected with+5V power supply, R 20one end by electric capacity C 7connect digitally; Four register U 31, U 32, U 33, U 34the 1st pin the U of end and the 4th circuit unit 11output terminal 2 oUTbe connected; Four register U 31, U 32, U 33, U 34the 11st pin CP hold and the U of the 4th circuit unit 10output terminal 1 oUTbe connected;
As shown in Figure 3, the 9th circuit unit be four being incorporated to-and go out 74LS194 i.e. 4 bidirectional shift register U of mode work 36, U 37, U 38, U 39the time data holding circuit be in turn connected into, its 4 bidirectional shift registers also can adopt the integrated circuit (IC) chip such as eight d type flip flops to replace, and its connection is, four register U 36, U 37, U 38, U 39the 1st pin end, 9,10 pin and resistance R 20one end be connected, R 20the other end be connected with+5V power supply, R 20one end by electric capacity C 7connect digitally; 11st pin CP end of four registers and output terminal, the i.e. U of the 7th circuit unit 353 pin be connected; Front 13 output terminals in 16 data output ends of four registers, namely from U 36the 15th pin rise, according to priority, the 14th, 13,12 pin, connecing down is U 37the 15th, 14,13,12 pin, then to connect down be U 38the 15th, 14,13,12 pin, be finally U 39the 15th pin, respectively the successively with ten circuit unit, i.e. (1) individual storer U 40, (2) individual storer U 4113 address wire A in parallel 0~ A 12one_to_one corresponding is connected;
As shown in Figure 4, the tenth circuit unit is the electrically erasable programmable ROM EEPROM2864 of 8K × 8 of two the address wire parallel connections being arranged to read-only working method, storer (1), i.e. U 40with storer (2), i.e. U 4113 articles of address wires in parallel and with front 13 data output ends of the 9th circuit unit sequentially one_to_one corresponding be connected, adopted the form of four binary-decimal binary-coded decimals stored in 5000 in conversion table in two Memory Storage Units value; Its connection is, U 40and U 41the 20th, 22 pin are by resistance R 21connect digitally, U 40and U 41the 27th pin by resistance R 22connect+5V power supply, U 40and U 4113 address wire A in parallel 0~ A 1213 output terminals, i.e. U before in 16 data output ends of the successively with nine circuit unit 36, U 37, U 3815,14,13,12 pin and U 3915 pin one_to_one corresponding be connected, U 40and U 41the data-out port line I/O of two storeies 0~ I/O 7totally 16 articles are connected with the 11 circuit unit;
As shown in Figure 4, the 11 circuit unit adopts the display circuit of the conventional device composition such as BCD-seven-segment decoder/driver, current-limiting resistance, LED seven-segment numeric indicator to carry out the tested power factor of instant playback value is by 74LS47 and BCD-seven-segment decoder/driver U in the present embodiment 42, U 43, U 44, U 45, current-limiting resistance R 23× 7, R 24× 7, R 25× 7, R 26× 7, seven sections of common anode pole LED nixie display U 46, U 47, U 48, U 49composition digital-scroll technique circuit, its storer (1), i.e. U in parallel with two address wires of the tenth circuit unit 40with storer (2), i.e. U 41the method of attachment of data-out port line I/O be, U 40data-out port line the 11st, 12,13,15 pin, i.e. I/O 0, I/O 1, I/O 2, I/O 3successively and U 427,1,2,6 pin be connected, its export and at U 46upper display be first tens digit stored in totally two store bytes of two storeies of address wire parallel connection, U 40data-out port line the 16th, 17,18,19 pin, i.e. I/O 4, I/O 5, I/O 6, I/O 7successively and U 437,1,2,6 pin be connected, its export and at U 47upper display be second tens digit stored in totally two store bytes of two storeies of address wire parallel connection, U 41data-out port line the 11st, 12,13,15 pin, i.e. I/O 0, I/O 1, I/O 2, I/O 3successively and U 447,1,2,6 pin be connected, its export and at U 48upper display be the 3rd tens digit stored in totally two store bytes of two storeies of address wire parallel connection, U 41data-out port line the 16th, 17,18,19 pin, i.e. I/O 4, I/O 5, I/O 6, I/O 7successively and U 457,1,2,6 pin be connected, its export and at U 49upper display be the 4th tens digit stored in two store bytes of two storeies of address wire parallel connection; U 42, U 43, U 44, U 45with current-limiting resistance R 23× 7, R 24× 7, R 25× 7, R 26× 7 and seven-segment numeric indicator U 46, U 47, U 48, U 49connection belong to knowledge.
As shown in Fig. 2,3,4,6, measurement mechanism, i.e. its concise and to the point course of work of measurement type power-factor measurement device of above-mentioned employing measurement type time data application module be, when from the first circuit unit voltage follower U 1in-phase input end 1 iNinput and from U 1output terminal export voltage sinusoidal waveform signal A-1 be converted into TTL rectangular waveform signal from U 8output terminal output to U 101 iN, U 114 pin, U 163 pin while, from U 11output terminal 2 oUTalso high level square-wave signal is exported to 1 pin of 1 pin of the 6th circuit unit four counters, the 8th circuit unit four registers and U 211,2 pin, the 6th circuit unit start counting, the 8th circuit unit setup time data temporary storage, the pulse-delay unit start time postpone; Subsequently from second circuit cell voltage follower U 3in-phase input end 1 iNinput and from U 3output terminal export current sinusoidal waveform signal A-2 be converted into TTL rectangular waveform signal from U 9output terminal output to U 103 pin, U 112 iN, U 165 pin while, from U 10output terminal 1 oUTexport high level square-wave signal to the 8th circuit unit four registers the 11st pin, i.e. CP end, utilize U 10the front rising edge of the high level square wave exported is the 8th circuit unit U 31, U 32, U 33, U 34totally 16 data input pins on time data deliver on its 16 data-out ports or perhaps deliver to the 9th circuit unit U 36, U 37, U 38, U 39totally 16 data input pins on, when the 6th circuit unit, namely the time pulse-scaling circuit start after 5120us time, output terminal, the i.e. U of the 7th circuit unit 353 pin export keep pulses to the 9th circuit unit U 36, U 37, U 38, U 39the 11st pin, namely CP end, utilize U 353 pin export and keep the front rising edge of high level of pulses the 9th circuit unit U 36, U 37, U 38, U 39totally 16 data input pins on time data to deliver on its data-out port and to keep a cycle and 20ms, due to electrically erasable programmable ROM (1), the i.e. U of 8K × 8 in parallel with two address wires being arranged to read-only working method of the tenth circuit unit of 13 data output ends before in these 16 data-out ports of the 9th circuit unit 40with storer (2), i.e. U 4113 address wires sequentially one_to_one corresponding be connected, i.e. U 36in 15,14,13,12 pin and two storer U 40and U 41parallel connection 13 address wires in A 0, A 1, A 2, A 3sequentially one_to_one corresponding is connected, U 37in 15,14,13,12 pin and parallel connection 13 address wires in A 4, A 5, A 6, A 7sequentially one_to_one corresponding is connected, U 38in 15,14,13,12 pin and parallel connection 13 address wires in A 8, A 9, A 10, A 11sequentially one_to_one corresponding is connected, U 39in 15 pin and A in 13 in parallel address wires 12correspondence is connected, and two storer U 40and U 41storage unit in adopted the form of four binary-decimal binary-coded decimals stored in 5000 in conversion table value, so be kept pulse to deliver to the 9th circuit unit U 36, U 37, U 38, U 3916 data-out ports on time data just become the storer U of the tenth circuit unit two address wire parallel connections 40and U 41address and the power factor value directly read in its respective memory unit, achieve the measurement to power factor; Almost with the 6th, while eight circuit units start working, the carrying out advanced, the delayed work of indicated power factor by LED and also carrying out of the 12 circuit unit, its simplified process as previously mentioned.Above-mentioned described be the situation of voltage leading current, if its course of work is the same during the situation of electric current leading voltage, only the color of pilot lamp becomes redness, shows that the power factor when electric current leading voltage is advanced.The power factor value applied when electrical network rated frequency 50HZ measured by measurement type power-factor measurement device is very accurately.
But well-known, the mains frequency in actual motion can not be stable, and it can produce the deviation that technical manual allows.According to relevant regulations, standard frequency range should be rated frequency f to measurement class of accuracy r99% ~ 101%, i.e. 0.99f r≤ f≤1.01f r, rated frequency f be should be to protection class of accuracy r96% ~ 102%, i.e. 0.96f r≤ f≤1.02f r.Therefore when skew appears in mains frequency, application measurement type power-factor measurement device is measured power factor value and also will be produced certain error, and this error is completely adequate for common instrument measurement and display and for the power factor controlling at scene and power factor compensation; But be applied to and accuracy of measurement is required that higher AC energy (electric degree) is but unallowable when measuring occasion, will use metering type power-factor measurement device, the time data application module in device adopts metering type time data application module.
When skew occurs mains frequency, mains frequency f f during skew cy(hertz/sec) represents, T T cyrepresent, t (us) uses t cy(us) represent, then the voltage of same phase and the phase differential of electric current or phase angle difference during mains frequency skew for:
In formula above-mentioned (3),
remove the rightmost item in (3), namely have:
When mains frequency f is rated frequency f rtime, the T in (3-1) rbe one with the rated frequency f in (3) rcorresponding ratings, also be one and f rcorresponding ratings, the t therefore in (3), (3-1) two formulas with be directly proportional, " time t value and the power factor value conversion table " of the present embodiment is rated for 50HZ according to frequency just and calculates under constant condition, so be in the respective memory unit that reads of storage address with t when mains frequency is 50HZ value is also just accurate;
In formula (5), the mains frequency f when offseting in actual motion cybe not 50HZ but with rated frequency f rduring the deviation having regulation to allow, T cytoo with T rthere is deviation, so with between also have deviation, assuming that in (3-1) and (5) identical, then equal on the right of two formulas:
Can know from (3-2) formula and find out, when with when not waiting, t and t cyvalue also unequal, now use t cygo in extraction table corresponding as the time t value in " time t value and the power factor value conversion table " worked out when being 50HZ according to rated frequency value, still use t in other words cygo to read in storer respective memory unit as storage address also be certain to during value to occur error in data, because the data worked out in " time t value and power factor value conversion table " store when the storage content in this storer is 50HZ according to rated frequency.
Use following straightforward procedure can correct this mistake: the phase differential of the same phase voltage immediately sampled and electric current or phase angle difference remove when rated frequency 50HZ then the t obtained is gone in extraction table corresponding as the time t value in " time t value and power factor value conversion table " value; Or directly wushu (3-2) carries out conversion and obtains t, then go using t as storage address to read in the storer respective memory unit that stores according to the data in " time t value and power factor value conversion table " value; No matter be any method, its result is all the same, that is:
Above formula (6) shows, obtains a phasing degree when mains frequency is offset required sampling time t cypass through adjustment in other words conj.or perhaps after " conversion ", just obtain an identical phasing degree the sampling time t required when mains frequency is specified, finally goes to read its data in advance is stored in respective memory unit according to " time t value and the power factor value conversion table " worked out during electrical network rated frequency 50HZ in storer using this sampling time value t as storage address error in data would not be there is during value; In formula be called conversion factor or commutation factor, work as T cy=T rtime, mains frequency is rated frequency, and conversion factor equals 1.Now give a concrete illustration, such as, the mistiming sampled when mains frequency 50.5HZ is 1000us, can apply above-mentioned method and carry out error correction: (one). cycle during known 50.5HZ is 19801.9802us, and application of formula (5) tries to achieve angular difference be 18.18 °, the cycle again during known 50HZ is 20000us, and the angle of each us is 0.018 °, this phase angle difference remove in 0.018 ° for 18.18 °, the t obtained is 1010us, and the time t value in " time t value and power factor value conversion table " that this 1010us works out when mains frequency is 50HZ is gone in extraction table corresponding the result that value obtains is accurately, obviously, if direct 1000us goes to extract in this table value will obtain the result of mistake; (2). cycle during known 50.5HZ is 19801.9802us, cycle during 50HZ is 20000us, the t that application of formula (6) obtains after carrying out adjusting in other words conj.or perhaps " conversion " is 1010us, then goes to read its data in advance is stored in respective memory unit for " time t value and the power factor value conversion table " worked out during 50HZ according to mains frequency in storer using the time value t after this correction as storage address error in data would not be there is during value.
Measurement mechanism of the present invention input be the measurement voltage of same phase, Current Transformer Secondary electric current converts to through resistance, and the sinusoidal voltage waveform signal of the process such as the humorous wave interference of filtering through electronic circuit, respectively through the tertiary circuit unit in device and zero-point voltage Circuit tuning and first, the process of two circuit unit waveform changing circuits, sine wave-shaped signal is divided into equal upper, lower two half-waves also export with rectangle square wave, the high level of this rectangle square wave, i.e. positive pulse part and low level, namely zero level part is completely equal in time, that is it is high, the low level time respectively accounts for the half of one-period time, therefore in apparatus of the present invention to T cycle length rand T cymeasurement all only measure high level, i.e. the positive pulse part of its rectangle square wave, hereinafter or in the computing related to just to explain no longer separately beyond illustrating, according to the standard frequency variation range that aforesaid regulation allows, its maximum frequency range is rated frequency f r96% ~ 102%, the time value T of its corresponding half period when mains frequency is rated frequency 50HZ rfor 10000us, the time value T of its corresponding half period when mains frequency generation offset variation cYpermission change maximum magnitude between 9804 ~ 10417us.Need to remark additionally a bit, above involved t and t cywhen the time value as sampling or counting, its implication is the same, one is the time value of sampling when representing rated frequency or counting, another is the time value of sampling when representing that rated frequency offsets or counting, difference is, t also has the function representing address code in conversion table and storer, therefore one represents not to be with bottom right to mark t, and another is to mark t with bottom right cyrepresent.
According to error correction method design ap-plication discussed above in accuracy of measurement being required to the metering type time data application module in the power-factor measurement device that high field is closed, this module comprises a gate circuit U in 42 input XOR gate integrated circuit 74LS86 101, its clock crystal oscillator frequency of a slice is the single-chip microcomputer 8031 i.e. U of 12MHZ 102, three 7,4LS,377 eight rising edge d type flip flop U 103, U 104, U 105, wherein (1) individual be U 104, (2) individual be U 105, (3) individual be U 103, 5000 in conversion table are stored with binary-coded decimal form storer EEPROM2864 and U of two address wire parallel connections of value 40, U 41, wherein (1) individual storer is U 40, (2) individual storer is U 41, single-chip microcomputer U 102pass through P 0mouth expansion delivery outlet, utilizes three 74LS377 and U 103, U 104, U 105with the storer U of two address wire parallel connections 40, U 41connect, here U 103, U 104, U 105be regarded as the external RAM unified addressing of single-chip microcomputer, single-chip microcomputer U 102output control signal is its software used can with reference to the introduction in " MCS-51 series monolithic Practical Interface technology the 86th page of Li Hua chief editor publishing house of BJ University of Aeronautics & Astronautics in August, 1993 ", and the concrete connection of its circuit is: the 4th circuit unit U 10output terminal 1 oUTwith XOR gate U 101the 1st pin be connected, the U of the 4th circuit unit 11output terminal 2 oUTwith XOR gate U 101the 2nd pin and single-chip microcomputer U 102's the U of the pulse-delay unit namely in the 13rd pin and the 12 circuit unit 21two input ends 1,2 pin be connected, XOR gate U 101the 3rd pin and single-chip microcomputer U 102's namely the 12nd pin is connected, single-chip microcomputer U 1028 of P0 mouth line end pin ascending, the order of namely pressing P0.0 to P0.7 sequentially individual eight rising edge d type flip flop U with (1) correspondingly by number 1048 data input pin 1D ~ 8D be connected, (1) individual eight rising edge d type flip flop U 1048 data output end 1Q ~ 8Q individual eight rising edge d type flip flop U with (2) correspondingly 1058 data input pin 1D ~ 8D be connected, (3) individual eight rising edge d type flip flop U 1038 data input pin 1D ~ 8D sequentially individual eight rising edge d type flip flop U with (1) correspondingly 1048 data input pin 1D ~ 8D parallel connection be connected, (3) individual eight rising edge d type flip flop U 1038 data output end 1Q ~ 8Q and (1) individual storer U 40the address line end pin of low eight by number ascending, namely sequentially connect correspondingly by the order of A0 to A7, (2) individual eight rising edge d type flip flop U 1058 data output ends in 1Q ~ 5Q and (1) individual storer U 40the address line end pin of high five by number ascending, namely sequentially connect correspondingly by the order of A8 to A12, due to storer U 40and U 41its memory capacity only has 8K, (2) individual eight rising edge d type flip flop U 1058 data output ends in also remain three end pin 6Q ~ 8Q, can vacant need not; Single-chip microcomputer U 102the 16th pin, namely end pin and three eight rising edge d type flip flop U 103, U 104, U 105the 11st pin, namely CP hold pin be connected, single-chip microcomputer U 10227th pin, i.e. P2.6 end pin and (1) individual eight rising edge d type flip flop U 104the 1st pin, namely end pin is connected, single-chip microcomputer U 10228th pin, i.e. P2.7 end pin simultaneously and (2), (3) individual eight rising edge d type flip flop U 105, U 103the 1st pin, namely end pin is connected, (2) individual storer U 41address line end pin A0 ~ A12 and (1) individual storer U 40address line end pin A0 ~ A12 carry out connection in parallel correspondingly; Setting single-chip microcomputer U 102the address date of 16 bits of two bytes that exports of P0 mouth be arranged in order to most significant digit by lowest order, 8 data input pins that point secondary, each byte deliver to eight rising edge d type flip flops, wherein first time delivers to (1) individual eight rising edge d type flip flop U 104the data of 8 data input pins are addresses of high byte, till this address date plays sixteen bit from the 9th of this 16 bit, successively, the 9th correspond to (1) individual eight rising edge d type flip flop U 1048 data input pins 1D, the tenth correspond to 2D ... sixteen bit corresponds to 8D; Second time delivers to (3) individual eight rising edge d type flip flop U 103the data of 8 data input pins are addresses of low byte, this address date from first of this 16 bit play till the 8th, successively, first correspond to (3) individual eight rising edge d type flip flop U 103the 1D of 8 data input pins, second correspond to 2D ... 8th corresponds to 8D; The two byte address data that point secondary is sent are at (3), (2) individual eight rising edge d type flip flop U 103, U 10513 binary storage device address codes arranging in order from low to high of data output end interruption-forming one and U 103data-out port 1Q ~ 8Q and U 105the storer U of data-out port 1Q ~ 5Q and two address wire parallel connection 40, U 41address end pin A0 ~ A12 have annexation one to one; This module also comprises other peripheral component and circuit, the circuit that the clock crystal oscillator that the 8D latch 74LS373 that these peripheral components and circuit comprise band ternary output is connected outer for the sheet of expansion program storage circuit with single-chip microcomputer 8031, frequency are 12MHZ is connected with single-chip microcomputer, the circuit connected for BCD-seven-segment decoder/driver, current-limiting resistance and the LED seven-segment numeric indicator needed for instant playback power factor data etc., these all belong to known technical know-how, introduce no longer in detail and draw in the drawings.
Now in conjunction with error correction method discussed above and the power-factor measurement device of employing metering type time data application module that connected into, and with reference to shown in one of figure 2,4,5,6,7, just can clearly understand, first and second circuit unit waveform changing circuit process of process, again by the 4th circuit unit U 10output terminal 1 oUTand U 11output terminal 2 oUToutput to XOR gate U respectively 101two input ends 1,2 pin after through U 101the sample time signal t that output terminal 3 pin exports cyaccess single-chip microcomputer end pin, its deration of signal is exactly the time counting value that timer/counter T0 reads, simultaneously U 8output terminal export voltage rectangular ripple and U 9output terminal export the wavelength-division of electric current rectangle not by or door U 114 pin and 2 iNthrough its output terminal 2 after pin input oUTthe voltage exported, both electric currents or gate signal access single-chip microcomputer end pin, its deration of signal is exactly the time counting value that timer/counter T1 reads; Therefore, formula (6) becomes:
t = t c y × T r T c y = T 0 × T r T 1 - T 0 - - - ( 7 )
In formula, t cythe time value that mistiming during sine wave-shaped signal zero passage to the voltage of same phase, electric current when being the skew of electrical network rated frequency counts, it is exactly the count value of T0, T cythe time value in cycle when being the skew of electrical network rated frequency, it is exactly the count difference value of (T1-T0); To the time counting value that the mistiming of the sine wave-shaped signal zero passage of the voltage of same phase, electric current counts when t is electrical network rated frequency 50HZ; T rbeing period time value during electrical network rated frequency 50HZ, is a known value;
Again formula (7) is simplified and obtains:
t = T 0 × T r T 1 - T 0 - - - ( 8 )
Further, required time data can be read and the calculation procedure applying single-chip microcomputer realizes quick, easy power-factor measurement and display by utilizing the function of the gate control position GATE of single-chip microcomputer timer and using method and two timer/counters T0, T1, " program circuit schematic diagram " as shown in Figure 7, the steps include:
function and the using method of the gate control position GATE of application single-chip microcomputer timer measure XOR gate output terminal and U 1013 pin output to single-chip microcomputer U 10212 pin namely high level, i.e. positive pulse width and measure the U of the 4th circuit unit 11output terminal 2 oUToutput to single-chip microcomputer U 10213 pin namely high level, i.e. positive pulse width, and respectively read T0 and T1 count value after close T0 and T1 respectively;
the value of T0 and T1 is substituted into formula calculate, after the value later to the radix point in acquired results rounds up, obtain 16 bits of two bytes;
the high byte of 16 bits is delivered to (1) individual eight rising edge d type flip flop U 104data output end;
the low byte of 16 bits is delivered to (3) individual eight rising edge d type flip flop U 103data output end and simultaneously (1) individual eight rising edge d type flip flop U 104value on data output end delivers to (2) individual eight rising edge d type flip flop U 105data output end on, using the storer U of 16 bits of this two byte as two address wire parallel connections 40, U 41address directly read out the power factor numerical value in its corresponding storage unit and give instant playback;
t0 and T1 is reset;
return after 1 is put to T0 and T1, wait for next test loop.
Interlock circuit in metering type time data application module in above-mentioned measurement mechanism is made a simple modification will make metering type time data application module become the measurement type time data application module of another kind of form: namely, disconnects U 11output terminal 2 oUTwith single-chip microcomputer U 102the 13rd pin, namely between connecting line, simultaneously need not again according to above-mentioned steps in formula calculate, as long as after directly reading the count value of T0 according to above-mentioned steps carry out, return after finally only also 1 being put to T0 again to T0 clearing, wait for next test loop; This change makes measurement type power-factor measurement device more simply small and exquisite compared with aforesaid measurement type power-factor measurement device, increases a kind of application mode more again.
Ground wire in the metallic shield casing that the power-factor measurement device installed by method of the present invention and requirement should be placed in ground connection and on the electronic circuit board of device should by the appropriate ground connection of regulation in case external interference.The secondary current that two input signals of measurement mechanism are respectively measurement voltage transformer (VT) and Verification of Measuring Current Transformer through resistance convert to and through the proportional sine wave-shaped signal of process, its waveforms amplitude and the primary current such as the humorous wave interference of filtering of electronic circuit, the quadratic sine waveform signal of the quadratic sine waveform signal summation current transformer of this two input signals, i.e. voltage transformer (VT) should use the signal shielding cable of shielding layer grounding and aviation connection-peg to be linked into the first circuit unit forward voltage follower U of measurement mechanism respectively 1in-phase input end 1 iNwith second circuit unit forward voltage follower U 3in-phase input end 1 iN.The signal recommendation Authorization Notice No. being input to the second circuit unit forward voltage follower in this power-factor measurement device be the cable punching full-shield electronic current transducer secondary side of CN204558230U involve the quadratic sine waveform signal exported after interference waits process through electronic circuit filtering is humorous; Be input to the signal of the signal recommendation ceramic electronic voltage transformer secondary side of the first circuit unit forward voltage follower in this power-factor measurement device, this secondary side signal be equally need through electronic circuit filtering humorous involve interference wait process after export quadratic sine waveform signal, this be used for ceramic electronic voltage transformer secondary side signal carry out filtering humorous involve interference wait process electronic circuit the same with the electronic circuit used in cable punching full-shield electronic current transducer secondary side.
In the circuit of apparatus of the present invention, amplifier U 1, U 2, U 3, U 4, U 5positive and negative power end all connect ± 15V working power, R 3the other end, R 9the other end, R 11the other end equal connecting analog ground; In addition, the positive supply termination+5V working power of other integrated circuit, its negative power end or ground connection termination are digitally; In the circuit of apparatus of the present invention, R 4=R 5=R 6=R 7, R 8=R 10, R 9=R 11, R 18=R 19, C 1=C 2.
Here is the simple signal table of time t value and power factor value conversion table.During as needed a complete conversion table, the power factor in literary composition of the present invention can be utilized to calculate formula (4) and to calculate voluntarily.

Claims (6)

1. the measuring method of a power factor, it is applied to power-factor measurement device, and the voltage of this measurement mechanism input and electric current two signals are respectively the measurement voltage of same phase, the secondary current of current transformer converts to through resistance, and the sinusoidal voltage waveform signal of the process such as the humorous wave interference of filtering through electronic circuit, referred to as voltage transformer (VT), the quadratic sine waveform signal of current transformer, it is characterized in that: described measuring method comprises a power factor and calculates formula, data are obtained by this formulae discovery, and the storage to these data, application process, it comprises the following steps:
(1) power factor calculates formula:
In formula, f rthe rated frequency of electric system, the time value that mistiming during sine wave-shaped signal zero passage to the voltage of same phase, electric current when t is rated frequency counts to get, its unit is microsecond (us);
(2) single-phase power factor of usual power frequency in get 0 ~ 90 °, it corresponds to radian is rated frequency f rtime one-period T r1/4th, namely in formula, T rperiod time value when being rated frequency; Setting electric system rated frequency is f rtime in change to by 0 need the Hus time, then wherein H gets positive integer, and unit is us; Time t value by 1us, by increasing progressively 1us, until till Hus, substitute into the power factor t calculated in formula respectively one by one and calculate H at every turn value, this H value all comprise the numerical value of after radix point four; The H obtained value Data becomes time t value and power factor value conversion table according to the ascending sequential organization of time t value, is called for short " conversion table ";
(3) represent with 16 bits respectively till time t value being played Hus from 1us, the address successively as storer is also individual the H in conversion table correspondingly after the radix point of value, 4 bit digital adopt four binary-decimal binary-coded decimals stored in the storage unit of storer, storer adopts electrically erasable programmable ROM EEPROM, storage address capacity should be greater than 5K, each storage unit of a storer is a byte, deposit 2 four binary-decimal binary-coded decimals namely 2 decimal numbers, the storage unit of two bytes deposits 4 decimal numbers, namely uses two 8K × 8 storeies, in order, first storer deposits one front two after the radix point of value in 4 tens digits, second storer deposits one latter two after the radix point of value in 4 tens digits; Wherein, corresponding 0th ~ 31 of t value in conversion table value is 1.0000, all to change into after 0.9999 4-digit number after radix point stored in the storage unit of appropriate address;
(4) mistiming during voltage and current two the signal zero passages obtained or perhaps time counting value are directly read the power factor value in storer respective memory unit as storage address and export.
2. the measurement mechanism of a power factor, apply the measuring method of a kind of power factor described in claim 1, the voltage of this measurement mechanism input and electric current two signals are respectively the measurement voltage of same phase, the secondary current of current transformer converts to through resistance, and the sinusoidal voltage waveform signal of the process such as the humorous wave interference of filtering through electronic circuit, referred to as voltage transformer (VT), the quadratic sine waveform signal of current transformer, it is characterized in that: it comprises first, two, three, four circuit units, 12 circuit unit and a time data application module, H in conversion table is stored with binary-coded decimal form the electrically erasable programmable ROM of two address wire parallel connections of value is connected in time data application module,
Wherein, the circuit structure of first and second circuit unit, components and parts and parameter thereof are identical, are the circuit that the square-wave signal that the voltage of input, Current Transformer Secondary sine wave-shaped signal convert Transistor-Transistor Logic level respectively to is exported,
First circuit unit comprises with amplifier OP-07 as forward voltage follower U 1, with OP-37 as the voltage comparator U with open-loop gain 4, resistance R 4, R 5, R 8, R 9, electric capacity C 1, diode D 1, diode D 2, also include U 6and U 8, U 6and U 8be the gate circuit had in 42 input nand gate 74LS132 of Schmidt trigger respectively, its connection is, the quadratic sine waveform signal access U of voltage transformer (VT) 1in-phase input end that is 1 iN, U 1inverting input and U 1output terminal be connected, U 1output terminal and resistance R 4one end be connected, resistance R 4the other end and U 4in-phase input end be connected, resistance R 5the other end and U 4inverting input that is 2 iNbe connected, U 4output terminal and resistance R 8one end be connected, R 8the other end and R 9one end be connected, R 9the other end connecting analog ground, electric capacity C 1and R 9parallel connection, R 8the other end and U 6two input ends be connected, diode D 1input end and U 6two input ends be connected, D 1output terminal connection+5V, diode D 2output terminal connect D 1input end, D 2input end connect digitally, U 6output terminal and U 8two input ends be connected, U 8output terminal be the output terminal of the first circuit unit, it exports the rectangular wave pulse signal of high level;
Second circuit unit comprises with amplifier OP-07 as forward voltage follower U 3, with OP-37 as the voltage comparator U with open-loop gain 5, resistance R 6, R 7, R 10, R 11, electric capacity C 2, diode D 3, diode D 4, also include U 7and U 9, U 7and U 9be the gate circuit had in 42 input nand gate 74LS132 of Schmidt trigger respectively, its connection is, the quadratic sine waveform signal access U of current transformer 3in-phase input end that is 1 iN, U 3inverting input and U 3output terminal be connected, U 3output terminal and resistance R 6one end be connected, resistance R 6the other end and U 5in-phase input end be connected, resistance R 7the other end and U 5inverting input that is 2 iNbe connected, U 5output terminal and resistance R 10one end be connected, R 10the other end and R 11one end be connected, R 11the other end connecting analog ground, electric capacity C 2and R 11parallel connection, R 10the other end and U 7two input ends be connected, diode D 3input end and U 7two input ends be connected, D 3output terminal connection+5V, diode D 4output terminal connect D 3input end, D 4input end connect digitally, U 7output terminal and U 9two input ends be connected, U 9output terminal be the output terminal of second circuit unit, it exports the rectangular wave pulse signal of high level;
Tertiary circuit unit is a zero-point voltage Circuit tuning unit, and it comprises with amplifier OP-07 as voltage follower U 2, adjustable resistance R 1, resistance R 2, R 3, its connection is, adjustable resistance R 1one end connection+15V, other end connection-15V, adjustable resistance R 1adjustable end contact resistance R 2one end, R 2other end contact resistance R 3one end, R 3the other end connecting analog ground, R 2the other end and U 2in-phase input end be connected, U 2inverting input and U 2output terminal be connected, U 2the output of output terminal be divided into two-way, the resistance R of a road and the first circuit unit 5one end be connected, R 5the other end and U 4inverting input that is 2 iNbe connected, the resistance R of another road and second circuit unit 7one end be connected, R 7the other end and U 5inverting input that is 2 iNbe connected;
4th circuit unit is by 42 inputs and an AND circuit U in door integrated circuit 74LS08 10with an OR circuit U in 42 inputs or door integrated circuit 74LS32 11form, its connection is, U 8output terminal connect U 10input end 1 iNand U 11input end 4 end pin; U 9output terminal connect U 11input end 2 iNand U 10input end 3 end pin;
12 circuit unit is one and carrys out advanced, the delayed circuit of indicated power factor by LED, and it comprises a U 16, i.e. 4 bidirectional shift register 74LS194, two gate circuit U in 74LS04 phase inverter 13, U 14, current-limiting resistance R 12, R 13, the green LED LED D that an instructed voltage is advanced 5, the red light emitting diodes LED D that an indicator current is advanced 6with resistance R 14, electric capacity C 3and a pulse-delay unit; U 11output terminal 2 oUTthe signal exported is input to U after the delay of this pulse-delay unit microsecond a little 1611 pin, i.e. CP end, can judge with the precedence intercepted in voltage, both electric currents signal and make advanced or delayed red, green lamplight pointing, the components and parts of pulse-delay unit comprise a gate circuit U in 42 inputs or door integrated circuit 74LS32 21, 74L,S02 42 inputs two gate circuit U in rejection gate integrated circuit 23, U 24, a gate circuit U in 74LS04 hex inverter integrated circuit 22with resistance R 16, electric capacity C 5; The connection of pulse-delay unit is, U 11output terminal 2 oUTconnect U respectively 21two input ends 1,2 pin, U 21output terminal 3 pin and resistance R 16one end be connected, R 16the other end respectively with U 23input end 1 pin and electric capacity C 5one end be connected, C 5the other end connect digitally, U 23another input end 2 pin and U 24output terminal 3 pin be connected, U 23output terminal 3 pin and U 24input end 1 pin be connected, phase inverter U 22input end and U 21output terminal 3 pin be connected, U 22output terminal and U 24another input end 2 pin be connected, U 24output terminal be the output terminal of pulse-delay unit, U 24output terminal 3 pin be connected to U 1611 pin, namely CP end;
U in 12 circuit unit 163 pin and U 8output terminal be connected, U 165 pin and U 9output terminal be connected, U 161,9,10 pin and resistance R 14one end be connected, R 14the other end be connected with+5V, R 14one end also with electric capacity C 3one end be connected, C 3the other end connect digitally, U 1615 pin and U 13input end be connected, U 13output terminal and the advanced green LED LED D of instructed voltage 5negative pole be connected, D 5positive pole by resistance R 12be connected with+5V, U 1613 pin and U 14input end be connected, U 14output terminal and the advanced red light emitting diodes LED D of indicator current 6negative pole be connected, D 6positive pole by resistance R 13be connected with+5V;
A time data application module, this time data application module has two kinds of application forms: when power-factor measurement device is applied to the common survey occasion to accuracy of measurement requirement is lower, time data application module in measurement mechanism adopts measurement type time data application module, and device is called measurement type power-factor measurement device; When the power-factor measurement device of applied power factor measuring method is applied to requiring that higher AC energy measures occasion to accuracy of measurement, time data application module in measurement mechanism adopts metering type time data application module, and device is called metering type power-factor measurement device;
When power-factor measurement device is measurement type power-factor measurement device, time data application module in its device adopts measurement type time data application module, it comprises the 5th, six, seven, eight, nine, ten, 11 circuit units;
5th circuit unit is 10MHZ pulses generation and very frequency circuit, and its 1MHZ Puled input exported is to the 6th circuit unit, and described 5th circuit unit comprises 10MHZ crystal oscillator, 74LS04 hex inverter U 30, 74LS160 decimal system synchronous counter U 29, resistance R 17, R 18, R 19, electric capacity C 6, its connection is, 74LS04 hex inverter U 30the 1st, contact resistance R between 2 pin 18, U 30the 3rd, connect R between 4 pin 19, U 30the 2nd, connect C between 3 pin 6, U 30the 1st, connect 10MHZ crystal oscillator, U between 4 pin 30the 2nd pin be connected with the 13rd pin, U 30the 12nd pin and 74LS160 decimal system synchronous counter U 29the 2nd pin CP end be connected, U 29the 1st, 7,9 and 10 pin by resistance R 17be connected with+5V power supply, U 29the 15th pin export the 1MHZ pulse of 10MHZ after very frequently, namely every microsecond is 1 pulse;
6th circuit unit is by four 74LS161 tetrad synchronous counter U 25, U 26, U 27, U 28one that is connected in sequence 16 binary time pulse counting circuits, what it exported is one by zero, increase progressively 16 bits of 1us, first, left side, i.e. U in these four counters at every turn 25the 14th pin be export 16 bits in lowest order, first, right side, i.e. U in these four counters 28the 11st pin be export 16 bits in most significant digit, its connection is, U 25the 15th pin connect U 26the 10th pin, U 26the 15th pin connect U 27the 10th pin, U 27the 15th pin connect U 28the 10th pin, four counters the 2nd pin CP hold and U 29the 15th pin be connected, four counters the 7th, 9 pin and U 25the 10th pin by resistance R 17be connected with+5V power supply, the 1st pin of four counters the U of end and the 4th circuit unit 11output terminal 2 oUTbe connected;
7th circuit unit is a maintenance pulsing circuit, is inputted and door integrated circuit U by 74L,S08 42 35in AND circuit form, its connection is, U 351 pin and 16 bits that export of the 6th circuit unit in the 11st, i.e. U 2712 pin be connected, U 352 pin and 16 bits in the 13rd, i.e. U 2814 pin be connected, U 353 pin as the 7th circuit unit output terminal time counting circuit start counting after 5120us time produces and export maintenance pulse, its Puled input is held to the CP of four bidirectional shift registers of the 9th circuit unit;
8th circuit unit be four being incorporated to-and go out 74LS194 i.e. 4 bidirectional shift register U of mode work 31, U 32, U 33, U 34the time data buffering circuit be in turn connected into, its connection is, four counters of the 6th circuit unit totally 16 data output ends connect one to one 16 data input pins of the 8th circuit unit, namely U 25, U 26, U 27, U 28each counter the 14th, 13,12,11 pin successively one_to_one corresponding access U 31, U 32, U 33, U 34each register the 3rd, 4,5,6 pin; Totally 16 data output ends of four registers are connected, namely U with 16 data input pin one_to_one corresponding of the 9th circuit unit 31, U 32, U 33, U 34each register the 15th, 14,13,12 pin successively one_to_one corresponding access U 36, U 37, U 38, U 39each register the 3rd, 4,5,6 pin; Four register U 31, U 32, U 33, U 34the 9th, 10 pin contact resistance R 20one end, resistance R 20the other end be connected with+5V power supply, R 20one end by electric capacity C 7connect digitally; Four register U 31, U 32, U 33, U 34the 1st pin the U of end and the 4th circuit unit 11output terminal 2 oUTbe connected; Four register U 31, U 32, U 33, U 34the 11st pin CP hold and the U of the 4th circuit unit 10output terminal 1 oUTbe connected;
9th circuit unit be four being incorporated to-and go out 74LS194 i.e. 4 bidirectional shift register U of mode work 36, U 37, U 38, U 39the time data holding circuit be in turn connected into, its connection is, four register U 36, U 37, U 38, U 39the 1st pin end, 9,10 pin and resistance R 20one end be connected, R 20the other end be connected with+5V power supply, R 20one end by electric capacity C 7connect digitally; 11st pin CP end of four registers and output terminal, the i.e. U of the 7th circuit unit 353 pin be connected; Front 13 output terminals in 16 data output ends of four registers, namely from U 36the 15th pin rise, according to priority, the 14th, 13,12 pin, connecing down is U 37the 15th, 14,13,12 pin, then to connect down be U 38the 15th, 14,13,12 pin, be finally U 39the 15th pin, respectively the successively with ten circuit unit, i.e. (1) individual storer U 40, (2) individual storer U 4113 address wire A in parallel 0~ A 12one_to_one corresponding is connected;
Tenth circuit unit is the electrically erasable programmable ROM EEPROM2864 of 8K × 8 of two the address wire parallel connections being arranged to read-only working method, storer (1), i.e. U 40with storer (2), i.e. U 4113 articles of address wires in parallel and and front 13 data output ends of the 9th circuit unit sequentially one_to_one corresponding be connected, adopted the form of four binary-decimal binary-coded decimals individual stored in the H in conversion table in two Memory Storage Units value; Its connection is, U 40and U 41the 20th, 22 pin are by resistance R 21connect digitally, U 40and U 41the 27th pin by resistance R 22connect+5V power supply, U 40and U 4113 address wire A in parallel 0~ A 1213 output terminals, i.e. U before in 16 data output ends of the successively with nine circuit unit 36, U 37, U 3815,14,13,12 pin and U 3915 pin one_to_one corresponding be connected, U 40and U 41the data-out port line I/O of two storeies 0~ I/O 7totally 16 articles are connected with the 11 circuit unit;
11 circuit unit is used to the tested power factor of instant playback value, it comprises BCD-seven-segment decoder/driver U 42, U 43, U 44, U 45; Current-limiting resistance R 23× 7, R 24× 7, R 25× 7, R 26× 7; Seven sections of common anode pole LED nixie display U 46, U 47, U 48, U 49; The input end of the 11 circuit unit is connected with the data-out port line I/O of the storer of two address wire parallel connections of the tenth circuit unit; Its method of attachment is, U 40data-out port line the 11st, 12,13,15 pin, i.e. I/O 0, I/O 1, I/O 2, I/O 3successively and U 427,1,2,6 pin be connected, its export and at U 46upper display be first tens digit stored in totally two store bytes of two storeies of address wire parallel connection, U 40data-out port line the 16th, 17,18,19 pin, i.e. I/O 4, I/O 5, I/O 6, I/O 7successively and U 437,1,2,6 pin be connected, its export and at U 47upper display be second tens digit stored in totally two store bytes of two storeies of address wire parallel connection, U 41data-out port line the 11st, 12,13,15 pin, i.e. I/O 0, I/O 1, I/O 2, I/O 3successively and U 447,1,2,6 pin be connected, its export and at U 48upper display be the 3rd tens digit stored in totally two store bytes of two storeies of address wire parallel connection, U 41data-out port line the 16th, 17,18,19 pin, i.e. I/O 4, I/O 5, I/O 6, I/O 7successively and U 457,1,2,6 pin be connected, its export and at U 49upper display be the 4th tens digit stored in two store bytes of two storeies of address wire parallel connection; U 42, U 43, U 44, U 459 ~ 15 pin and current-limiting resistance R 23× 7, R 24× 7, R 25× 7, R 26× 7 and seven-segment numeric indicator U 46, U 47, U 48, U 49corresponding connection is to realize digital-scroll technique;
When power-factor measurement device is metering type power-factor measurement device, the time data application module in its device adopts metering type time data application module, and this module comprises a gate circuit U in 42 input XOR gate integrated circuit 74LS86 101, its clock crystal oscillator frequency of a slice is the single-chip microcomputer 8031 i.e. U of 12MHZ 102, three eight rising edge d type flip flop 74LS377 and U 103, U 104, U 105with the H stored with binary-coded decimal form in conversion table electrically erasable programmable ROM EEPROM2864 and U of two address wire parallel connections of value 40, U 41, single-chip microcomputer 8031 passes through P 0mouth expansion delivery outlet, utilize three eight rising edge d type flip flop 74LS377 to be connected with the ROM (read-only memory) of these two address wire parallel connections, the concrete connection of its circuit is: the U of the 4th circuit unit 10output terminal 1 oUTwith XOR gate U 101the 1st pin be connected, the U of the 4th circuit unit 11output terminal 2 oUTwith XOR gate U 101the 2nd pin and single-chip microcomputer 8031 i.e. U 102the 13rd pin and the 12 circuit unit in the U of pulse-delay unit 21two input ends 1,2 pin be connected, XOR gate U 101the 3rd pin and single-chip microcomputer 8031 i.e. U 102the 12nd pin be connected; 8 of single-chip microcomputer P0 mouth line end pin are ascending, the order of namely pressing P0.0 to P0.7 sequentially individual eight rising edge d type flip flop U with (1) correspondingly by number 1048 data input pin 1D ~ 8D be connected, (1) individual eight rising edge d type flip flop U 1048 data output end 1Q ~ 8Q individual eight rising edge d type flip flop U with (2) correspondingly 1058 data input pin 1D ~ 8D be connected, (3) individual eight rising edge d type flip flop U 1038 data input pin 1D ~ 8D sequentially individual eight rising edge d type flip flop U with (1) correspondingly 1048 data input pin 1D ~ 8D parallel connection be connected, (3) individual eight rising edge d type flip flop U 1038 data output end 1Q ~ 8Q and (1) individual storer U 40the address line end pin of low eight by number ascending, namely sequentially connect correspondingly by the order of A0 to A7, (2) individual eight rising edge d type flip flop U 1058 data output ends in 1Q ~ 5Q and (1) individual storer U 40the address line end pin of high five by number ascending, namely sequentially connect correspondingly by the order of A8 to A12, single-chip microcomputer U 102the 16th pin, namely end pin and three eight rising edge d type flip flop U 103, U 104, U 105the 11st pin, namely CP hold pin be connected, single-chip microcomputer U 102the 27th pin, i.e. P2.6 pin and (1) individual eight rising edge d type flip flop U 104the 1st pin, namely end pin is connected, single-chip microcomputer U 102the 28th pin, i.e. P2.7 pin simultaneously and (2), (3) individual eight rising edge d type flip flop U 105, U 103the 1st pin, namely end pin is connected, (2) individual storer U 41address line end pin A0 ~ A12 and (1) individual storer U 40address line end pin A0 ~ A12 carry out connection in parallel correspondingly; Setting single-chip microcomputer U 102the address date of 16 bits of two bytes that its P0 mouth exports be arranged in order to most significant digit by lowest order, 8 data input pins that point secondary, each byte deliver to eight rising edge d type flip flops, wherein first time delivers to (1) individual eight rising edge d type flip flop U 104the data of 8 data input pins are addresses of high byte, till this address date plays sixteen bit from the 9th of this 16 bit, successively, the 9th 1D corresponding to eight rising edge d type flip flops, 8 data input pins, the tenth correspond to 2D ... sixteen bit corresponds to 8D; Second time delivers to (3) individual eight rising edge d type flip flop U 103the data of 8 data input pins are addresses of low byte, this address date plays till the 8th from first of this 16 bit, successively first 1D corresponding to eight rising edge d type flip flops, 8 data input pins, second correspond to 2D ... 8th corresponds to 8D; The two byte address data that point secondary is sent are at (3), (2) individual eight rising edge d type flip flop U 103, U 10513 binary storage device address codes arranging in order from low to high of data output end interruption-forming one and U 103data-out port 1Q ~ 8Q and U 105the storer U of data-out port 1Q ~ 5Q and two address wire parallel connection 40, U 41address end pin A0 ~ A12 have annexation one to one.
3. the measurement mechanism of a kind of power factor according to claim 2, it is characterized in that: described metering type time data application module also comprises peripheral component and circuit, the 8D latch 74LS373 that peripheral component and circuit comprise band ternary output is connected outer for the sheet of expansion program storage circuit with single-chip microcomputer 8031, the circuit that the frequency clock crystal oscillator that is 12MHZ is connected with single-chip microcomputer 8031, for needed for instant playback power factor data, BCD-seven-segment decoder/driver, the display circuit that current-limiting resistance and LED seven-segment numeric indicator are connected.
4. the measurement mechanism of a kind of power factor according to claim 2, it is characterized in that: described metering type time data application module also comprises a simple computing formula and software program, carry out simple computation by the software in program storage to the time data sampled immediately to read the power factor value in respective memory unit as storage address to obtain more precise time data and to show, the steps include:
function and the using method of the gate control position GATE of application single-chip microcomputer timer measure XOR gate output terminal and U 1013 pin output to single-chip microcomputer U 10212 pin namely high level, i.e. positive pulse width and measure the U of the 4th circuit unit 11output terminal 2 oUToutput to single-chip microcomputer U 10213 pin namely high level, i.e. positive pulse width, and respectively read T0 and T1 count value after close T0 and T1 respectively;
the value of T0 and T1 is substituted into formula calculate, after the value later to the radix point in acquired results rounds up, obtain 16 bits of two bytes;
the high byte of 16 bits is delivered to (1) individual eight rising edge d type flip flop U 104data output end;
the low byte of 16 bits is delivered to (3) individual eight rising edge d type flip flop U 103data output end and simultaneously (1) individual eight rising edge d type flip flop U 104value on data output end delivers to (2) individual eight rising edge d type flip flop U 105data output end on, using the storer U of 16 bits of this two byte as two address wire parallel connections 40, U 41address directly read out the power factor numerical value in its corresponding storage unit and give instant playback;
t0 and T1 is reset;
return after 1 is put to T0 and T1, wait for next test loop.
5. the measurement mechanism of a kind of power factor according to claim 2, is characterized in that: adopt measurement type time data application module in described device, and it keeps the temporary sampling time data of pulsing circuit at least to keep the time of 20ms, i.e. a cycle.
6. the measurement mechanism of a kind of power factor according to claim 2, it is characterized in that: when adopting metering type time data application module in described device, doing an amendment to the interlock circuit of this metering type time data application module then makes it become measurement type time data application module: namely, disconnects U 11output terminal 2 oUTwith single-chip microcomputer U 10213rd pin, namely between connecting line, simultaneously need not again according to the in claim 4 individual step calculates, as long as according to the in claim 4 after directly reading the count value of T0 step is carried out, and returns, wait for next test loop after finally only also putting 1 to T0 again to T0 clearing.
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CN112233613A (en) * 2020-10-29 2021-01-15 中国航发南方工业有限公司 Display panel assembly, display and operation device of gas turbine generator set
CN112289257A (en) * 2020-10-29 2021-01-29 中国航发南方工业有限公司 Display and operation device of gas turbine generator set
CN113589032A (en) * 2021-04-07 2021-11-02 天地融科技股份有限公司 Method and system for carrying out real-time power test on load on single live wire
CN114034814A (en) * 2021-10-28 2022-02-11 浙江极智通信科技股份有限公司 Carbon monoxide monitor testing method, terminal, system and storage medium

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Publication number Priority date Publication date Assignee Title
CN106885939B (en) * 2017-04-17 2017-12-08 山东省产品质量检验研究院 Three extreme point measuring methods of low-voltage electrical apparatus short circuit tolerance strength test power factor
CN106885939A (en) * 2017-04-17 2017-06-23 山东省产品质量检验研究院 Three extreme point measuring methods of low-voltage electrical apparatus short circuit tolerance strength test power factor
CN107144729B (en) * 2017-04-24 2019-06-07 北京电力经济技术研究院 The interval integral measurement method of low-voltage electrical apparatus short circuit tolerance strength test power factor
CN107144729A (en) * 2017-04-24 2017-09-08 北京电力经济技术研究院 The interval integral measuring method of low-voltage electrical apparatus short circuit tolerance strength test power factor
CN110082673A (en) * 2018-01-26 2019-08-02 煤科集团沈阳研究院有限公司 Low-voltage alternating-current switch on and off examines power factor test macro and test method
CN108646087A (en) * 2018-05-11 2018-10-12 华北科技学院 Fault detector and the method for measuring power factor using the fault detector
CN108646087B (en) * 2018-05-11 2020-10-16 华北科技学院 Fault indicator and method for measuring power factor using the same
CN108682383A (en) * 2018-06-15 2018-10-19 东莞阿尔泰显示技术有限公司 A kind of the protection circuit and its control method of LED display
CN112233613A (en) * 2020-10-29 2021-01-15 中国航发南方工业有限公司 Display panel assembly, display and operation device of gas turbine generator set
CN112289257A (en) * 2020-10-29 2021-01-29 中国航发南方工业有限公司 Display and operation device of gas turbine generator set
CN112233613B (en) * 2020-10-29 2021-08-06 中国航发南方工业有限公司 Display panel assembly, display and operation device of gas turbine generator set
CN113589032A (en) * 2021-04-07 2021-11-02 天地融科技股份有限公司 Method and system for carrying out real-time power test on load on single live wire
CN114034814A (en) * 2021-10-28 2022-02-11 浙江极智通信科技股份有限公司 Carbon monoxide monitor testing method, terminal, system and storage medium

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