CN105514100A - Semiconductor component and manufacture method thereof - Google Patents
Semiconductor component and manufacture method thereof Download PDFInfo
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- CN105514100A CN105514100A CN201410497745.3A CN201410497745A CN105514100A CN 105514100 A CN105514100 A CN 105514100A CN 201410497745 A CN201410497745 A CN 201410497745A CN 105514100 A CN105514100 A CN 105514100A
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Abstract
The invention discloses a manufacture method of a semiconductor component. Multiple grid structures are formed on a substrate; first dielectric layers are formed between adjacent grid structures respectively, and the upper surfaces of the first dielectric layers are lower than then lower surfaces of the grid structures and include grooves; an intermediate layer which covers the grid structures, the first dielectric layers and the grooves is formed; openings are formed in the intermediate layer, and each opening is placed between two adjacent grid structures; the first dielectric layers are removed via the openings; and a second dielectric layer is formed on the intermediate layer, so that air gaps are defined between adjacent grid structures. The invention also provides the semiconductor component.
Description
Technical field
The invention relates to a kind of semiconductor element and manufacture method thereof.
Background technology
Under the trend improving semiconductor element integrated level at present, the size of element can be reduced according to design rule.But along with size is more and more little, the capacitance-resistance electrical interference postponed between (resistor-capacitordelay, RCdelay) and each composition component makes the limited speed of integrated circuit, and affects its reliability and stability.Therefore, the semiconductor element operating efficiency that capacitance-resistance postpones to cause reduces, for needing the problem of solution at present badly.
Summary of the invention
The invention provides a kind of manufacture method of semiconductor element, it forms air gap between grid structure, and can effectively prevent the capacitance-resistance between grid structure from postponing, and improve the electrical interference between each composition component, to promote the efficiency of semiconductor element further.
The manufacture method of semiconductor element of the present invention is as follows.In substrate, form multiple grid structure, and form the first dielectric layer between adjacent two grid structures, its upper surface lower than the upper surface of grid structure, and has the first groove.Then, form the intermediate layer of overlies gate structure, the first dielectric layer and the first groove, and in wherein forming multiple opening, each opening is between adjacent two grid structures.Via opening to remove the first dielectric layer between adjacent two grid structures.Finally, on intermediate layer, form the second dielectric layer, to define air gap between adjacent two grid structures.
In one embodiment of this invention, the manufacture method of described semiconductor element, the intermediate layer wherein on each first groove has the second groove.Now, the method forming opening in intermediate layer is included in the sidewall formation clearance wall of each the second groove, to expose intermediate layer.With clearance wall be mask to remove part intermediate layer, to form these openings, then remove clearance wall.
In one embodiment of this invention, the manufacture method of described semiconductor element, the method wherein forming intermediate layer is included on grid structure and the first dielectric layer and forms the first intermediate layer of material, and the second intermediate layer of material is formed in the first intermediate layer of material, wherein the material of the second intermediate layer of material is different from the first intermediate layer of material, and different from the material of clearance wall.
In one embodiment of this invention, the manufacture method of described semiconductor element, when wherein removing the first dielectric layer between adjacent two grid structures via a little opening, more comprises part first intermediate layer of material removed on the first dielectric layer.
In one embodiment of this invention, the manufacture method of described semiconductor element, wherein before formation first intermediate layer of material, more comprise and carry out a silication technique for metal, on the gate conductor layer of each grid structure, form metal silicide layer, and the height of air gap is higher than the upper surface of gate conductor layer.
The present invention also proposes a kind of structure of semiconductor element, comprises and is configured at suprabasil multiple grid structure, the intermediate layer above the substrate on grid structure and between adjacent two grid structures, and is positioned at the dielectric layer on intermediate layer.Wherein between adjacent two grid structures, there is air gap.
In one embodiment of this invention, the structure of described semiconductor element, wherein each air gap comprises the principal space defined by the sidewall of adjacent two grid structures, substrate surface and intermediate layer, and is positioned on principal space, the protruding space defined by intermediate layer and dielectric layer.
In one embodiment of this invention, the structure of described semiconductor element, wherein intermediate layer comprise be positioned at grid structure surface and sidewall on the first intermediate layer of material, and the second intermediate layer of material be positioned in the first intermediate layer of material, between adjacent two grid structures, have opening, wherein the material of the second intermediate layer of material is different from the first intermediate layer of material.
In one embodiment of this invention, the structure of described semiconductor element, wherein each grid structure comprises gate conductor layer and metal silicide layer, and the height of principal space is greater than the height on gate conductor layer surface.
In one embodiment of this invention, the structure of described semiconductor element, wherein the volume of each air gap is 5% to 95% of the gap between adjacent two grid structures.
Based on above-mentioned, the manufacture method of semiconductor element proposed by the invention, air gap can be formed between adjacent two grid structures, and the height of the air gap formed is higher than the upper surface of the gate conductor layer of grid structure, therefore can effectively prevent the capacitance-resistance between grid structure from postponing, and the electrical interference improved between each composition component, and promote the efficiency of semiconductor element further.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate institute's accompanying drawings to be described in detail below.
Accompanying drawing explanation
The manufacturing process generalized section of semiconductor element of Figure 1A to Fig. 1 K for illustrating according to the embodiment of the present invention.
[symbol description]
10: substrate
12: dielectric materials layer
12a, 16,28: dielectric layer
13rd: the first district
15th: the second district
14: stop-layer
20: intermediate layer
22: the first intermediate layer of material
24: the second intermediate layer of material
26: material layer
26a: clearance wall
30,50: grid structure
32,52: gate conductor layer
34,54: electric charge storage layer
36,56: hard mask layer
38,58: metal silicide layer
40: the first grooves
42: air gap
42a: principal space
42b: protruding space
44: the second grooves
46: opening
48: hole
Embodiment
The manufacturing process generalized section of semiconductor element of Figure 1A to Fig. 1 J for illustrating according to the embodiment of the present invention.
Please refer to Figure 1A, provide substrate 10, substrate 10 is such as semiconductor base, semiconducting compound substrate or insulating barrier have semiconductor base (SemiconductorOverInsulator, SOI).Semiconductor is such as the atom of IVA race, such as silicon or germanium.Semiconducting compound is such as the semiconducting compound that the atom of IVA race is formed, such as, be carborundum or germanium silicide, or the semiconducting compound that IIIA race atom and VA race atom are formed, such as, be GaAs.Substrate 10 comprises the first district 13 and the second district 15.In one embodiment, the first district 13 is such as memory cell areas, and the second district 15 is such as periphery circuit region.
Then, continue referring to Figure 1A, in substrate 10, multiple grid structure 30,50 is formed.Grid structure 30,50 at least comprises gate conductor layer 32,52.The material of gate conductor layer 32 can be conductor, such as, be doped polycrystalline silicon.In addition, as shown in Figure 1A, grid structure 30,50 more can comprise dielectric layer 34,54, between corresponding grid conducting layer 32,52 and substrate 10.In one embodiment, semiconductor element is such as memory element, and dielectric layer 34,54 is such as electric charge storage layer.Electric charge storage layer can be laminated construction, such as, be ONO (oxide-nitride-oxide) layer, that is comprising silicon oxide/silicon nitride/silicon oxide three layers.On the other hand, as shown in Figure 1A, grid structure 30,50 more can comprise hard mask layer 36,56, is positioned on corresponding gate conductor layer 32,52.The material of hard mask layer 36,56 can be such as silica, silicon oxynitride or silicon nitride.
Then, continue referring to Figure 1A, form dielectric materials layer 12 on the substrate 10, with the hard mask layer 36,56 in overlies gate structure 30,50.In dielectric materials layer 12 between adjacent two grid structures 30 in the first district 13, there is hole 48.In one embodiment, the height of hole 48 is greater than the height on gate conductor layer 32 surface.The material of dielectric materials layer 12 is such as silica, phosphorosilicate glass, boron-phosphorosilicate glass or its combination.The formation method of dielectric materials layer 12 is such as high density plasma CVD method (HDP-CVD).
Next, please refer to Figure 1A and Figure 1B, anisotropic etching is carried out to dielectric materials layer 12, to remove part dielectric materials layer 12, expose the top of hard mask layer 36 and 56.Afterwards, the dielectric materials layer 12 through etching sequentially forms stop-layer 14 and dielectric layer 16.The material of stop-layer 14 is different from dielectric materials layer 12, and different from dielectric layer 16.The material of stop-layer 14 is such as silicon nitride, silicon oxynitride, carbon silicon oxynitride or carborundum, and formation method is such as chemical vapour deposition technique or atomic layer deposition method (ALD).The material of dielectric layer 16 is such as silica, and formation method is such as high density plasma CVD method.
Please refer to Figure 1B and Fig. 1 C, a flatening process is carried out to dielectric layer 16, to exposing stop-layer 14.Described flatening process is such as chemical mechanical milling method.Next, please refer to Fig. 1 C and Fig. 1 D, removal stop layer 14 and hard mask layer 36,56, to expose gate conductor layer 32,52.The method removed is such as wet type etch method or Siconi etching method, but not as limit.Afterwards, please refer to Fig. 1 D and Fig. 1 E, etching is carried out back, to form dielectric layer 12a to the dielectric materials layer 12 between adjacent two grid structures 30,50.The upper surface of dielectric layer 12a lower than the upper surface of gate conductor layer 32,52, and has the first groove 40 in dielectric layer 12a between adjacent two grid structures 30 in the first district 13.
Then, please refer to Fig. 1 F, carry out silication technique for metal, to form metal silicide layer 38,58 on the gate conductor layer 32,52 of each grid structure 30,50.The material of metal silicide layer 38,58 can be such as the silicide of titanium, tungsten, cobalt, nickel, copper, molybdenum, tantalum, erbium, zirconium or platinum.In one embodiment, the material of metal silicide layer 38,58 is such as cobalt silicide (CobaltSilicide, CoSi).Now, described silication technique for metal is such as first deposit one deck cobalt, afterwards, carry out the first rapid hot technics (RapidThermalProcess, RTP), then carry out cobalt silicide selective etch, remove unreacted cobalt, carry out the second rapid hot technics more afterwards, to make the pasc reaction in cobalt and gate conductor layer 32,52, to form the metal silicide layer 38,58 that material is cobalt silicide.
Please refer to Fig. 1 G, form intermediate layer 20.Intermediate layer 20 covers dielectric layer 12a, the first groove 40 with the metal silicide layer 38,58 on gate structure 30,50, and the intermediate layer 20 on each first groove 40 has the second groove 44.Afterwards, material layer 26 is formed, to be covered on intermediate layer 20.In one embodiment, intermediate layer 20 is a laminated construction, is made up of the first intermediate layer of material 22 and the second intermediate layer of material 24.Intermediate layer 20 and the formation method of material layer 26 are included on metal silicide layer 38,58 on grid structure 30,50 and dielectric layer 12a and first form the first intermediate layer of material 22, the second intermediate layer of material 24 is formed again in the first intermediate layer of material 22, afterwards, then form material layer 26.First intermediate layer of material 22 is different from the material of the second intermediate layer of material 24.The material of the first intermediate layer of material 22 is such as silica, phosphorosilicate glass, boron-phosphorosilicate glass or its combination, and the method for formation is such as chemical vapour deposition technique.The material of the second intermediate layer of material 24 is such as silicon nitride, silicon oxynitride, carbon silicon oxynitride or carborundum, and formation method is such as chemical vapour deposition technique or atomic layer deposition method.In an exemplary embodiment, the material of the first intermediate layer of material 22 is such as silica, and the material of the second intermediate layer of material 24 is such as silicon nitride, and material layer 26 is identical with the material of the first intermediate layer of material 22, such as be all silica, but the present invention is not as limit.
Please refer to Fig. 1 G and Fig. 1 H, anisotropic etching is carried out to material layer 26, form clearance wall 26a with the sidewall in each the second groove 44, expose intermediate layer 20.Afterwards, please refer to Fig. 1 H and Fig. 1 I, because the thickness covering the intermediate layer 20 (the second intermediate layer of material 24) on the first groove 40 is very thin, therefore utilize clearance wall 26a as mask, can the intermediate layer 20 that exposes of easy removal, to form multiple opening 46 in the intermediate layer 20 in the first district 13, and each opening 46 is between adjacent two grid structures 30.Afterwards, continue referring to Fig. 1 I and Fig. 1 J, via formed opening 46, the dielectric layer 12a between adjacent two grid structures 30 removing the first district 13.In another embodiment, as schemed shown in I and Fig. 1 J, during dielectric layer 12a between adjacent two grid structures 30 removing the first district 13 via opening 46, also can remove part first intermediate layer of material 22 on the dielectric layer 12a in the first district 13 and clearance wall 26a simultaneously.The method removing part first intermediate layer of material 22 on the dielectric layer 12a in dielectric layer 12a between clearance wall 26a, adjacent two grid structures 30 and the first district 13 can be such as wet type etch method or Siconi etching method, but not as limit.
Please refer to Fig. 1 J and Fig. 1 K, on intermediate layer 20, form dielectric layer 28, to define air gap 42 between adjacent two grid structures 30 in the first district 13.The material of dielectric layer 28 is such as silica, phosphorosilicate glass, boron-phosphorosilicate glass or its combination.And the formation method of dielectric layer 28 is such as high density plasma CVD method.
Please refer to Fig. 1 K, comprise substrate 10, multiple grid structure 30 and 50, intermediate layer 20, dielectric layer 28 and air gap 42 according to the structure of the semiconductor element of the embodiment of the present invention.Multiple grid structure 30,50 is configured in substrate 10, and each grid structure 30,50 at least comprises gate conductor layer 32,52 and metal silicide layer 38,58.Above the substrate 10 of intermediate layer 20 on grid structure 30,50 and between adjacent two grid structures 30,50.Dielectric layer 28 is positioned on intermediate layer 20.
Continue referring to Fig. 1 K, according to one embodiment of the invention, intermediate layer 20 is a laminated construction, is made up of the first intermediate layer of material 22 and the second intermediate layer of material 24.In the surface that first intermediate layer of material 22 is positioned at grid structure 30,50 and partial sidewall.Second intermediate layer of material 24 is positioned in the first intermediate layer of material 22.First intermediate layer of material 22 is different from the material of the second intermediate layer of material 24.
Continue referring to Fig. 1 K, air gap 42 is between adjacent two grid structures 30, and wherein the volume of each air gap 42 is such as 5% to 95% of the gap between adjacent two grid structures 30.According to one embodiment of the invention, air gap 42 such as comprises principal space 42a and protruding space 42b.Principal space 42a defined by adjacent two grid structures 30 and the sidewall of metal silicide layer 38, the surface of substrate 10 and intermediate layer 20, and the height of principal space 42a is greater than the height on gate conductor layer 32 surface.Protruding space 42b is positioned on principal space 42a, defined by intermediate layer 20 and dielectric layer 28.The shape of principal space 42a is such as rectangle, ladder type or its combination; The shape of protruding space 42b is such as triangle, arch or its combination, but not as limit.In one embodiment, the shape of principal space 42a is such as rectangle; The shape of protruding space 42b is such as arch.Height due to the principal space 42a of air gap 42 is greater than the height on gate conductor layer 32 surface, therefore, effectively can avoid the interference that conducting between grid structure causes.
In sum, the manufacture method of semiconductor element provided by the invention, can form air gap, and the height of the air gap formed is greater than the height of the gate conductor layer of grid structure between two adjacent grid structures.Therefore, it is possible to prevent the capacitance-resistance between grid structure from postponing, and improve the electrical interference between each composition component, and fully promote the efficiency of semiconductor element.
Although the present invention discloses as above with embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion of defining depending on the right of enclosing.
Claims (10)
1. a manufacture method for semiconductor element, comprising:
Multiple grid structure is formed in a substrate;
Between adjacent two grid structures, form one first dielectric layer, the upper surface of this first dielectric layer lower than the upper surface of these grid structures, and has one first groove;
In substrate, form an intermediate layer, cover these grid structures, this first dielectric layer and these the first grooves;
In this intermediate layer, form multiple opening, each opening is between adjacent two grid structures;
Via these openings, remove this first dielectric layer between adjacent two grid structures; And
On this intermediate layer, form one second dielectric layer, wherein between adjacent two grid structures, define an air gap.
2. the manufacture method of semiconductor element according to claim 1, this intermediate layer wherein on each first groove has one second groove, and the method forming these openings in this intermediate layer comprises:
Sidewall in each the second groove forms a clearance wall, and this clearance wall exposes this intermediate layer;
With this clearance wall for mask, remove this intermediate layer of part, to form these openings; And remove these clearance walls.
3. the manufacture method of semiconductor element according to claim 1, the method wherein forming this intermediate layer comprises:
One first intermediate layer of material is formed on these grid structures and this first dielectric layer; And
In this first intermediate layer of material, form one second intermediate layer of material, wherein the material of this second intermediate layer of material is different from this first intermediate layer of material, and different from the material of this clearance wall.
4. the manufacture method of semiconductor element according to claim 3, wherein via these openings, when removing this first dielectric layer between adjacent two grid structures, more comprises this first intermediate layer of material of part removed on this first dielectric layer.
5. the manufacture method of semiconductor element according to claim 4, wherein before this first intermediate layer of material of formation, more comprise and carry out a silication technique for metal, on a gate conductor layer of each grid structure, form a metal silicide layer, and the height of these air gaps is higher than the upper surface of these gate conductor layers.
6. a semiconductor element, comprising:
Multiple grid structure, is configured in a substrate;
One intermediate layer, above this substrate on these grid structures and between adjacent two grid structures; And
One dielectric layer, is positioned on this intermediate layer,
Wherein, between adjacent two grid structures, there is an air gap.
7. semiconductor element according to claim 6, wherein each air gap comprises:
One principal space, defined by the sidewall of adjacent two grid structures, this substrate surface and this intermediate layer; And
One protruding space, is positioned on this principal space, defined by this intermediate layer and this dielectric layer.
8. semiconductor element according to claim 7, wherein this intermediate layer comprises:
One first intermediate layer of material, on the surface being positioned at these grid structures and sidewall; And
One second intermediate layer of material, is positioned in this first intermediate layer of material, between adjacent two grid structures, have an opening, and wherein the material of this second intermediate layer of material is different from this first intermediate layer of material.
9. semiconductor element according to claim 6, wherein each grid structure comprises a gate conductor layer and a metal silicide layer, and the height of this principal space is greater than the height on this gate conductor layer surface.
10. the manufacture method of semiconductor element according to claim 6, wherein the volume of each air gap is 5% to 95% of the gap between adjacent two grid structures.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1791974A (en) * | 2003-05-21 | 2006-06-21 | 桑迪士克股份有限公司 | Use of voids between elements in semiconductor structures for isolation |
| US20110318914A1 (en) * | 2010-06-25 | 2011-12-29 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device |
| US20120074484A1 (en) * | 2010-09-27 | 2012-03-29 | Kang Jin-Kyu | Semiconductor devices and methods of manufacturing semiconductor devices |
| US20120156855A1 (en) * | 2010-12-16 | 2012-06-21 | Jae-Hwang Sim | Methods of manufacturing semiconductor devices |
| TW201417188A (en) * | 2012-10-25 | 2014-05-01 | Macronix Int Co Ltd | Airgap structure and method of manufacturing thereof |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1791974A (en) * | 2003-05-21 | 2006-06-21 | 桑迪士克股份有限公司 | Use of voids between elements in semiconductor structures for isolation |
| US20110318914A1 (en) * | 2010-06-25 | 2011-12-29 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device |
| US8765572B2 (en) * | 2010-06-25 | 2014-07-01 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device |
| US20120074484A1 (en) * | 2010-09-27 | 2012-03-29 | Kang Jin-Kyu | Semiconductor devices and methods of manufacturing semiconductor devices |
| US20120156855A1 (en) * | 2010-12-16 | 2012-06-21 | Jae-Hwang Sim | Methods of manufacturing semiconductor devices |
| TW201417188A (en) * | 2012-10-25 | 2014-05-01 | Macronix Int Co Ltd | Airgap structure and method of manufacturing thereof |
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