CN105513976B - Method for packaging semiconductor, packaging body and encapsulation unit - Google Patents
Method for packaging semiconductor, packaging body and encapsulation unit Download PDFInfo
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- CN105513976B CN105513976B CN201510874625.5A CN201510874625A CN105513976B CN 105513976 B CN105513976 B CN 105513976B CN 201510874625 A CN201510874625 A CN 201510874625A CN 105513976 B CN105513976 B CN 105513976B
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- carrier
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- packaging body
- packaging
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The present invention provides a kind of method for packaging semiconductor, packaging body and encapsulation unit, and the method for packing includes the following steps：The packaging body with multiple encapsulation units is provided, the first face of the packaging body is combined with a carrier；Cutting step is carried out to the packaging body, so that the encapsulation unit is independent of one another；Pair with the carrier-bound encapsulation unit carry out plating metal step, so as to expose to the metal section whole plated metal of the encapsulation unit；Remove the carrier.It is an advantage of the current invention that an advantage of the present invention is that using the carrier combined with packaging body, for example, carrying out plating metal using the conductive carrier of insulating carrier or packaging body in itself, it is not necessary to which extra processing procedure can be achieved pin and electroplate entirely, improve reliability；And frame pin can be designed flexibly and easily.
Description
Technical field
The present invention relates to field of semiconductor package, more particularly to a kind of method for packaging semiconductor, packaging body and encapsulation unit.
Background technology
Referring to Fig. 1, packaging body draws by the base island 10 in center and around what base island 10 was arranged in the lower part in chip package space
Foot 11 is formed, chip placement 12 on base island 10, and each conductive part on chip 12 is electrically connected by metal wire 13 and each pin 11 respectively
Connect, remaining encapsulated space filling epoxy resin.For DFN techniques, since it only has both sides to have pin, so, in the encapsulation
After body plastic packaging, cutting separation is carried out to packaging body, as shown in Figure 1, after cutting, the cut surface of pin 11 can be exposed to the encapsulation
Opposite two sides (part as indicated by the arrows in the figure) of body, are so unfavorable for the requirement of reliability and solderability.
And traditional mode electroplated to pin side, it is that conduction rack is set on the other two relative side of packaging body
(or even muscle) 14, pin 11 is electrically connected to external frame 15 by the conduction rack 14, forms galvanic circle, is cut in first time
After (being longitudinally cutting in figure), using electroplating technology, using conduction rack 14 by drawing exposed to the packaging body two relative side
Foot electroplated metal layer 16.
After completing to electroplate, second of cutting (transverse direction) is carried out, conduction rack 14 is separated.
But all there is the QFN techniques of pin for four sides, as shown in Fig. 2, pin 11 is indicated using dotted line up and down, edge
The pin 11 on body side surface cutting conduction rack 14 and the side is encapsulated, conduction rack 14 and pin 11 have section (such as in the side
Arrow meaning part in Fig. 2).
There are shortcoming for the method for above-mentioned conventional side pin plating metal：After being finished due to first time cutting, the envelope
Dress body, which exposes, has no other structures presence on the two relative side of pin section, that is, is not present and draws with other two relative side
The structure of foot connection, therefore, the pin and conduction rack exposed after being cut at second can not form conductive return with external structure
Road, its section can not plating metal, the reliability of packaging body product can be reduced.
Due to the packaging body shortcoming so that the packaging body that this kind of four sides has pin is unsuitable for the high production of reliability requirement
Product.Therefore, it is badly in need of a kind of high packaging body product of reliability.
The content of the invention
The technical problem to be solved by the invention is to provide a kind of method for packaging semiconductor, packaging body and encapsulation unit, its
It can realize that pin plates entirely, improve reliability.
To solve the above-mentioned problems, the present invention provides a kind of method for packaging semiconductor, include the following steps：Offer has
The packaging body of multiple encapsulation units, the first face of the packaging body are combined with a carrier；Cutting step is carried out to the packaging body,
So that the encapsulation unit is independent of one another；Pair with the carrier-bound encapsulation unit carry out plating metal step so that
Expose to the metal section whole plated metal of the encapsulation unit；Remove the carrier.
Further, the carrier is conductive carrier, and the first face of the packaging body has lead frame for the packaging body
One side, it is described plating metal method be：Energization plating is carried out to the encapsulation unit and conductive carrier, so as to expose to described
The metal section whole plating metal of encapsulation unit.
Further, before metal step is plated, a surface mask film covering of the encapsulation unit is deviated from the conductive carrier.
Further, conductive carrier is carbon steel, is the carrier of the lead frame before the packaging body encapsulates.
Further, before the packaging body is combined with the carrier, the step of further including a preplating, for by the envelope
The bare metal plating metal that dress body is subsequently blocked by carrier.
Further, the carrier is insulating carrier, and the first face of the packaging body is the packaging body away from lead frame
One side, it is described plating metal method be：Chemical plating is carried out to the encapsulation unit, so as to expose to the gold of the encapsulation unit
Belong to section all plating metals.
Further, after cutting the packaging body, the cut surface of the encapsulation unit lateral leads and the pin exposure of bottom surface,
In electroless plating step, the metal section whole plated metal of the encapsulation unit is exposed to.
Further, the insulating carrier is UV films.
Further, the UV films one side is fixed on a nonmetallic supporter, the first face of another side and the packaging body
With reference to.
Further, in the step of removing the insulating carrier, the UV films are removed using the method for irradiating ultraviolet light.
The present invention also provides a kind of packaging body, including multiple settings are on the same vector and encapsulation unit independent of each other,
Expose to the equal plated metal in metal section of each encapsulation unit.
Further, the carrier is arranged on one side or the carrier of the encapsulation unit with lead frame and is arranged on institute
State one side of the encapsulation unit away from lead frame.
The present invention also provides a kind of encapsulation unit, the encapsulation unit at least in two adjacent sides there is cutting to be formed
Metal section, all metal sections are all covered with the coat of metal.
Further, every one side of the encapsulation unit is both provided with pin, and the metal section of each pin covers
There is the coat of metal.
Further, the coat of metal uniformity of each metal section.
Further, the intersection at least two faces of the pin has dividing strip, the coat of metal tool of dividing strip both sides
Variant feature.
Further, the difference characteristic is different for the thickness of the dividing strip both sides coat of metal.
An advantage of the present invention is that using the carrier combined with packaging body, for example, utilizing insulating carrier or packaging body
The conductive carrier of itself carries out plating metal, it is not necessary to which extra processing procedure can be achieved pin and electroplate entirely, improve reliability；And frame
Pin can be designed flexibly and easily.
Brief description of the drawings
Fig. 1 is the structure diagram of existing packaging body；
Fig. 2 is the schematic cross-section of existing packaging body；
Fig. 3 is the step schematic diagram of method for packaging semiconductor of the present invention；
Fig. 4 is the step schematic diagram of the first embodiment of method for packaging semiconductor plating metal of the present invention；
Fig. 5 A~Fig. 5 E are the flow charts of the first embodiment of method for packaging semiconductor of the present invention；
Fig. 6 is the step schematic diagram of the second embodiment of method for packaging semiconductor plating metal of the present invention；
Fig. 7 A~Fig. 7 D are the flow charts of the second embodiment of method for packaging semiconductor of the present invention；
Fig. 8 is the structure diagram of the first embodiment of packaging body of the present invention；
Fig. 9 is the structure diagram of the second embodiment of packaging body of the present invention；
Figure 10 is the structure diagram of encapsulation unit made according to the method for the present invention.
Embodiment
Below in conjunction with the accompanying drawings to the specific embodiment party of method for packaging semiconductor provided by the invention, packaging body and encapsulation unit
Formula elaborates.
Referring to Fig. 3, method for packaging semiconductor of the present invention includes the following steps：Step S1, providing has multiple encapsulation units
Packaging body, the first face of the packaging body is combined with a carrier；Step S2, cutting step is carried out to the packaging body, so that
It is independent of one another to obtain the encapsulation unit；Step S3, pair plating metal step is carried out with the carrier-bound encapsulation unit, with
Make the metal section whole plated metal for exposing to the encapsulation unit；Step S4, the carrier is removed.
In the first embodiment of method for packaging semiconductor of the present invention, the carrier is conductive carrier, the envelope
Filling the first face of body has the one side of lead frame for the packaging body.Referring to Fig. 4, the of method for packaging semiconductor of the present invention
In one embodiment, the method for plating metal includes the following steps：Step S40, the envelope is deviated from the conductive carrier
Fill a surface mask film covering of unit；Step S41, energization plating is carried out to the encapsulation unit and conductive carrier, so that exposed
In the metal section whole plating metal of the encapsulation unit.
Fig. 5 A~Fig. 5 E are the flow diagrams of the first embodiment of method for packaging semiconductor of the present invention.
Referring to step S1 and Fig. 5 A, there is provided have the packaging body of multiple encapsulation units 31, the first face 38 of the packaging body
Combined with a conductive carrier 32.In this embodiment, two encapsulation units 31 are only symbolically enumerated.
Further, the conductive carrier 32 is carbon steel, and the first face of the packaging body has lead for the packaging body
The one side of frame 33.The conductive carrier 32 is the carrier that lead frame 33 has in itself, in the progress of lead frame 33 die bond, is beaten
The lead frame 33 is supported during line and encapsulation.Therefore, the conductive carrier 32 is not to be added in this step
Package bottom, but lead frame 33 supporting structure of itself.It is when the lead frame 33 makes and conductive in covering
Before carrier 32,33 bottom of lead frame is electroplated in advance, for the packaging body subsequently to be hidden by conductive carrier 32
The bare metal electroplated metal layer of gear.
Referring to step S2 and Fig. 5 B, cutting step is carried out to the packaging body, so that the encapsulation unit 31 is only each other
It is vertical.Conductive carrier 32 is not cut in step cutting, so that conductive carrier 32 can be connected with each encapsulation unit 31, follow-up
In plating step, plating circuit is formed.After the cutting step, metal section 35 exposes to the encapsulation unit 31, the metal
Section 35 includes the metal section of pin, can also include the metal section of 31 other structures of encapsulation unit.
Referring to step S40 and Fig. 5 C, deviate from a surface mask film covering of the encapsulation unit 31 in the conductive carrier 32
34。
Since the conductive carrier 32 away from another surface of encapsulation unit 31 and need not be electroplated, in order to save plating material
Material, the mask 34 cover another surface that the conductive carrier 32 deviates from the encapsulation unit 31, to avoid the conductive load
Body 32 is plated away from another surface of the encapsulation unit 31.
Referring to step S41 and Fig. 5 D, energization plating is carried out to the encapsulation unit 31 and conductive carrier 32, so as to expose to
The whole electroplated metal layers 36 in metal section 35 of the encapsulation unit 31.In this step, the exposed table of the conductive carrier 32
Face is also plated metal layer 36, and the metal layer on 35 surface of metal section is marked using dotted line signal in figure, gone subsequently
Except in the step of conductive carrier 32, the metal layer 36 is cut along the dotted line, to retain 35 surface of metal section
Metal layer.
In this embodiment, the metal section 35 refers to the section of pin, in other embodiments, institute
State whole metal sections that metal section 35 includes exposing to the encapsulation unit 31.Further, the metal layer 36 with it is described
The metal material of 31 preplating of encapsulation unit is identical, is, for example, metallic gold.
Referring to step S4 and Fig. 5 E, the conductive carrier 32 is removed, forms the encapsulating structure that metal section 35 is plated entirely.It is described
Minimizing technology can use the method peeled off, or other methods well known to those skilled in the art.Preferably, the conductive carrier
32 protrude from the encapsulation unit 31, in order to the stripping of the conductive carrier 32.
Present embodiment makes full use of the conductive carrier of packaging body frame in itself to be electroplated, it is not necessary to extra system
Journey can be achieved metal section and electroplate entirely, improve reliability；And frame pin can be designed flexibly and easily.
In the second embodiment of method for packaging semiconductor of the present invention, the carrier is insulating carrier, the envelope
The first face for filling body is one side of the packaging body away from lead frame.Referring to Fig. 6, the of method for packaging semiconductor of the present invention
In two embodiments, the method for plating metal includes the following steps：Step S60, chemical plating is carried out to the encapsulation unit,
So that metal is all plated in the metal section for exposing to the encapsulation unit；Step S61, the insulating carrier is removed, forms pin
The encapsulating structure plated entirely.
Fig. 7 A~Fig. 7 D are the flow diagrams of the second embodiment of method for packaging semiconductor of the present invention.
Referring to step S1 and Fig. 7 A, there is provided have the packaging body of multiple encapsulation units 71, the first face 78 of the packaging body
Combined with an insulating carrier 72.In this embodiment, two encapsulation units 71 are only symbolically enumerated.
The insulating carrier 72 is UV films, and the first face of the packaging body is one of the packaging body away from lead frame 73
Face.72 one side of insulating carrier is fixed on a nonmetallic supporter (not indicated in attached drawing), another side and the packaging body
The first face combine.In this embodiment, the one side of the insulating carrier 72 is attached to taking with plastic hoop in advance,
To fix and support the insulating carrier 72.By the first face paste of the packaging body on insulating carrier 72.
Referring to step S2 and Fig. 7 B, cutting step is carried out to the packaging body, so that the encapsulation unit 71 is only each other
It is vertical.Insulating carrier 72 is not cut in step cutting, so that insulating carrier 72 can be connected with each encapsulation unit 71.Cutting
Afterwards, the cut surface of the pin of the side of the encapsulation unit 71 and the exposure of the pin of bottom surface.
Referring to step S60 and Fig. 7 C, chemical plating is carried out to the encapsulation unit 71, so as to expose to the encapsulation unit 71
The whole metal claddings 76 in metal section 75.In this embodiment, the section of the metal section 75 only pin, institute
State pin and do not carry out preplating, therefore, the pin exposed is in the equal plated metal of cut surface and bottom surface of the encapsulation unit 71
Layer 76.In this embodiment, the metal of chemical plating can be nickel gold.
Referring to step S61 and Fig. 7 D, the insulating carrier 72 is removed, forms the encapsulating structure that pin 75 plates entirely.In this tool
In body embodiment, if the insulating carrier 72 is UV films, the insulating carrier 72 is removed using the method for irradiating ultraviolet light.
The present invention also provides a kind of packaging body, referring to Fig. 8, in the first embodiment of packaging body of the present invention, institute
State packaging body include it is multiple be arranged in identical carrier 82 and encapsulation unit independent of each other 81, it is single to expose to each encapsulation
The metal section (unmarked in attached drawing) of member 81 plated metal layer 86.In this embodiment, only symbolically enumerate
Carrier 82 described in two encapsulation units 81 is conductive carrier, and the conductive carrier 82 has lead frame with the encapsulation unit 81
83 one side connection.The conductive carrier 82 is the carrier that lead frame 83 has in itself, for example, carbon steel, in lead frame
The lead frame 83 is supported during 83 progress die bonds, routing and encapsulation.In this embodiment, the encapsulation is single
First 82 bottom surfaces have been plated by the pin that conductive carrier 82 covers before being combined with conductive carrier 82.
Referring to Fig. 9, in the second embodiment of packaging body of the present invention, the packaging body includes multiple be arranged on together
On one carrier 92 and encapsulation unit independent of each other 91, expose to the metal section of each encapsulation unit 91 (in attached drawing not
Mark) equal plated metal layers 96.In this embodiment, two encapsulation units 91 are only symbolically enumerated.The carrier
92 be insulating carrier, such as UV films.The insulating carrier is connected with the one side of the encapsulation unit 91 away from lead frame 93.
In present embodiment, the bottom surface of the encapsulation unit 91 and the equal plated metal layer 96 of the pin 95 of side.
Referring to Figure 10, the present invention also provides a kind of encapsulation unit, the encapsulation unit at least has in two adjacent sides
There is the metal section 105 that cutting is formed, all metal sections 105 are all covered with the coat of metal 106.In this specific embodiment party
In formula, the metal section 105 is the section for the multiple pins 103 for exposing to the encapsulation unit side.The encapsulation unit
It can also include plastic-sealed body 100 at the same time, be placed with the base island 102 of chip 101.The pin 103 surrounds 102 cloth of base island
Put.Each conductive part on chip 101 is electrically connected by metal wire 104 with each pin 103 respectively.The plastic-sealed body 100 is by Ji Dao
102nd, chip 101, pin 103 and 104 plastic packaging of metal wire are in equal in one, all metal sections 105 of all pins 103
Covered with coating 106.In other embodiments of encapsulation unit of the present invention, the metal section 105 includes pin
Metal section, can also include the metal section of 31 other structures of encapsulation unit.
In this embodiment, every one side of the encapsulation unit is both provided with pin 103, for example, QFN is square
Encapsulation, its four sides are respectively provided with pin, and all metal sections 105 of each pin 103 are all covered with coating 106.Into one
Step, 106 uniformity of coating of the metal section 105, as shown in Figure 10, the thickness and material identical of coating 106.At this
In other embodiments of invention encapsulation unit, the intersection at least two faces of pin 103 is (attached with dividing strip
Do not indicated in figure), the coating 106 of dividing strip both sides has difference characteristic.The dividing strip is due at least two of pin 103
Coated coating 106 when face is different and produce.The difference characteristic refers to that the thickness of the coating 106 of dividing strip both sides is different or plates
The material of layer 106 is different.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (15)
1. a kind of method for packaging semiconductor, it is characterised in that include the following steps：
The packaging body with multiple encapsulation units is provided, the first face of the packaging body is combined with a carrier；
Cutting step is carried out to the packaging body, so that the encapsulation unit is independent of one another；
Pair with the carrier-bound encapsulation unit carry out plating metal step, so as to expose to the metal of the encapsulation unit
Section whole plated metal；
Remove the carrier.
2. method for packaging semiconductor according to claim 1, it is characterised in that the carrier is conductive carrier, the envelope
Filling the first face of body has the one side of lead frame for the packaging body, and the method for the plating metal is：To the encapsulation unit
And conductive carrier carries out energization plating, so as to expose to the metal section whole plating metal of the encapsulation unit.
3. method for packaging semiconductor according to claim 2, it is characterised in that before metal step is plated, in the conduction
Carrier deviates from a surface mask film covering of the encapsulation unit.
4. the method for packaging semiconductor according to Claims 2 or 3, it is characterised in that the conductive carrier is carbon steel, is
The carrier of lead frame before the packaging body encapsulation.
5. the method for packaging semiconductor according to Claims 2 or 3, it is characterised in that in the packaging body and the carrier
The step of with reference to before, a preplating is further included, for the bare metal plating metal for subsequently being blocked the packaging body by carrier.
6. method for packaging semiconductor according to claim 1, it is characterised in that the carrier is insulating carrier, the envelope
The first face for filling body is one side of the packaging body away from lead frame, and the method for the plating metal is：
Chemical plating is carried out to the encapsulation unit, so that metal is all plated in the metal section for exposing to the encapsulation unit.
7. method for packaging semiconductor according to claim 6, it is characterised in that after cutting the packaging body, the encapsulation
The cut surface of unit lateral leads and the pin of bottom surface expose, and in electroless plating step, the metal for exposing to the encapsulation unit is cut
Face whole plated metal.
8. method for packaging semiconductor according to claim 6, it is characterised in that the insulating carrier is UV films.
9. method for packaging semiconductor according to claim 8, it is characterised in that it is nonmetallic that the UV films one side is fixed on one
On supporter, another side is combined with the first face of the packaging body.
10. method for packaging semiconductor according to claim 8 or claim 9, it is characterised in that removing the step of the insulating carrier
In rapid, the UV films are removed using the method for irradiating ultraviolet light.
11. a kind of packaging body, it is characterised in that including multiple settings on the same vector and encapsulation unit independent of each other, outside
It is exposed to the equal plated metal in metal section of each encapsulation unit, the carrier is conductive carrier or insulating carrier, described
Conductive carrier is the carrier of the lead frame before packaging body encapsulation.
12. packaging body according to claim 11, it is characterised in that the carrier be arranged on the encapsulation unit have draw
Wire frame or the carrier be arranged on the encapsulation unit away from lead frame while.
13. a kind of encapsulation unit, it is characterised in that the encapsulation unit at least has what cutting was formed in two adjacent sides
Metal section, all metal sections are all covered with the coat of metal, and every one side of the encapsulation unit, which is both provided with, to be drawn
Foot, and the metal section of each pin is all covered with the coat of metal, the intersection at least two faces of the pin, which has, to be separated
Band, the coat of metal of dividing strip both sides have difference characteristic.
14. encapsulation unit according to claim 13, it is characterised in that the coat of metal uniform one of each metal section
Cause.
15. encapsulation unit according to claim 13, it is characterised in that the difference characteristic is dividing strip both sides metal-plated
The thickness of layer is different.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510874625.5A CN105513976B (en) | 2015-12-02 | 2015-12-02 | Method for packaging semiconductor, packaging body and encapsulation unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510874625.5A CN105513976B (en) | 2015-12-02 | 2015-12-02 | Method for packaging semiconductor, packaging body and encapsulation unit |
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| CN105513976A CN105513976A (en) | 2016-04-20 |
| CN105513976B true CN105513976B (en) | 2018-04-17 |
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| CN201510874625.5A Active CN105513976B (en) | 2015-12-02 | 2015-12-02 | Method for packaging semiconductor, packaging body and encapsulation unit |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106048679A (en) * | 2016-05-30 | 2016-10-26 | 北京首钢微电子有限公司 | Electroplating method of integrated circuit |
| CN110718484A (en) * | 2019-09-24 | 2020-01-21 | 日月光封装测试(上海)有限公司 | Method for separating integrated circuit packages |
| CN113035721A (en) * | 2019-12-24 | 2021-06-25 | 维谢综合半导体有限责任公司 | Packaging process for plating conductive film on side wall |
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|---|---|---|---|---|
| US4996587A (en) * | 1989-04-10 | 1991-02-26 | International Business Machines Corporation | Integrated semiconductor chip package |
| CN101090077A (en) * | 2006-06-12 | 2007-12-19 | 矽品精密工业股份有限公司 | Semiconductor package and its manufacturing method |
| CN102237324A (en) * | 2010-04-29 | 2011-11-09 | 国碁电子(中山)有限公司 | Integrated circuit packaging structure and method |
| CN102683315A (en) * | 2011-11-30 | 2012-09-19 | 江苏长电科技股份有限公司 | Barrel-plating four-side pinless packaging structure and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7405468B2 (en) * | 2003-04-11 | 2008-07-29 | Dai Nippon Printing Co., Ltd. | Plastic package and method of fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4996587A (en) * | 1989-04-10 | 1991-02-26 | International Business Machines Corporation | Integrated semiconductor chip package |
| CN101090077A (en) * | 2006-06-12 | 2007-12-19 | 矽品精密工业股份有限公司 | Semiconductor package and its manufacturing method |
| CN102237324A (en) * | 2010-04-29 | 2011-11-09 | 国碁电子(中山)有限公司 | Integrated circuit packaging structure and method |
| CN102683315A (en) * | 2011-11-30 | 2012-09-19 | 江苏长电科技股份有限公司 | Barrel-plating four-side pinless packaging structure and manufacturing method thereof |
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