CN105513953B - Improve the process control method that high tension apparatus performance changes with resistance substrate rate - Google Patents
Improve the process control method that high tension apparatus performance changes with resistance substrate rate Download PDFInfo
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- CN105513953B CN105513953B CN201510992546.4A CN201510992546A CN105513953B CN 105513953 B CN105513953 B CN 105513953B CN 201510992546 A CN201510992546 A CN 201510992546A CN 105513953 B CN105513953 B CN 105513953B
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- resistance substrate
- high pressure
- drift region
- substrate
- substrate rate
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- 239000000758 substrate Substances 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000004886 process control Methods 0.000 title claims abstract description 7
- 238000002347 injection Methods 0.000 claims abstract description 28
- 239000007924 injection Substances 0.000 claims abstract description 28
- 230000005516 deep trap Effects 0.000 claims abstract description 20
- 238000013507 mapping Methods 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 238000002474 experimental method Methods 0.000 claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 claims abstract description 5
- 238000005259 measurement Methods 0.000 claims abstract description 4
- 230000035945 sensitivity Effects 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Manufacturing & Machinery (AREA)
- Pressure Sensors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of process control methods for improving high tension apparatus performance and changing with resistance substrate rate, include the following steps：Substrate is divided into different sections by step 1 according to resistance substrate rate specification；Step 2, the silicon substrate for choosing different sections, by deep trap and high pressure drift region injection experiments, find the injection condition of respective bins；Step 3 sets deep trap and high pressure drift region injection condition and resistance substrate rate mapping table in technological process, in IC manufacturing processes, the resistivity of first on-line measurement substrate, in subsequent injection step according to deep trap and high pressure drift region injection condition and the corresponding injection condition of resistance substrate rate mapping table selection.The present invention improves its performance when high tension apparatus can be made to change with resistance substrate rate.
Description
Technical field
The present invention relates to semiconductor integrated circuit field, more particularly to a kind of improvement high tension apparatus performance with resistance substrate
The process control method of rate variation.
Background technology
At present, common LDMOS (lateral diffusion metal oxide semiconductor) structure such as Fig. 2 institutes in semiconductor fabrication
Show.Wherein, 1 is silicon substrate, and 2 be field oxide (STI or LOCOS), and 3 be polysilicon gate, and 4 be deep trap injection region, and 5 be high pressure
Drift about injection region, and 6 be body injection region, and 7 be source and drain injection region, and 8 draw injection region for body.
The net dopant concentration of deep trap injection region and high pressure drift injection region determines the breakdown voltage of device, drift region series connection
The device properties such as resistance.
The variation of resistance substrate rate can have an impact deep trap and high pressure drift region net dopant concentration, cause device performance wave
It is dynamic.
Invention content
The technical problem to be solved in the present invention is to provide a kind of works for improving high tension apparatus performance and changing with resistance substrate rate
Skill control method improves its performance when high tension apparatus can be made to change with resistance substrate rate.
In order to solve the above technical problems, the technology controlling and process that the improvement high tension apparatus performance of the present invention changes with resistance substrate rate
Method includes the following steps：
Substrate is divided into different sections by step 1 according to resistance substrate rate specification；
Step 2, the silicon substrate for choosing different stalls, by deep trap and high pressure drift region injection experiments, find respective bins
Injection condition；
Step 3 sets deep trap and high pressure drift region injection condition and resistance substrate rate mapping table in technological process,
In IC (integrated circuit) manufacturing process, the resistivity of first on-line measurement substrate, in subsequent injection step according to deep trap and height
Press drift region injection condition and the corresponding injection condition of resistance substrate rate mapping table selection；
According to the technique sensitivity of different components, the section is increased or decreased.
Advantageous effect possessed by method using the present invention is：Impurity concentration and deep trap for high tension apparatus substrate and
High pressure drift doping concentration can compare, and change in resistance can generate shadow for deep trap and high pressure drift region net dopant concentration
It rings, the distribution of device space charged region electric field is caused to change, so as to influence the breakdown voltage of device and drift region series resistance.
Deep trap and high pressure drift region net dopant concentration are changed according to the resistivity of silicon substrate, keep the net doping of corresponding region
Concentration is constant, can keep the space-charge region electric field distribution of high tension apparatus.Improve the technology stability of high tension apparatus.Profit simultaneously
The resistance substrate rate range that can be used can be improved with the method for the present invention, reduces the purchase cost of chip.For example originally may be used
Resistance substrate rate range with use is central value plus-minus 10%, and plus-minus 30% can be expanded to by the method for the present invention；It can
2 times are increased with the substrate range used.
Description of the drawings
The present invention is described in further detail with specific embodiment below in conjunction with the accompanying drawings：
Fig. 1 is the process control method flow chart that the improvement high tension apparatus performance changes with resistance substrate rate；
Fig. 2 is existing LDMOS device structure chart；
Fig. 3 is 80V high tension apparatus breakdown voltage with change in resistance relational graph.
Specific embodiment
With reference to shown in Fig. 1, the improvement high tension apparatus performance is below with the process control method that resistance substrate rate changes
Embodiment in, include the following steps：
Substrate is divided into different sections according to resistance substrate rate specification by step 1, for example, resistivity for 14~
The substrate of 24ohm.cm can be divided into 14~16,16~18,18~20,20~22,22~24 totally 5 sections.According to difference
The technique sensitivity of device, can increase or decrease section.
Step 2, the silicon substrate for choosing different stalls, by deep trap and high pressure drift region injection experiments, find corresponding gear
Injection condition.The deep trap refers to trap of the junction depth at 1 micron or more, and the high pressure refers to applied voltage in 50V to 1000V.
Step 3 sets deep trap and high pressure drift region injection condition and resistance substrate rate mapping table in technological process,
In IC manufacturing processes, the resistivity of first on-line measurement substrate is noted in subsequent injection step according to deep trap and high pressure drift region
Enter condition and the corresponding injection condition of resistance substrate rate mapping table selection.
With reference to shown in Fig. 3, in resistance substrate rate in the variation range from 14ohm.cm to 25ohm.cm, 80V devices are hit
It wears voltage and will appear fluctuation more than 20V.Through experiment it can be seen that as resistivity increases, the raising of higher-pressure region net dopant concentration,
High tension apparatus space-charge region area becomes smaller.The variation of high tension apparatus net dopant concentration can be adjusted by changing deep trap implantation dosage
It is distributed with space-charge region electric field, and changing rule is approximate with substrate doping variation.
The present invention is described in detail above by specific embodiment, but these are not formed to the present invention's
Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these
It should be regarded as protection scope of the present invention.
Claims (1)
1. a kind of process control method for improving high tension apparatus performance and changing with resistance substrate rate, which is characterized in that including as follows
Step：
Substrate is divided into different sections by step 1 according to resistance substrate rate specification；
Step 2, the silicon substrate for choosing different sections, by deep trap and high pressure drift region injection experiments, find the note of respective bins
Enter condition；
Step 3 sets deep trap and high pressure drift region injection condition and resistance substrate rate mapping table in technological process, in IC
In manufacturing process, the resistivity of first on-line measurement substrate injects item in subsequent injection step according to deep trap and high pressure drift region
Part and the corresponding injection condition of resistance substrate rate mapping table selection；
According to the technique sensitivity of different components, the section is increased or decreased.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510992546.4A CN105513953B (en) | 2015-12-25 | 2015-12-25 | Improve the process control method that high tension apparatus performance changes with resistance substrate rate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510992546.4A CN105513953B (en) | 2015-12-25 | 2015-12-25 | Improve the process control method that high tension apparatus performance changes with resistance substrate rate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105513953A CN105513953A (en) | 2016-04-20 |
| CN105513953B true CN105513953B (en) | 2018-06-19 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201510992546.4A Active CN105513953B (en) | 2015-12-25 | 2015-12-25 | Improve the process control method that high tension apparatus performance changes with resistance substrate rate |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111969039A (en) * | 2020-08-10 | 2020-11-20 | 湖南大学 | Substrate wafer structure for improving substrate resistivity and preparation method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3885999A (en) * | 1971-12-15 | 1975-05-27 | Ates Componenti Elettron | Planar epitaxial process for making linear integrated circuits |
| CN101225506A (en) * | 2007-01-17 | 2008-07-23 | 中芯国际集成电路制造(上海)有限公司 | Method for monitoring ion implantation state |
| CN103151281A (en) * | 2011-12-07 | 2013-06-12 | 无锡华润上华科技有限公司 | Monitoring method for ion implantation technology |
| CN104217929A (en) * | 2014-10-11 | 2014-12-17 | 王金 | Epitaxial wafer and processing method thereof |
| CN104900499A (en) * | 2015-04-30 | 2015-09-09 | 上海华力微电子有限公司 | Dosage matching method of ion implanter |
-
2015
- 2015-12-25 CN CN201510992546.4A patent/CN105513953B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3885999A (en) * | 1971-12-15 | 1975-05-27 | Ates Componenti Elettron | Planar epitaxial process for making linear integrated circuits |
| CN101225506A (en) * | 2007-01-17 | 2008-07-23 | 中芯国际集成电路制造(上海)有限公司 | Method for monitoring ion implantation state |
| CN103151281A (en) * | 2011-12-07 | 2013-06-12 | 无锡华润上华科技有限公司 | Monitoring method for ion implantation technology |
| CN104217929A (en) * | 2014-10-11 | 2014-12-17 | 王金 | Epitaxial wafer and processing method thereof |
| CN104900499A (en) * | 2015-04-30 | 2015-09-09 | 上海华力微电子有限公司 | Dosage matching method of ion implanter |
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| CN105513953A (en) | 2016-04-20 |
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