CN105511583A - Power-fail protection circuit and method for storage device - Google Patents
Power-fail protection circuit and method for storage device Download PDFInfo
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- CN105511583A CN105511583A CN201510870803.7A CN201510870803A CN105511583A CN 105511583 A CN105511583 A CN 105511583A CN 201510870803 A CN201510870803 A CN 201510870803A CN 105511583 A CN105511583 A CN 105511583A
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- memory device
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/16—Protection against loss of memory contents
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention relates to the field of electrocommunication and discloses a power-fail protection circuit and method for a storage device. The power-fail protection circuit comprises a control circuit and an energy storage element, wherein the control circuit is used for responding to a power-fail reset signal of a host system and disconnecting power supply connection between a host system and the storage device; under the situation that the power supply connection is disconnected, the energy storage element is used for supplying power to the storage device for a reset period of time. By means of the power-fail protection circuit and method for the storage device, the problem of reliability of flash equipment containing an FTL layer under the situation of accident power-fail can be solved, and thus the flash equipment containing the FTL layer can be applied to the network communication field which is high in reliability requirement.
Description
Technical field
The present invention relates to electronic communication field, particularly, relate to a kind of power-down protection circuit for memory device and method.
Background technology
The memory device (hereinafter referred to as " flash equipment ") of flash memory flash device composition is extensively present in portable electric appts and computer equipment, flash equipment adds 1 flash chip (e.g., nand flash memory chip) composition by a controller usually.Because host interface is generally file system interface, and flash device belongs to block device, so have a controller between flash device and host interface serial bus USB to perform map operation, controller performs map operation by flash translation layer (FTL) (flashTranslationLayer is hereinafter referred to as " FTL ").
FTL is a conversion layer between nand flash memory chip and base file system, and it enables operating system and file system as access hard disk, access flash equipment.
The flash equipment comprising FTL layer has small size, high performance feature usually, the file system such as file configuration table table FAT (FileAllocationTable), NTFS (NewTechnologyFileSystem, New Technology File System) can be made to operate single stage unit nand flash memory chip as operating other any memory device.
But the flash equipment comprising FTL has individual serious problems, be exactly SRAM and DRAM that FTL mapping table needs to be kept at controller inside, after data rewriting completes by the time, then mapping table be updated in nand flash memory chip.If run into accident power-off, so there is the possibility damaged in mapping table, once mapping table damages, the flash equipment comprising FTL layer needs formatted usually, or cannot read and write again, needs to return factory or use specific purpose tool just can recover.Therefore, although the existence of FTL layer simplifies the difficulty of system, the unreliability of data can be caused, make cannot be used for storing the data in the higher field of security request data as flash equipment such as u dishes.
And for above-mentioned technical matters in prior art, the mode of the main nand flash memory chip that uses and file system and no longer adopt FTL layer.The advantage using which is to rebuild after loss of data, and after reformatting, product can continue to use.But for the mode of nand flash memory chip and file system, need to develop the erasure balance that special file system does data, the safeguard measures such as garbage reclamation.
Summary of the invention
The object of this invention is to provide a kind of power-down protection circuit for memory device and method, it can realize when accident power-off, and protection FTL mapping table is not damaged.
To achieve these goals, the invention provides a kind of power-down protection circuit for memory device, this circuit comprises: control circuit, disconnects this host computer system be electrically connected with the confession of described memory device for the power-off reset signal in response to host computer system; And energy-storage travelling wave tube, when described confession electrical connection is disconnected, this energy-storage travelling wave tube is used for powering a schedule time for described memory device.
Preferably, described memory device comprises controller and flash memory flash device, the described schedule time according to described host computer system to the write of described memory device and/or Update Table time, sum time delay that flash translation layer (FTL) FTL mapping table is updated to described flash device by the data propagation delay time of general-purpose serial bus USB and described controller is determined.
Preferably, the described schedule time is the time delay 2 times of sum that flash translation layer (FTL) FTL mapping table is updated to described flash device by the data propagation delay time of described USB and described controller.
Preferably, described energy-storage travelling wave tube is storage capacitor, and the capacitance of this storage capacitor was determined according to the described schedule time.
Preferably, described control circuit is mos pipe or relay.
Correspondingly, the present invention also provides a kind of power-off protection method for memory device, and the method comprises: disconnect this host computer system in response to the power-off reset signal of host computer system and be electrically connected with the confession of described memory device; And when described confession electrical connection is disconnected, energy-storage travelling wave tube is that described memory device is powered a schedule time.
Preferably, described memory device comprises controller and flash memory flash device, the described schedule time according to described host computer system to the write of described memory device and/or Update Table time, sum time delay that flash translation layer (FTL) FTL mapping table is updated to described flash device by the data propagation delay time of general-purpose serial bus USB and described controller is determined.
Preferably, the described schedule time is the time delay 2 times of sum that flash translation layer (FTL) FTL mapping table is updated to described flash device by the data propagation delay time of described USB and described controller.
Preferably, described energy-storage travelling wave tube is storage capacitor, and the capacitance of this storage capacitor was determined according to the described schedule time.
Preferably, described control circuit is mos pipe or relay.
Pass through technique scheme; by increasing by a power-down protection circuit; make when host computer system accident power-off; for memory device is powered a period of time; and then protection FTL mapping table is not damaged; and ensure that the data of FTL mapping table can be updated to flash device, improve the reliability of memory device, and then make memory device can be used for the higher network communication field of reliability requirement.
Other features and advantages of the present invention are described in detail in embodiment part subsequently.
Accompanying drawing explanation
Accompanying drawing is used to provide a further understanding of the present invention, and forms a part for instructions, is used from explanation the present invention, but is not construed as limiting the invention with embodiment one below.In the accompanying drawings:
Fig. 1 shows the structured flowchart of the power-down protection circuit for memory device provided by the present invention;
Circuit connection diagram concrete when Fig. 2 shows that in the present invention, control circuit is mos pipe;
Circuit connection diagram concrete when Fig. 3 shows that in the present invention, control circuit is relay; And
Fig. 4 shows the circuit diagram of the power-down protection circuit for memory device according to an embodiment of the present invention.
Description of reference numerals
100 control circuit 200 energy-storage travelling wave tubes
210 storage capacitor 110 voltage amplifier circuits
120 relay 300U dishes
400mos pipe 410 the one mos manages
420 the 2nd mos pipes
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Should be understood that, embodiment described herein, only for instruction and explanation of the present invention, is not limited to the present invention.
Fig. 1 shows the structured flowchart of the power-down protection circuit for memory device provided by the present invention.As shown in Figure 1, the invention provides a kind of power-down protection circuit for memory device, this circuit comprises: control circuit 100, disconnects this host computer system be electrically connected with the confession of described memory device for the power-off reset signal in response to host computer system; And energy-storage travelling wave tube 200, when described confession electrical connection is disconnected, this energy-storage travelling wave tube is used for powering a schedule time for described memory device.Memory device as described herein is mainly for the flash equipment comprising FTL layer, this memory device can be SD (SecureDigital, safe digital) card, TF (MicroSD) card, CF (CompactFlash) card, USB flash disk etc.
Preferably, energy-storage travelling wave tube 200 can be storage capacitor, but the present invention is not restricted to this.
Wherein, control circuit 200 can be a switch, and preferably, control circuit 200 can be mos (MetalOxideSemiconductor, metal-oxide semiconductor (MOS)) pipe or relay.
Circuit connection diagram concrete when Fig. 2 shows that in the present invention, control circuit is mos pipe.As shown in Figure 2, control circuit 200 is mos pipe, reset signal is connected to the grid of mos pipe through voltage amplifier circuit 110, here two mos pipes are comprised, the source electrode of the one mos pipe 410 and the 2nd mos pipe 420 links together, the drain electrode of the one mos pipe 410 is connected with the power supply input of memory device, the drain electrode of the 2nd mos pipe 420 is connected with memory device, namely a mos pipe 410 is connected with the 2nd mos pipe 420 mirror image, to prevent the reverse direction current flow in a mos pipe 410 and the 2nd mos pipe 420.In host computer system, the high voltage of reset signal is generally 3.3V, and low-voltage is 0V.
When host computer system normally works (non-power down), reset signal is in high voltage 3.3V, this 3.3V voltage transitions can be the voltage enough making a mos pipe 410 and the 2nd mos pipe 420 conducting by voltage amplifier circuit 110, such as, can be 12V voltage by this 3.3V voltage transitions, normally work to make memory device.When the unexpected power down of host computer system, reset signal changes low-voltage 0V into by high voltage, after the grid of the one mos pipe 410 and the 2nd mos pipe 420 receives this 0V, one mos pipe 410 and the 2nd mos pipe 420 are in nonconducting state, and then disconnect the confession electrical connection of host computer system and memory device.
Circuit connection diagram concrete when Fig. 3 shows that in the present invention, control circuit is relay.As shown in Figure 3, control circuit 200 is relay 120, and reset signal is connected to the positive pole of relay 120 through voltage amplifier circuit 110, and normally opened contact one end for relay is connected with the power supply input of memory device, and the other end is connected with memory device.
When host computer system normally works (non-power down), reset signal is in high voltage 3.3V, voltage amplifier circuit 110 can by this 3.3V voltage transitions for more high voltage is electric to make relay 120 obtain, relay 120 electric after, normally opened contact is closed and then memory device is normally worked.When the unexpected power down of host computer system, reset signal changes low-voltage 0V into by high voltage, relay 120 dead electricity, and normally opened contact disconnects, and then disconnects the confession electrical connection of host computer system and memory device.
In one embodiment, memory device can be USB flash disk.Fig. 4 shows the circuit diagram of the power-down protection circuit for memory device according to an embodiment of the present invention; as shown in Figure 4; power-down protection circuit for USB flash disk 300 comprises: mos pipe 400, storage capacitor 210; when host computer system power down; power-off reset signal control mos pipe 400 disconnects host computer system and inputs the power supply of USB flash disk; prevent other load of current direction of storage capacitor 200, storage capacitor 210 can be powered a schedule time for USB flash disk equipment.
In addition, control circuit 100 disconnects this host computer system and is electrically connected with the confession of described memory device in response to the power-off reset signal of host computer system, but not disconnect in response to the signal of host computer system power supply power-fail this host computer system and described memory device for being electrically connected, because host computer system power down is a process slowly, such as, for most of flash chip of power supply 3.3V, the whole power process of host computer system may continue a few tens of milliseconds, when stop accessing storage device by the power failure signal of the host computer system host computer system that can not know for sure.But generally, host computer system includes a reset control circuit, when power supply power-fail to a certain extent time, power-off reset signal is lowered, ensure that host computer system is in reset mode, the moment that power-off reset signal is lowered can think last moment of host computer system accessing storage device.
Memory device (comprising the flash equipment of FTL layer) in the present invention generally comprises controller and flash memory flash device, generally, the delay in the moment of flash device write by the controller in moment and memory device that host computer system writes memory device is different, that is, when host computer system is to memory device write and/or Update Table, the data transmission of general-purpose serial bus USB has a time delay, and flash translation layer (FTL) FTL mapping table is updated to described flash device by controller also has a time delay, therefore, the above-mentioned schedule time can according to this two time delay sum determine.This schedule time can ensure when host computer system power down, and the controller of memory device is stored in data in SRAM and FTL mapping table is updated to flash device, and can not be lost.
Preferably, the schedule time is the time delay 2 times of sum that flash translation layer (FTL) FTL mapping table is updated to described flash device by the data propagation delay time of described USB and described controller.But the present invention is not restricted to this.
Wherein, the time delay that FTL mapping table is updated to flash device by the data propagation delay time of USB and controller can be obtained by actual test, and the time delay obtained measured by different memory devices is not identical.
Correspondingly, the electric capacity of storage capacitor 210 was determined according to the above-mentioned schedule time.Particularly, the electric capacity of storage capacitor 210 is calculated by the working current I of the schedule time, memory device and operating voltage U.
The discharge and recharge formula of electric capacity is: I=C* △ U/ △ t, when thinking that memory device supply voltage drops to 90% of its operating voltage here, and memory device cisco unity malfunction.Then △ U=U-0.9*U=0.1*U, then electric capacity C=I* △ t/ △ U=10*I* △ t/U, wherein △ t is the above-mentioned schedule time, and working current I can be obtained by actual measurement.For USB flash disk, the operating voltage of USB flash disk is 5V, so the electric capacity C1=2*I* △ t of storage capacitor 200.
Power-down protection circuit for memory device provided by the present invention can be installed in host computer system, but is not restricted to this.
In addition, the present invention also provides a kind of power-off protection method for memory device, and the method comprises: disconnect this host computer system in response to the power-off reset signal of host computer system and be electrically connected with the confession of described memory device; And when described confession electrical connection is disconnected, energy-storage travelling wave tube is that described memory device is powered a schedule time.The idiographic flow of the method and benefit similar to the above-mentioned power-down protection circuit for memory device, repeat no more here.
By the power-down protection circuit for memory device provided by the invention and method; the integrity problem of flash equipment when unexpected power down comprising FTL layer can be solved, and then make the flash equipment comprising FTL layer can be used for the higher network communication field of reliability requirement.
Below the preferred embodiment of the present invention is described in detail by reference to the accompanying drawings; but; the present invention is not limited to the detail in above-mentioned embodiment; within the scope of technical conceive of the present invention; can carry out multiple simple variant to technical scheme of the present invention, these simple variant all belong to protection scope of the present invention.
It should be noted that in addition, each concrete technical characteristic described in above-mentioned embodiment, in reconcilable situation, can be combined by any suitable mode, in order to avoid unnecessary repetition, the present invention illustrates no longer separately to various possible array mode.
In addition, also can carry out combination in any between various different embodiment of the present invention, as long as it is without prejudice to thought of the present invention, it should be considered as content disclosed in this invention equally.
Claims (10)
1. for a power-down protection circuit for memory device, it is characterized in that, this circuit comprises:
Control circuit, disconnects this host computer system and is electrically connected with the confession of described memory device for the power-off reset signal in response to host computer system; And
Energy-storage travelling wave tube, when described confession electrical connection is disconnected, this energy-storage travelling wave tube is used for powering a schedule time for described memory device.
2. protection circuit according to claim 1, is characterized in that, described memory device comprises controller and flash memory flash device;
The described schedule time according to described host computer system to the write of described memory device and/or Update Table time, the time delay that flash translation layer (FTL) FTL mapping table is updated to described flash device is determined by the data propagation delay time of general-purpose serial bus USB and described controller.
3. protection circuit according to claim 2, is characterized in that, the described schedule time is the time delay 2 times of sum that flash translation layer (FTL) FTL mapping table is updated to described flash device by the data propagation delay time of described USB and described controller.
4. protection circuit according to claim 1, is characterized in that, described energy-storage travelling wave tube is storage capacitor, and the capacitance of this storage capacitor was determined according to the described schedule time.
5. according to the protection circuit in claim 1-4 described in any one claim, it is characterized in that, described control circuit is mos pipe or relay.
6. for a power-off protection method for memory device, it is characterized in that, the method comprises:
Disconnect this host computer system to be electrically connected with the confession of described memory device in response to the power-off reset signal of host computer system; And
When described confession electrical connection is disconnected, energy-storage travelling wave tube is that described memory device is powered a schedule time.
7. method according to claim 6, is characterized in that, described memory device comprises controller and flash memory flash device;
The described schedule time according to described host computer system to the write of described memory device and/or Update Table time, sum time delay that flash translation layer (FTL) FTL mapping table is updated to described flash device by the data propagation delay time of general-purpose serial bus USB and described controller is determined.
8. method according to claim 7, is characterized in that, the described schedule time is the time delay 2 times of sum that flash translation layer (FTL) FTL mapping table is updated to described flash device by the data propagation delay time of described USB and described controller.
9. method according to claim 6, is characterized in that, described energy-storage travelling wave tube is storage capacitor, and the capacitance of this storage capacitor was determined according to the described schedule time.
10. according to the method in claim 6-9 described in any one claim, it is characterized in that, described control circuit is mos pipe or relay.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510870803.7A CN105511583A (en) | 2015-12-02 | 2015-12-02 | Power-fail protection circuit and method for storage device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510870803.7A CN105511583A (en) | 2015-12-02 | 2015-12-02 | Power-fail protection circuit and method for storage device |
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| CN105511583A true CN105511583A (en) | 2016-04-20 |
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| CN201510870803.7A Pending CN105511583A (en) | 2015-12-02 | 2015-12-02 | Power-fail protection circuit and method for storage device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106502928A (en) * | 2016-09-29 | 2017-03-15 | 华为技术有限公司 | A kind of storage system power-off protection method, storage control and electronic equipment |
| CN112559395A (en) * | 2020-12-18 | 2021-03-26 | 国电南瑞科技股份有限公司 | Relay protection device and method based on dual-Soc storage system exception handling mechanism |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050144368A1 (en) * | 2003-12-30 | 2005-06-30 | Samsung Electronics Co., Ltd. | Address mapping method and mapping information managing method for flash memory, and flash memory using the same |
| CN102355046A (en) * | 2011-09-09 | 2012-02-15 | Tcl新技术（惠州）有限公司 | Voltage detection and power failure protection device and implementation method |
| CN102496907A (en) * | 2011-12-02 | 2012-06-13 | 北京赛科世纪数码科技有限公司 | Set top box, power fail safeguard device and power fail data protection method |
| CN104090527A (en) * | 2014-07-01 | 2014-10-08 | 深圳市英威腾电气股份有限公司 | Power-down protection device |
-
2015
- 2015-12-02 CN CN201510870803.7A patent/CN105511583A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050144368A1 (en) * | 2003-12-30 | 2005-06-30 | Samsung Electronics Co., Ltd. | Address mapping method and mapping information managing method for flash memory, and flash memory using the same |
| CN102355046A (en) * | 2011-09-09 | 2012-02-15 | Tcl新技术（惠州）有限公司 | Voltage detection and power failure protection device and implementation method |
| CN102496907A (en) * | 2011-12-02 | 2012-06-13 | 北京赛科世纪数码科技有限公司 | Set top box, power fail safeguard device and power fail data protection method |
| CN104090527A (en) * | 2014-07-01 | 2014-10-08 | 深圳市英威腾电气股份有限公司 | Power-down protection device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106502928A (en) * | 2016-09-29 | 2017-03-15 | 华为技术有限公司 | A kind of storage system power-off protection method, storage control and electronic equipment |
| WO2018059361A1 (en) * | 2016-09-29 | 2018-04-05 | 华为技术有限公司 | Power down protection method for storage system, storage controller, and electronic device |
| CN106502928B (en) * | 2016-09-29 | 2019-08-20 | 华为技术有限公司 | A kind of storage system power-off protection method, storage control and electronic equipment |
| CN112559395A (en) * | 2020-12-18 | 2021-03-26 | 国电南瑞科技股份有限公司 | Relay protection device and method based on dual-Soc storage system exception handling mechanism |
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Application publication date: 20160420 |