CN105489638B - Backside structure of insulated gate bipolar transistor and preparation method thereof - Google Patents
Backside structure of insulated gate bipolar transistor and preparation method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 claims abstract description 27
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- 238000002347 injection Methods 0.000 claims abstract description 8
- 239000007924 injection Substances 0.000 claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 210000002421 cell wall Anatomy 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 238000002513 implantation Methods 0.000 claims description 27
- 239000000126 substance Substances 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 4
- 239000002019 doping agent Substances 0.000 claims description 3
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- -1 phosphonium ion Chemical class 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
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- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 238000010248 power generation Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
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- 239000011248 coating agent Substances 0.000 description 1
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- 238000005520 cutting process Methods 0.000 description 1
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- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- PQIOSYKVBBWRRI-UHFFFAOYSA-N methylphosphonyl difluoride Chemical group CP(F)(F)=O PQIOSYKVBBWRRI-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0821—Collector regions of bipolar transistors
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- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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Abstract
The present invention relates to a kind of backside structures of insulated gate bipolar transistor, backside trench is equipped at intervals at the back side of silicon wafer, angle α between the cell wall and horizontal plane of backside trench is at 60~88 °, overleaf the channel bottom of groove and side wall form the N+ type field cutoff layer of channel form and the P+ type collector layer of channel form by injection, the N+ type field cutoff layer of channel form is connected with N-type substrate, the P+ type collector layer of channel form is connected with the slot bottom of N+ type field cutoff layer and side wall, the groove top surface of N+ type field cutoff layer and the groove top surface of P+ type collector layer are connected with N+ type collector layer, the metal layer 5 at the back side being connected on N+ type collector layer 6 and the raised 5-1 that corresponding 4 inner metal layer 5 of backside trench is arranged in form collector.The present invention can reduce manufacturing cost and fragment rate, not need that a cut-off type insulated gate bipolar transistor can be realized by thin slice technique.
Description
Technical field
The present invention relates to backside structures of a kind of insulated gate bipolar transistor and preparation method thereof, belong to insulated gate bipolar crystalline substance
Body Manifold technology field.
Background technique
Insulated gate bipolar transistor (IGBT) by double pole triode and insulating gate type field effect tube and at compound full control
Type voltage driven type power semiconductor, with insulating gate type field effect tube high input impedance and double pole triode it is low
The advantages that conduction voltage drop and driving circuit are simple, safety operation area is wide, no matter in terms of the technological transformation of conventional industries, such as
Electric machine speed regulation, various high frequency switch powers etc., or in terms of the exploitation of new energy, such as solar power generation, wind power generation and new
In terms of energy automobile etc. and new industry, such as smart grid, rail traffic, as power electronic system core switching device
The IGBT of part plays the crucial effect that do not replace.
For IGBT optimization, Facad structure has been upgraded to trench gate structure from planar gate structure, and backside structure is from wearing
Logical (PT), non-break-through (NPT) have been upgraded to thin slice electric field cut-off (FS) technology, so that device property becomes closer to technology original
Point, low pressure drop, low-loss improve power consumption efficiency to reduce energy consumption.Conventional field blocking-up type (FS) insulated gate bipolar transistor
Pipe backside structure as shown in Figure 1, is made of N+ type barrier layer, P+ type emission layer and collector layer.However, the country can be steady now
The foundries of back side FS structure and few are quantitatively produced, one of technology barrier of domestic IGBT substitution import IGBT is become.Due to
Blocking-up type (FS) structure for back side of IGBT needs to process using thin slice technique, and thin slice processing systems and work
Skill requires particularly customized, causes chip manufacture costly, and chip is easy fragment.
Summary of the invention
The object of the present invention is to provide backside structures of a kind of insulated gate bipolar transistor and preparation method thereof, can reduce system
This and fragment rate are caused, does not need that a cut-off type insulated gate bipolar transistor can be realized by thin slice technique.
The technical solution of the present invention in order to achieve the above objectives is: a kind of backside structure of insulated gate bipolar transistor, special
Sign is: be equipped at intervals with backside trench at the back side of silicon wafer, the angle α between the cell wall and horizontal plane of backside trench 60~
88 °, overleaf the channel bottom of groove and side wall form the N+ type field cutoff layer of channel form and the P+ type of channel form by injection
The N+ type field cutoff layer of collector layer, channel form is connected with N-type substrate, the P+ type collector layer and N+ type field cutoff layer of channel form
Slot bottom and side wall be connected, the groove top surface and N+ type collector layer of the groove top surface of N+ type field cutoff layer and P+ type collector layer
It is connected, the metal layer 5 at the back side being connected on N+ type collector layer 6 and the protrusion that corresponding 4 inner metal layer 5 of backside trench is set
5-1 forms collector.
Wherein: the groove on the groove and P+ type collector layer in backside trench, N+ type field cutoff layer on the silicon wafer
It is trapezoidal.
The depth h of the backside trench in 10~100um, groove width b in 5~50um, two backside trench centers away from H 50~
150um。
The thickness δ of the N+ type collector layer is in 0.1~0.5um.
The thickness δ 2 of N+ type field cutoff layer is in 0.5~5um.
The thickness δ 1 of the P+ type collector layer is in 0.1~0.5um.
The production method of the backside structure of insulated gate bipolar transistor of the present invention, it is characterised in that: by insulated gate bipolar crystalline substance
After body pipe front side of silicon wafer technique carries out, sequentially include the following steps:
(1) silicon chip back side, is thinned to 150~250um；
(2), N-type ion is overleaf injected, implantation dosage is 5E14~5E15/cm2, Implantation Energy is 30~400KeV, shape
At thickness δ 0.1~0.5um N+ type collector layer；
(3), chemical wet etching groove forms backside trench, and backside trench side wall and plane included angle α be at 60~88 °, back side ditch
The depth h of slot is in 10~100um, and groove width b is in 5~50um；
(4), overleaf the trench bottom of groove and side wall implanted dopant are N-type ion, and implantation dosage is 5E11~5E14/
cm2, Implantation Energy is 30KeV~11MeV, forms the N+ type field cutoff layer of channel form, and the thickness δ 2 of N+ type field cutoff layer exists
0.5~5um；
(5), again in the channel bottom and side wall injecting p-type ion of N+ type field cutoff layer, implantation dosage is 5E14~5E15/
cm2, Implantation Energy is 30~170KeV, form the P+ type collector layer of channel form, the thickness δ 1 of P+ type collector layer 0.1~
0.5um；
(6) after, annealing, overleaf deposited metal, is filled in the protrusion on metal layer in corresponding backside trench and is formed
Collector.
The present invention forms backside trench structure at the insulated gate bipolar transistor back side, and backside trench side wall is not vertical
, overleaf the trench bottom of groove and side can form the N+ type field cutoff layer and P+ type collector of channel form by injection
Layer, therefore do not need thin slice technique and back side FS structure can be realized.The present invention can have by the N+ type field cutoff layer of channel form
Effect cut-off electric field improves breakdown voltage, and forms N+ type collector layer at no trench area back side, is conducive to shorten the turn-off time,
Guarantee to realize pressure drop and turn-off speed better trade-off while breakdown voltage is met the requirements.Insulated gate bipolar transistor of the present invention
Provided with backside trench, the metal layer at the back side there is protrusion and can increase with silicon wafer contact area, reduce rear-face contact resistance,
The toughness for increasing chip, is not easy fragment, and thermal resistance is substantially reduced than sheet.
The present invention improves structure for back side of IGBT, will be brilliant after positive MOS structure completes
Piece thinning back side thickness only needs to approach with NPT back process requirement thickness, does not need for back surface of the wafer to be thinned to FS back
Face technique requires thickness, so that silicon wafer thickness is thinned to 150~250um, and can reduce the fragment rate of chip, it is unified inject N-type from
Son goes out backside trench by chemical wet etching to form N+ type collector layer, and the groove sidewall of backside trench is made not hang down with plane
Directly, then rearwardly the trench bottom of groove and slot are injected laterally N-type ion formation field cutoff layer, can effectively end electric field, raising is hit
Voltage is worn, simultaneously as vertical structure resistor coupled in parallel, the silicon wafer thickness formed at FS structure is relatively thin, and pressure drop is small, it is ensured that device
Part entirety pressure drop is still smaller.And FS structure, because chip is relatively thin, itself turns off just than very fast in turn off process, no groove
Area's back portion keeps N+ doping, to form N+ type collector layer, is conducive to the quick export in hole in turn off process, equally
Be conducive to accelerate turn-off speed.The present invention has only been partially formed thin slice technique, compared to NPT technique, because backside trench is deposited
, the contact area of back metal and silicon is increased, rear-face contact resistance is reduced, while also increasing the toughness of chip, this
FS back process can be realized without the aid of thin slice technique in invention, and is able to achieve the optimization of parameter, has great importance.
Detailed description of the invention
The embodiment of the present invention is described in further detail with reference to the accompanying drawing.
Fig. 1 is the schematic diagram of former structure for back side of IGBT.
Fig. 2 is the schematic diagram of structure for back side of IGBT of the present invention.
Fig. 3 is the contrast schematic diagram of insulated gate bipolar transistor characteristic of the present invention and FS technique and NPT operational characteristic.
Wherein: 1-silicon wafer, 2-N+ type field cutoff layers, 3-P+ type collector layers, 4-backside trench, 5-metal layers, 5-
1-protrusion, 6-N+ type collector layers.
Specific embodiment
As shown in Figure 2, the backside structure of insulated gate bipolar transistor of the invention is equipped at intervals with back at the back side of silicon wafer 1
Face groove 4, angle α between the cell wall and horizontal plane of backside trench 4 of the invention is between 60~88 °, overleaf groove 4
Channel bottom and side wall form the N+ type field cutoff layer 2 of channel form and the P+ type collector layer 3 of channel form by injection, pass through N+
Type field cutoff layer 2 can effectively end electric field, improve breakdown voltage, while guaranteeing that breakdown voltage is met the requirements, realize preferable
Pressure drop and turn-off speed relationship.
As shown in Figure 2, the N+ type field cutoff layer 2 of channel form of the present invention is connected with N-type substrate, the P+ type collector of channel form
Layer 3 is connected with the slot bottom of N+ type field cutoff layer 2 and side wall, the groove top surface of N+ type field cutoff layer 2 and the ditch of P+ type collector layer 3
Groove top face is connected with N+ type collector layer 6, since N+ type collector layer is without groove structure, is conducive to shorten the turn-off time.This hair
The metal layer 5 at the bright back side being connected on N+ type collector layer 6 and the raised 5-1 that corresponding 4 inner metal layer 5 of backside trench is set
Collector is formed, since the raised 5-1 on metal layer 5 is arranged in corresponding backside trench 4, can increase back metal and silicon
Contact area reduces rear-face contact resistance, reduces manufacture fragment rate.
As shown in Figure 2, the backside trench 4 on silicon wafer 1 of the present invention, groove and P+ type collector on N+ type field cutoff layer 2
The trapezoidal slot of groove on layer 3, the dovetail groove can be antiparallelogram slot or inequilateral dovetail groove, the depth of backside trench 4 of the present invention
H is spent in 10~100um, and groove width b is in 5~50um, and two groove center distance H are 50~150um, by backside trench region
Accounting control, so that device pressure drop is lesser simultaneously, also reduces turn-off power loss, and silicon wafer technique is easy to control, and realizing influences
The compromise of device technology and characteristic.As shown in Figure 2, the thickness δ of N+ type collector layer 6 of the present invention is in 0.1~0.5um, N+ type field
The thickness δ 2 of cutoff layer 2 is in 0.5~5um, and the thickness δ 1 of P+ type collector layer 3 is in 0.1~0.5um.
The backside structure of insulated gate bipolar transistor of the invention, the folder between the cell wall and horizontal plane of backside trench 4
For angle α between 62~80 °, the depth h of backside trench 4 is 60 in 10~40um, two groove center distance H in 30~80um, groove width b
The thickness δ of~100um, N+ type collector layer 6 is in 0.2~0.4um, and the thickness δ 2 of N+ type field cutoff layer 2 is in 1~4um, P+ type
The thickness δ 1 of collector layer 3 is in 0.2~0.4um.
The backside structure of insulated gate bipolar transistor of the invention can also be between the cell wall and horizontal plane of backside trench 4
Angle α between 65~75 °, the depth h of backside trench 4 in 40~60um, groove width b between 25~30um, in two grooves
The heart is 70~120um away from H, and the thickness δ of N+ type collector layer 6 is in 0.2~0.5um, and the thickness δ 2 of N+ type field cutoff layer 2 exists
1.5~4um, the thickness δ 1 of P+ type collector layer 3, by Optimal Parameters, guarantee that breakdown voltage is met the requirements in 0.2~0.5um
While realize pressure drop and turn-off speed better trade-off.
The production method of the backside structure of insulated gate bipolar transistor of the present invention, by insulated gate bipolar transistor front side of silicon wafer
After technique carries out, sequentially include the following steps:
(1), by silicon wafer 1 thinning back side to 150~250um, mill can be used disappear and carry out thinned, 1 thinning back side of silicon wafer to NPT
The thickness of back process, thickness is rinsed depending on the requirement of product voltage, and after being thinned with deionized water, to keep the back side
It is clean clear, can also carry out destressing processing when necessary.
(2), N-type ion is overleaf injected, implantation dosage is 5E14~5E15/cm2, Implantation Energy is 30~400KeV, shape
At thickness δ in the N+ type collector layer 6 of 0.1~0.5um, N-type ion can be used phosphonium ion or arsenic ion, N-type injection of the present invention
Energy is 150-310KeV, and implantation dosage is 8E14~3E15/cm2When, 6 thickness of N+ type collector layer of formation 0.2~
0.4um；When N-type Implantation Energy is 160-400KeV, implantation dosage is 8E14~3E15/cm2When, the thickness of N+ type collector layer 6
δ is spent in 0.2~0.5um, and control 6 thickness of N+ type collector layer is facilitated according to Implantation Energy and dosage.
(3), chemical wet etching groove forms backside trench 4 and is exposed, develops and carves in 1 backside coating photoresist of silicon wafer
Erosion forms backside trench 4, and 4 side wall of backside trench and plane included angle α be at 60~88 °, the depth h of backside trench 4 10~
100um, groove width b are in 5~50um, and two groove center distance H are 50~150um；Such as etch the backside trench 4 of the formation angle α
Between 62~80 °, the depth h of backside trench 4 in 30~80um, groove width b 10~40um, two groove center distance H be 60~
100um；Or angle α is between 65~75 °, the depth h of backside trench 4 in 40~60um, groove width b between 25~30um,
Two groove center distance H are 70~120um, and the accounting in backside trench region can be adjusted accordingly according to application.
(4), overleaf the trench bottom of groove 4 and side wall implanted dopant are N-type ion, and implantation dosage is 5E11~5E14/
cm2, Implantation Energy is 30KeV~5MeV, forms the N+ type field cutoff layer 2 of channel form, and the thickness δ 2 of N+ type field cutoff layer 2 exists
Phosphonium ion or arsenic ion can be used in 0.5~5um, N-type ion.The present invention is when N-type Implantation Energy is in 900KeV-7.5MeV, injection
Dosage is in 5E12~5E13/cm2When, the thickness δ 2 of the N+ type field cutoff layer 2 of formation is in 1~4um, when N-type Implantation Energy is
2KeV-8MeV, implantation dosage are 5E12~5E13/cm2When, the thickness δ 2 of the N+ type field cutoff layer 2 of formation, can in 1.5~4um
It can be adjusted accordingly according to application.
(5), again in the channel bottom and side wall injecting p-type ion of N+ type field cutoff layer 2, implantation dosage is 5E14~5E15/
cm2, Implantation Energy is 30~160KeV, forms the P+ type collector layer 3 of channel form, boron ion or difluoro can be used in P-type ion
Change boron ion, the thickness δ 1 of P+ type collector layer 3 is in 0.1~0.5um.The present invention is 60-130KeV, note when p-type Implantation Energy
Entering dosage is 8E14~3E15/cm2When, the thickness δ 1 of the P+ type collector layer 3 of formation is in 0.2~0.4um；When corresponding p-type note
Entering energy is 60-170KeV, and implantation dosage is 8E14~3E15/cm2When, the thickness δ 1 of P+ type collector layer 3 0.2~
0.5um can be adjusted accordingly according to application.The present invention overleaf 4 bottom of groove by injection can be formed N+ type field cut-off
Layer 2 and P+ type collector layer 3, not needing thin slice technique can be realized back side FS structure.
(6), silicon wafer 1 is put into annealing furnace and is annealed, conventional annealing processing can be used, after annealing, overleaf deposit is golden
Belong to layer 5, can overleaf sputter or evaporate Ti-Ni-Ag, be filled in the raised 5-1 on metal layer 5 in corresponding backside trench 4
Collector is formed, with increase and silicon wafer contact area, rear-face contact resistance is reduced, increases the toughness of chip, and it is non-friable
Piece, thermal resistance are substantially reduced than sheet.
The Character Comparison of the insulated gate bipolar transistor characteristic and thin slice FS technique and NPT technique that make according to the present invention,
From figure 3, it can be seen that device property is better than NPT processing performance, pressure drop and turn-off power loss all reduced, the only more cuttings of technique
Technique is not needed using to thin slice technique, and manufacturing cost is without big increase, and fragment rate not will increase, and is avoided that thin slice technique
Bring adverse effect.
Claims (7)
1. a kind of backside structure of insulated gate bipolar transistor, it is characterised in that: be equipped at intervals with back side ditch at the back side of silicon wafer (1)
Slot (4), the angle α between the cell wall and horizontal plane of backside trench (4) at 60~88 °, overleaf the channel bottom of groove (4) and
Side wall forms the N+ type field cutoff layer (2) of channel form and the P+ type collector layer (3) of channel form, the N+ type of channel form by injection
Field cutoff layer (2) is connected with N-type substrate, the P+ type collector layer (3) of channel form and the slot bottom and side wall of N+ type field cutoff layer (2)
It is connected, the groove top surface of N+ type field cutoff layer (2) and the groove top surface of P+ type collector layer (3) and N+ type collector layer (6) phase
Even, the metal layer (5) for being connected to the back side on N+ type collector layer (6) and setting are in corresponding backside trench (4) inner metal layer (5)
Protrusion (5-1) formed collector.
2. the backside structure of insulated gate bipolar transistor according to claim 1, it is characterised in that: on the silicon wafer (1)
Backside trench (4), the groove on N+ type field cutoff layer (2) and the groove on P+ type collector layer (3) it is trapezoidal.
3. the backside structure of insulated gate bipolar transistor according to claim 1 or 2, it is characterised in that: the back side ditch
The depth h of slot (4) is in 10~100um, and groove width b is in 5~50um, and two backside trench (4) center is away from H in 50~150um.
4. the backside structure of insulated gate bipolar transistor according to claim 1 or 2, it is characterised in that: the N+ type collection
The thickness δ of electrode layer (6) is in 0.1~0.5um.
5. the backside structure of insulated gate bipolar transistor according to claim 1 or 2, it is characterised in that: N+ type field
The thickness δ 2 of cutoff layer (2) is in 0.5~5um.
6. the backside structure of insulated gate bipolar transistor according to claim 1 or 2, it is characterised in that: the P+ type collection
The thickness δ 1 of electrode layer (3) is in 0.1~0.5um.
7. the production method of the backside structure of insulated gate bipolar transistor according to claim 1, it is characterised in that: will be exhausted
After edge grid bipolar transistor front side of silicon wafer technique carries out, sequentially include the following steps:
(1), by silicon wafer (1) thinning back side to 150~250um；
(2), N-type ion is overleaf injected, implantation dosage is 5E14~5E15/cm2, Implantation Energy is 30~400KeV, is formed thick
δ is spent in the N+ type collector layer (6) of 0.1~0.5um；
(3), chemical wet etching groove forms backside trench (4), and backside trench (4) side wall and plane included angle α be at 60~88 °, the back side
The depth h of groove (4) is 50~150um in 5~50um, two groove center distance H in 10~100um, groove width b；
(4), overleaf the trench bottom of groove (4) and side wall implanted dopant are N-type ion, and implantation dosage is 5E11~5E14/cm2,
Implantation Energy is 30KeV~11MeV, forms the N+ type field cutoff layer (2) of channel form, and the thickness δ 2 of N+ type field cutoff layer (2)
In 0.5~5um；
(5), again in the channel bottom of N+ type field cutoff layer (2) and side wall injecting p-type ion, implantation dosage is 5E14~5E15/
cm2, Implantation Energy is 30~170KeV, forms the P+ type collector layer (3) of channel form, the thickness δ 1 of P+ type collector layer (3)
In 0.1~0.5um；
(6) after, annealing, overleaf deposited metal (5), make the protrusion (5-1) on metal layer (5) be filled in corresponding back side ditch
Collector is formed in slot (4).
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| CN110676314B (en) * | 2019-10-23 | 2021-05-04 | 广东美的白色家电技术创新中心有限公司 | Insulated gate bipolar transistor, power module and domestic electrical appliance |
| CN112670338B (en) * | 2020-12-23 | 2024-06-21 | 南京晟芯半导体有限公司 | SiC insulated gate bipolar transistor with low threshold voltage and manufacturing method thereof |
| CN117766575A (en) * | 2023-12-29 | 2024-03-26 | 江苏易矽科技有限公司 | RC-IGBT structure capable of inhibiting Snapback phenomenon |
| CN118099199A (en) * | 2024-04-23 | 2024-05-28 | 洛阳鸿泰半导体有限公司 | Three-dimensional semiconductor substrate wafer and method suitable for IGBT device manufacturing |
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