CN105489610A - Thin-film transistor array substrate, display panel and display device - Google Patents
Thin-film transistor array substrate, display panel and display device Download PDFInfo
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- CN105489610A CN105489610A CN201510830567.6A CN201510830567A CN105489610A CN 105489610 A CN105489610 A CN 105489610A CN 201510830567 A CN201510830567 A CN 201510830567A CN 105489610 A CN105489610 A CN 105489610A
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- 239000010409 thin film Substances 0.000 title claims abstract description 38
- 239000000758 substrate Substances 0.000 title claims abstract description 18
- 239000002184 metal Substances 0.000 claims description 30
- 238000002161 passivation Methods 0.000 claims description 7
- 239000000700 radioactive tracer Substances 0.000 description 9
- 230000009977 dual effect Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 239000012141 concentrate Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000012528 membrane Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
Abstract
The invention provides a thin-film transistor array substrate. The thin-film transistor array substrate comprises a plurality of scanning lines, a plurality of data lines, a plurality of TFTs and a plurality of pixel electrodes, which are arranged on a substrate, wherein each pixel electrode is connected with the corresponding scanning line and data line through the corresponding TFT; the thin-film transistor array substrate has a double-scanning line pixel array structure; the plurality of data lines divide each scanning line in the plurality of scanning lines into a plurality of first scanning segments and a plurality of second scanning segments; the plurality of first scanning segments are connected with the TFTs; the plurality of second scanning segments are not connected with the TFTs; the first scanning segments and the second scanning segments are located between two adjacent data lines; the first scanning segments and the second scanning segments on each scanning line are alternately distributed along the length direction of the scanning lines; and the line widths of the second scanning segments are smaller than those of the first scanning segments. According to the thin-film transistor array substrate, the area of a pixel electrode can be relatively improved by reducing the line widths of the second scanning segments; and the aperture ratio of the pixel is improved. The invention further provides a display panel and a display device with the thin-film transistor array substrate.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of thin-film transistor array base-plate and there is display floater and the display unit of this thin-film transistor array base-plate.
Background technology
Along with the development of large scale display floater, in the pel array of array base palte, one is had to be called as half source drive (halfsourcedriving, HSD) framework.In the pel array of HSD framework, the adjacent pixel of two row is a shared data wire, and the number of data wire can be made to reduce by half.For display floater, driving chip comprises grid drive chip (gatedriver) and source driving chip (sourcedriver) is all absolutely necessary, source driving chip due to the structural rate grid drive chip of its complexity more expensive, and HSD framework reduces by half owing to can make data wire number, the cost of source driving chip therefore can be reduced.
Although adopt the display floater of HSD framework that the driving port number of source driving chip can be allowed to reduce by half, but because the odd number of pixels in same one-row pixels is connected with different scan lines respectively from even number pixel, therefore the scan line doubles in HSD framework, therefore the pel array of HSD framework is also called dual scanning line pixel array.
Fig. 1 is the floor map of existing array base palte, Fig. 2 is the equivalent circuit diagram of the array base palte of Fig. 1, please refer to the drawing 1 and Fig. 2, this array base palte has dual scanning line pixel array structure, comprise multi-strip scanning line 11, a plurality of data lines 12, multiple TFT13 and multiple pixel electrode 14, each pixel electrode 14 is connected with data wire 12 with corresponding scan line 11 by TFT13, is connected on two scan lines 11 up and down of this row pixel electrode respectively by TFT13 with often adjacent two pixel electrodes 14 in a line pixel electrode.
In order to ensure the normal processing procedure of each TFT13, the gate metal layer of each TFT13 need ensure certain live width, make the live width of whole piece scan line 11 identical with the live width of the gate metal layer of TFT13, scan line 11 area occupied is larger, cause the aperture opening ratio of pixel low, affect the optical characteristics of display floater.
Summary of the invention
The object of the present invention is to provide a kind of thin-film transistor array base-plate, and there is display floater and the display unit of this thin-film transistor array base-plate, comparatively large with scan line area occupied in the dual scanning line pixel array structure solving existing array base palte, the problem that pixel aperture ratio is low.
The invention provides a kind of thin-film transistor array base-plate, comprise the multi-strip scanning line be arranged on underlay substrate, a plurality of data lines, multiple TFT and multiple pixel electrode, each pixel electrode is connected with data wire with corresponding scan line by TFT; Article two, be provided with two row pixel electrodes between adjacent data line, every bar data wire is connected with the two row pixel electrodes being positioned at these data wire both sides; Article two, two pixel electrodes between adjacent data line, that be positioned at same a line are connected on same scan line; With a line pixel electrode between two one group be alternately connected on two scan lines of the both sides being up and down positioned at this row pixel electrode; Every bar scan line in this multi-strip scanning line is divided into multiple first Scanning Section be connected with TFT and multiple second Scanning Sections be not connected with TFT by this plurality of data lines, this first Scanning Section and this second Scanning Section are all between two adjacent data lines, the first Scanning Section on every bar scan line and the second Scanning Section are alternately distributed along the length direction of scan line, and the live width of this second Scanning Section is less than the live width of this first Scanning Section; The scan line of two next-door neighbours is provided with between the pixel electrode of neighbouring two row, the pixel electrode of scan line two row neighbouring with this respectively of these two next-door neighbours is connected, the first Scanning Section on the scan line of these two next-door neighbours is alternately distributed along the length direction of scan line, and the second Scanning Section on the scan line of these two next-door neighbours is also alternately distributed along the length direction of scan line.
Further, with in the pixel electrode of a line, the pixel electrode group being positioned at odd number is connected with the scan line of the downside of this row pixel electrode, the pixel electrode group being positioned at even number is connected with the scan line of the upside of this row pixel electrode, and wherein each pixel electrode group comprises two pixel electrodes between two adjacent data lines, that be positioned at same a line.
Further, with in the pixel electrode of a line, the pixel electrode group being positioned at even number is connected with the scan line of the downside of this row pixel electrode, the pixel electrode group being positioned at odd number is connected with the scan line of the upside of this row pixel electrode, and wherein each pixel electrode group comprises two pixel electrodes between two adjacent data lines, that be positioned at same a line.
Further, the live width of this second Scanning Section is 1/3rd of the live width of this first Scanning Section.
Further, the gate metal layer of each TFT is connected with corresponding scan line, and the source metal of each TFT is connected with corresponding data wire, and the drain metal layer of each TFT is connected with corresponding pixel electrode.
Further; this thin-film transistor array base-plate also comprise cover each TFT source metal and drain metal layer on passivation protection layer; this passivation protection layer is provided with through hole, and the drain metal layer of each TFT is connected with corresponding pixel electrode by this through hole.
Further, the live width of this first Scanning Section is identical with the width of the gate metal layer of each TFT.
The present invention also provides a kind of display floater, comprises above-mentioned thin-film transistor array base-plate.
The present invention also provides a kind of display unit, comprises above-mentioned display floater.
Thin-film transistor array base-plate provided by the invention, this thin-film transistor array base-plate has dual scanning line pixel array structure, the number of data wire is reduced by half, be conducive to the cost reducing source driving chip, additionally by by between two adjacent data lines, be positioned at same a line two pixel electrodes concentrate be connected on same scan line, significantly can reduce the live width of the Scanning Section that every bar scan line is not connected with TFT, thus relatively promote the area of pixel electrode, improve the aperture opening ratio of pixel, larger with scan line area occupied in the dual scanning line pixel array structure solving existing array base palte, the problem that pixel aperture ratio is low, and every two pixel electrodes between two one group be evenly distributed on array base palte, this array base palte is when colored filter substrate of arranging in pairs or groups is made into liquid crystal panel, colour mixture of the present invention is more even, display image quality effect is more excellent.
Accompanying drawing explanation
Fig. 1 is the floor map of existing array base palte.
Fig. 2 is the equivalent circuit diagram of the array base palte of Fig. 1.
Fig. 3 is the floor map of thin-film transistor array base-plate in the embodiment of the present invention.
Fig. 4 is the equivalent circuit diagram of the thin-film transistor array base-plate of Fig. 3.
Fig. 5 is the partial cutaway schematic view of thin-film transistor array base-plate in the embodiment of the present invention.
Embodiment
For further setting forth the present invention for the technical approach reaching predetermined goal of the invention and take and effect, below in conjunction with drawings and Examples, to the specific embodiment of the present invention, structure, feature and effect thereof, be described in detail as follows.
Fig. 3 is the floor map of thin-film transistor array base-plate in the embodiment of the present invention, Fig. 4 is the equivalent circuit diagram of the thin-film transistor array base-plate of Fig. 3, Fig. 5 is the partial cutaway schematic view of thin-film transistor array base-plate in the embodiment of the present invention, please refer to the drawing 3 to Fig. 5, this thin-film transistor array base-plate has dual scanning line pixel array structure, the multi-strip scanning line 21 that this thin-film transistor array base-plate comprises underlay substrate 20 and is arranged on underlay substrate 20, a plurality of data lines 22, multiple TFT23 and multiple pixel electrode 24, each pixel electrode 24 is connected with data wire 22 with corresponding scan line 21 by a TFT23.
The plurality of pixel electrode 24 is array distribution on underlay substrate 20, convenient in order to describe, below also with P
mNrepresent a pixel electrode, wherein M represents the line number at this pixel electrode place, and N represents the columns at this pixel electrode place.
Article two, be provided with two row pixel electrodes 24 between adjacent data line 22, every bar data wire 22 is connected with the two row pixel electrodes 24 being positioned at these data wire 22 both sides.As shown in Figure 3 and Figure 4, for Article 2 data wire and Article 3 data wire in scheming, two row pixel electrodes are provided with between Article 2 data wire and Article 3 data wire, be respectively the 3rd row pixel electrode and the 4th row pixel electrode, wherein Article 2 data wire is connected with the 3rd row pixel electrode with the secondary series pixel electrode being positioned at this article of data wire both sides, and Article 3 data wire is connected with the 5th row pixel electrode with the 4th row pixel electrode being positioned at this article of data wire both sides.
Article two, two pixel electrodes 24 between adjacent data line 22, that be positioned at same a line are connected on same scan line 21.As shown in Figure 3 and Figure 4, for the pixel electrode of the first row in scheming, two pixel electrode P between Article 1 data wire and Article 2 data wire
11, P
12be connected on same scan line (being namely positioned at the scan line on the downside of the first row pixel electrode), two pixel electrode P between Article 2 data wire and Article 3 data wire
13, P
14be connected on same scan line (being namely positioned at the scan line on the upside of the first row pixel electrode), the rest may be inferred by analogy repeats no more for it.
With a line pixel electrode 24 between two one group be alternately connected on two scan lines 21 of the both sides being up and down positioned at this row pixel electrode.In the present embodiment, with in the pixel electrode 24 of a line, the scan line 21 of the pixel electrode group and the downside of this row pixel electrode that are positioned at odd number is connected, the scan line 21 of the pixel electrode group and the upside of this row pixel electrode that are positioned at even number is connected, and wherein each pixel electrode group comprises two pixel electrodes 24 between two adjacent data lines, that be positioned at same a line.As shown in Figure 3 and Figure 4, for the pixel electrode of the first row in scheming, two pixel electrode P between Article 1 data wire and Article 2 data wire
11, P
12be connected on the scan line 21 of the downside being positioned at the first row pixel electrode, two pixel electrode P between Article 2 data wire and Article 3 data wire
13, P
14be connected on the scan line 21 of the upside being positioned at the first row pixel electrode, two pixel electrode P between Article 3 data wire and Article 4 data wire
15, P
16be connected on the scan line 21 of the downside being positioned at the first row pixel electrode, all the other by that analogy, thus make in the pixel electrode of same a line, the scan line 21 of the pixel electrode group and the downside of this row pixel electrode that are positioned at odd number is connected, and the scan line 21 of the pixel electrode group and the upside of this row pixel electrode that are positioned at even number is connected.Wherein, P
11, P
12and P
15, P
16for the odd pixel electrode group of the first row pixel electrode, P
13, P
14for the even pixel electrode group of the first row pixel electrode.
Understandably, in other embodiments, with in the pixel electrode 24 of a line, also can be that the scan line 21 of the pixel electrode group and the downside of this row pixel electrode being positioned at even number is connected, the scan line 21 of the pixel electrode group and the upside of this row pixel electrode that are positioned at odd number is connected, wherein each pixel electrode group comprises two pixel electrodes 24 between two adjacent data lines, that be positioned at same a line, does not repeat them here.
In the present embodiment, every bar scan line 21 in this multi-strip scanning line 21 is divided into multiple first Scanning Section 211 be connected with TFT23 and multiple second Scanning Sections 212 be not connected with TFT23 by this plurality of data lines 22, this first Scanning Section 211 and this second Scanning Section 212 are all between two adjacent data lines 22, the first Scanning Section 211 on every bar scan line 21 and the second Scanning Section 212 are alternately distributed along the length direction of scan line, and the live width of this second Scanning Section 212 is less than the live width of this first Scanning Section 211.As above-mentioned, due to by between two adjacent data lines 22, two pixel electrodes being positioned at same a line 24 concentrate and are connected on same scan line 21, particularly, be be connected on the first Scanning Section 211 of being connected with TFT23, therefore significantly can reduce the live width of the second Scanning Section 212 be not connected with TFT23.
The scan line 21 of two next-door neighbours is provided with between the pixel electrode 24 of neighbouring two row, the pixel electrode 24 of scan line 21 two row neighbouring with this respectively of these two next-door neighbours is connected, the first Scanning Section 211 on the scan line 21 of these two next-door neighbours is alternately distributed along the length direction of scan line, and the second Scanning Section 212 on the scan line 21 of these two next-door neighbours is also alternately distributed along the length direction of scan line.Particularly, as shown in Figure 3 and Figure 4, for the pixel electrode of the first row in scheming and the second row, two scan lines be close to 21 are provided with between the first row pixel electrode and the second row pixel electrode, for convenience of description, for the time being the scan line 21 that these two are close to is called upper tracer 21a and lower tracer 21b, is positioned at two pixel electrode P of the first row
11, P
12be connected on the upper tracer 21a in the scan line 21 of these two next-door neighbours, be positioned at two pixel electrode P of the second row
23, P
24be connected on the lower tracer 21b in the scan line 21 of these two next-door neighbours, be positioned at two pixel electrode P of the first row
15, P
16be connected on the upper tracer 21a in the scan line 21 of these two next-door neighbours, all the other by that analogy.Make on the scan line 21 of these two next-door neighbours, first Scanning Section 211 of upper tracer 21a and first Scanning Section 211 of lower tracer 21b are just alternately distributed along the length direction of scan line, and second Scanning Section 212 of second Scanning Section 212 of upper tracer 21a and lower tracer 21b is also alternately distributed along the length direction of scan line.So, second Scanning Section 212 with less width can be utilized to realize the lifting of pixel aperture ratio, first Scanning Section 211 simultaneously with larger width is evenly alternately in staggered distribution on whole array base palte, every two pixel electrodes 24 are made one group to be evenly distributed on array base palte between two, this array base palte is at collocation colored filter substrate (colerfilter, when CF) being made into liquid crystal panel, colour mixture of the present invention is more even, and display image quality effect is more excellent.
In the present embodiment, the live width of the second Scanning Section 212 be not connected with TFT23 is about 1/3rd of the live width of the first Scanning Section 211 be connected with TFT23.If such as the live width of the first Scanning Section 211 is 30um, then the live width of the second Scanning Section 212 mostly is 10um most.Because the live width of scan line 21 significantly reduces, relatively can promote the area of pixel electrode 24, thus improve the aperture opening ratio of pixel, the present embodiment can improve aperture opening ratio more than 20%.
Please refer to the drawing 5; in the present embodiment; this thin-film transistor array base-plate also forms gate metal layer 231 on underlay substrate 20; gate metal layer 231 is formed with gate insulator 232; gate insulator 232 is formed with semiconductor layer 233; semiconductor layer 233 is formed with source metal 234 and drain metal layer 235, source metal 234 and drain metal layer 235 is formed with passivation protection layer 25, passivation protection layer 25 is formed pixel electrode 24.Wherein, gate metal layer 231, gate insulator 232, semiconductor layer 233, source metal 234 and drain metal layer 235 form TFT23, the gate metal layer 231 of each TFT23 is connected with corresponding scan line 21, the source metal 234 of each TFT23 is connected with corresponding data wire 22, and the drain metal layer 235 of each TFT23 is connected with corresponding pixel electrode 24.Passivation protection layer 25 is provided with the through hole (figure does not mark) of exposed portion drain electrode, and the drain metal layer 235 of each TFT23 is connected with corresponding pixel electrode 24 by this through hole.
In the present embodiment, the live width of the first Scanning Section 211 be connected with TFT23 is identical with the width of the gate metal layer 231 of each TFT23, thus it is connected with corresponding scan line 21 not affect TFT23, also without the need to changing structure and the processing procedure of TFT23.
The present invention also provides a kind of display floater, and this display floater comprises above-mentioned thin-film transistor array base-plate, color membrane substrates (not shown) and the liquid crystal layer (not shown) between this thin-film transistor array base-plate and this color membrane substrates.
The present invention also provides a kind of display unit, and this display unit comprises above-mentioned display floater.
The thin-film transistor array base-plate that above-described embodiment provides, this thin-film transistor array base-plate has dual scanning line pixel array structure, the number of data wire is reduced by half, be conducive to the cost reducing source driving chip, additionally by by between two adjacent data lines, be positioned at same a line two pixel electrodes concentrate be connected on same scan line, significantly can reduce the live width of the Scanning Section that every bar scan line is not connected with TFT, thus relatively promote the area of pixel electrode, improve the aperture opening ratio of pixel, larger with scan line area occupied in the dual scanning line pixel array structure solving existing array base palte, the problem that pixel aperture ratio is low, and every two pixel electrodes between two one group be evenly distributed on array base palte, this array base palte is when colored filter substrate of arranging in pairs or groups is made into liquid crystal panel, colour mixture of the present invention is more even, display image quality effect is more excellent.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, make a little change when the technology contents of above-mentioned announcement can be utilized or be modified to the Equivalent embodiments of equivalent variations, in every case be do not depart from technical solution of the present invention content, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (9)
1. a thin-film transistor array base-plate, comprise the multi-strip scanning line be arranged on underlay substrate, a plurality of data lines, multiple TFT and multiple pixel electrode, each pixel electrode is connected with data wire with corresponding scan line by TFT, it is characterized in that:
Article two, be provided with two row pixel electrodes between adjacent data line, every bar data wire is connected with the two row pixel electrodes being positioned at these data wire both sides;
Article two, two pixel electrodes between adjacent data line, that be positioned at same a line are connected on same scan line;
With a line pixel electrode between two one group be alternately connected on two scan lines of the both sides being up and down positioned at this row pixel electrode;
Every bar scan line in this multi-strip scanning line is divided into multiple first Scanning Section be connected with TFT and multiple second Scanning Sections be not connected with TFT by this plurality of data lines, this first Scanning Section and this second Scanning Section are all between two adjacent data lines, the first Scanning Section on every bar scan line and the second Scanning Section are alternately distributed along the length direction of scan line, and the live width of this second Scanning Section is less than the live width of this first Scanning Section;
The scan line of two next-door neighbours is provided with between the pixel electrode of neighbouring two row, the pixel electrode of scan line two row neighbouring with this respectively of these two next-door neighbours is connected, the first Scanning Section on the scan line of these two next-door neighbours is alternately distributed along the length direction of scan line, and the second Scanning Section on the scan line of these two next-door neighbours is also alternately distributed along the length direction of scan line.
2. thin-film transistor array base-plate according to claim 1, it is characterized in that, with in the pixel electrode of a line, the pixel electrode group being positioned at odd number is connected with the scan line of the downside of this row pixel electrode, the pixel electrode group being positioned at even number is connected with the scan line of the upside of this row pixel electrode, and wherein each pixel electrode group comprises two pixel electrodes between two adjacent data lines, that be positioned at same a line.
3. thin-film transistor array base-plate according to claim 1, it is characterized in that, with in the pixel electrode of a line, the pixel electrode group being positioned at even number is connected with the scan line of the downside of this row pixel electrode, the pixel electrode group being positioned at odd number is connected with the scan line of the upside of this row pixel electrode, and wherein each pixel electrode group comprises two pixel electrodes between two adjacent data lines, that be positioned at same a line.
4. thin-film transistor array base-plate according to claim 1, is characterized in that, the live width of this second Scanning Section is 1/3rd of the live width of this first Scanning Section.
5. the thin-film transistor array base-plate according to any one of Claims 1-4, it is characterized in that, the gate metal layer of each TFT is connected with corresponding scan line, and the source metal of each TFT is connected with corresponding data wire, and the drain metal layer of each TFT is connected with corresponding pixel electrode.
6. thin-film transistor array base-plate according to claim 5; it is characterized in that; this thin-film transistor array base-plate also comprise cover each TFT source metal and drain metal layer on passivation protection layer; this passivation protection layer is provided with through hole, and the drain metal layer of each TFT is connected with corresponding pixel electrode by this through hole.
7. thin-film transistor array base-plate according to claim 5, is characterized in that, the live width of this first Scanning Section is identical with the width of the gate metal layer of each TFT.
8. a display floater, is characterized in that, comprises the thin-film transistor array base-plate as described in any one of claim 1 to 7.
9. a display unit, is characterized in that, comprises display floater as claimed in claim 8.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109407433A (en) * | 2018-11-14 | 2019-03-01 | 惠科股份有限公司 | A kind of array substrate and display panel |
| CN109634011A (en) * | 2019-01-08 | 2019-04-16 | 昆山国显光电有限公司 | Array substrate, display panel and display device |
| CN109799659A (en) * | 2019-03-13 | 2019-05-24 | 昆山龙腾光电有限公司 | Array substrate and liquid crystal display panel |
| CN110060652A (en) * | 2019-06-10 | 2019-07-26 | 北海惠科光电技术有限公司 | Array substrate, display device and its driving method |
| CN111580293A (en) * | 2020-06-05 | 2020-08-25 | 厦门天马微电子有限公司 | Array substrate, driving method thereof, display panel and display device |
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| CN109799659A (en) * | 2019-03-13 | 2019-05-24 | 昆山龙腾光电有限公司 | Array substrate and liquid crystal display panel |
| CN109799659B (en) * | 2019-03-13 | 2022-04-22 | 昆山龙腾光电股份有限公司 | Array substrate and liquid crystal display panel |
| CN110060652A (en) * | 2019-06-10 | 2019-07-26 | 北海惠科光电技术有限公司 | Array substrate, display device and its driving method |
| CN111580293A (en) * | 2020-06-05 | 2020-08-25 | 厦门天马微电子有限公司 | Array substrate, driving method thereof, display panel and display device |
| WO2021243830A1 (en) * | 2020-06-05 | 2021-12-09 | 厦门天马微电子有限公司 | Array substrate and drive method therefor, display panel and display device |
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