CN105489241B - Static RAM - Google Patents
Static RAM Download PDFInfo
- Publication number
- CN105489241B CN105489241B CN201410539431.5A CN201410539431A CN105489241B CN 105489241 B CN105489241 B CN 105489241B CN 201410539431 A CN201410539431 A CN 201410539431A CN 105489241 B CN105489241 B CN 105489241B
- Authority
- CN
- China
- Prior art keywords
- transistor
- storage unit
- bit line
- wordline
- memory node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Abstract
This application discloses a kind of Static RAM.Wherein, which includes：First bit line；The first transistor is connected to by source electrode and drain electrode between the first bit line and power supply or ground；N number of storage unit, for each in N number of storage unit for memory level state, level state includes high level and low level, and N is more than or equal to 1；N number of second transistor is corresponded with N number of storage unit, each in N number of second transistor is connected to by source electrode and drain electrode between corresponding storage unit and the grid of the first transistor；N number of first wordline is corresponded with N number of second transistor；Second bit line；Third transistor is connected to by source electrode and drain electrode between the second bit line and power supply or ground；N number of 4th transistor is corresponded with N number of storage unit；N number of second wordline is corresponded with N number of 4th transistor.Present application addresses Static RAM read data operation stability it is low the problem of.
Description
Technical field
This application involves memory area, in particular to a kind of Static RAM.
Background technology
Static RAM (SRAM) can realize quick read/write operation.Fig. 1 is a kind of 6T according to prior art
The schematic diagram of Static RAM, as shown in Figure 1, each memory module of the 6T Static RAM includes 6 crystal
Pipe, is transistor PG-1, transistor PG-2, transistor PU-1, transistor PD-1, transistor PU-2 and transistor PD-2 respectively.
Transistor PU-1, transistor PD-1, transistor PU-2, transistor PD-2, power vd D and ground VSS collectively form storage unit, use
In memory level state, i.e. high level state and low level state, which includes two memory nodes, is storage respectively
Node Q and memory node QN, memory node Q and a pair of opposite level state of memory node QN storages.Wordline WL is connected to crystalline substance
The grid of body pipe PG-1 and transistor PG-2, for controlling from storage unit reading level state or electricity being written to storage unit
Level state.Transistor PG-1 is connected to by source electrode and drain electrode between the memory node Q of storage unit and bit line BL, transistor
PG-2 is connected to by source electrode and drain electrode between the memory node QN of storage unit and bit line BLB.
When wordline WL is high level, transistor PG-1 and transistor PG-2 are simultaneously turned on, and bit line BL can read and deposit
The level state of node Q is stored up, bit line BLB can read the level state of memory node QN, realize from storage unit and read number
According to.Likewise, bit line BL for example is added in high level first to storage unit write-in high level " 1 ", corresponding bit line BLB adds
Enter low level, when wordline WL be high level when, transistor PG-1 and transistor PG-2 are simultaneously turned on, bit line BL, bit line BLB electricity
Level state is transmitted separately to memory node Q and memory node QN so that memory node Q is high level state " 1 ", corresponding to store
Node QN is low level state " 0 ", realizes to storage unit and data are written.
The 6T Static RAM can only realize single port read/write, and read-write efficiency is relatively low, and the T static randoms are deposited
The storage node voltage of reservoir can be influenced by read operation, and static noise margin value is smaller, and memory stability is too low.
Fig. 2 is a kind of dual-port static random access memory schematic diagram according to prior art, as shown in Fig. 2, the dual-port
On the basis of Static RAM 6T Static RAM shown in Fig. 1, transistor PGA2 and transistor are increased
PGB2 and bit line BL2, BL1B and wordline WLB, wherein, transistor PGA2 is connected to bit line BL2 by source electrode or drain electrode,
Transistor PGB2 is connected to bit line BL1B by source electrode or drain electrode, and transistor PGA2 and transistor PGB2 grids are connected to wordline
WLB.Other elements are corresponding with element in Fig. 1 respectively in figure, and bit line BL1 corresponds to bit line BL, and bit line BL2B corresponds to bit line
BLB, transistor PGA1 correspond to transistor PG-1, and transistor PGB1 corresponds to transistor PG-2, and wordline WLA corresponds to wordline
WL。
The dual-port static random access memory can be realized while from two port read/write, you can with simultaneously from two ends
Mouth is written data or reads data from two ports, and read-write efficiency is improved, but the dual-port static random storage
The read-write operation of two ports of device can influence each other, and stability is also lower than traditional 6T Static RAM.
In order to improve the static noise margin of Static RAM and stability, manufactured 8T Static RAM and
10T Static RAM, Fig. 3 are that a kind of 8T Static RAM schematic diagram, Fig. 4 are according to existing according to prior art
A kind of 10T Static RAM schematic diagram of technology.
As shown in figure 3,8T Static RAM on the basis of 6T Static RAM shown in Fig. 1 by increasing
Transistor RPD and transistor RPG, bit line RBL are connected to memory node QN, transistor via transistor RPD and transistor RPG
The grid of RPG is connected to wordline RWL, and wordline RWL reads data, transistor PG-1 for controlling from Static RAM
Wordline WWL is connected to transistor PG-2, data are written into Static RAM for controlling by bit line WWL, and the 8T is static
Random access memory other parts are the same as 6T Static RAM shown in FIG. 1.Due to the presence of transistor RPD and transistor RPG,
So that read port voltage does not interfere with the voltage of memory node QN, it is improved so as to the stability of Static RAM,
Static noise margin value becomes larger, but the 8T Static RAM can only perform single port read operation, and reading efficiency is relatively low.
As shown in figure 4,10T Static RAM is improved on the basis of 8T Static RAM, in crystal
Pipe RPD and the symmetrical positions of transistor RPG increase two transistors, and the two transistors are connected to wordline RWL and position
Line RBL, bit line RBLB correspond to the bit line RBL in Fig. 3.The other parts of the 10T Static RAM are the same as 8T shown in Fig. 3
Static RAM.The 10T Static RAM can realize that differential type is read, and improve the access speed of memory,
And with higher stability, but each storage unit of 10T Static RAM includes 10 transistors, area compared with
Greatly, it is unfavorable for Integrated manufacture.
To sum up, static memory (SRAM) can realize quick read/write operation, but read static noise margin (RSNM)
Become worse and worse, stability is lower and lower.The reading static noise margin of dual-port (2RW, 2 reading-writing ports) static memory
It is more worse than traditional 6T static memories, although dual-port (2RW) static memory has faster access speed.For reality
It is existing high to read static noise margin, invent 8T static memories and 10T static memories, but its access speed and unit
Area is difficult to meet the requirements.
For the problem of Static RAM read data operation stability is low in the prior art, not yet propose have at present
The solution of effect.
Invention content
The embodiment of the present application provides a kind of Static RAM, to solve Static RAM read data operation
The problem of stability is low.
According to the one side of the embodiment of the present application, a kind of Static RAM is provided, including：First bit line；The
One transistor is connected to by source electrode and drain electrode between the first bit line and power supply or ground；N number of storage unit, N number of storage unit
In each for memory level state, level state includes high level and low level, and N is more than or equal to 1；N number of second crystal
Pipe is corresponded with N number of storage unit, each in N number of second transistor is connected to corresponding deposit by source electrode and drain electrode
Between storage unit and the grid of the first transistor；N number of first wordline corresponds, N number of first wordline with N number of second transistor
In each be connected to the grid of corresponding second transistor, read level state for controlling from corresponding storage unit；
Second bit line；Third transistor is connected to by source electrode and drain electrode between the second bit line and power supply or ground；N number of 4th transistor,
It is corresponded with N number of storage unit, wherein, each in N number of 4th transistor is connected to corresponding by source electrode and drain electrode
Between storage unit and the grid of third transistor；And N number of second wordline, it is corresponded with N number of 4th transistor, N number of the
Each in two wordline is connected to the grid of corresponding 4th transistor, and level is read for controlling from corresponding storage unit
State.
Further, each storage unit in N number of storage unit includes：First memory node, for store with it is each
The level state of storage unit is the same as the level state of phase；Second memory node, for storing the level shape with each storage unit
The level state of state reverse phase；Wherein, each in N number of second transistor is connected to corresponding storage list by source electrode and drain electrode
The first memory node in member and between the grid of the first transistor, alternatively, each in N number of second transistor passes through source electrode
And drain electrode is connected between the second memory node in corresponding storage unit and the grid of the first transistor.
Further, each storage unit in N number of storage unit includes：First phase inverter is connected to the first storage section
Between point and the second memory node；Second phase inverter is oppositely connected to the first memory node and relative to the first phase inverter
Between two memory nodes.
Further, each storage unit in N number of storage unit includes：First PMOS, is connected by source electrode and drain electrode
Between power supply and the first memory node, the grid of the first PMOS is connected to the second memory node；First NMOS, by source electrode and
Drain electrode is connected between the first memory node and ground, and the grid of the first NMOS is connected to the second memory node；2nd PMOS, passes through
Source electrode and drain electrode is connected between power supply and the second memory node, and the grid of the 2nd PMOS is connected to the first memory node；Second
NMOS is connected to by source electrode and drain electrode between the second memory node and ground, and the grid of the 2nd NMOS is connected to the first storage section
Point.
Further, which further includes：Third bit line；N number of 5th transistor, with N number of storage unit
It corresponds, each in N number of 4th transistor is connected to corresponding storage unit and third bit line by source electrode and drain electrode
Between；4th bit line；N number of 6th transistor is corresponded with N number of storage unit, each in N number of 6th transistor passes through
Source electrode and drain electrode is connected between corresponding storage unit and the 4th bit line；N number of third wordline, with N number of 5th transistor and N number of
6th transistor corresponds, each in N number of third wordline is connected to corresponding 5th transistor and the 6th transistor
Level shape is written for controlling to read level state from corresponding storage unit, and/or control to corresponding storage unit in grid
State.
Further, which further includes：Processor connects the first bit line and N number of first wordline, is used for
Any first wordline output into N number of first wordline controls signal and is read and any first wordline pair from the first bit line
The level state for the storage unit answered, control signal are used to control source electrode and the leakage of the corresponding second transistor of any first wordline
Conducting between pole.
Further, the first transistor and second transistor are NMOS.
In the Static RAM that the application provides, control the first transistor and second transistor real by the first wordline
It now reads to keep the level state of storage unit constant during static memory data, has reached raising Static RAM and read number
According to the purpose of operational stability, and then solves the technical issues of Static RAM read data operation stability is low.
Description of the drawings
Attached drawing described herein is used for providing further understanding of the present application, forms the part of the application, this Shen
Illustrative embodiments and their description please do not form the improper restriction to the application for explaining the application.In the accompanying drawings：
Fig. 1 is a kind of schematic diagram of 6T Static RAM according to prior art；
Fig. 2 is a kind of dual-port static random access memory schematic diagram according to prior art；
Fig. 3 is a kind of 8T Static RAM schematic diagram according to prior art；
Fig. 4 is a kind of 10T Static RAM schematic diagram according to prior art；
Fig. 5 is the schematic diagram according to the Static RAM of the embodiment of the present application；And
Fig. 6 is the schematic diagram according to the memory module of the embodiment of the present application.
Specific embodiment
The application is described in detail below with reference to attached drawing and in conjunction with the embodiments.It should be noted that do not conflicting
In the case of, the feature in embodiment and embodiment in the application can be combined with each other.
In order to which those skilled in the art is made to more fully understand application scheme, below in conjunction in the embodiment of the present application
The technical solution in the embodiment of the present application is clearly and completely described in attached drawing, it is clear that described embodiment is only
The embodiment of the application part, instead of all the embodiments.Based on the embodiment in the application, ordinary skill people
Member's all other embodiments obtained without making creative work should all belong to the model of the application protection
It encloses.
It should be noted that term " first " in the description and claims of this application and above-mentioned attached drawing, "
Two " etc. be the object for distinguishing similar, and specific sequence or precedence are described without being used for.It should be appreciated that it uses in this way
Data can be interchanged in the appropriate case, so as to embodiments herein described herein can in addition to illustrating herein or
Sequence other than those of description is implemented.In addition, term " comprising " and " having " and their any deformation, it is intended that cover
Cover it is non-exclusive include, be not necessarily limited to for example, containing the process of series of steps or unit, method, system, product or equipment
Those steps or unit clearly listed, but may include not listing clearly or for these processes, method, product
Or the intrinsic other steps of equipment or unit.
According to the embodiment of the present application, a kind of Static RAM is provided, Fig. 5 is the static state according to the embodiment of the present application
Random access memory schematic diagram.
As shown in figure 5, the Static RAM includes：First bit line 20, the first transistor 10, N number of storage unit, N
A second transistor, N number of first wordline, the second bit line 40, third transistor 30, N number of 4th transistor and N number of second wordline.
The first transistor 10 is connected to by source electrode and drain electrode between the first bit line 20 and power supply or ground；
N number of storage unit, for each in N number of storage unit for memory level state, level state includes high level
And low level, N are more than or equal to 1；
N number of second transistor is corresponded with N number of storage unit, each in N number of second transistor by source electrode and
Drain electrode is connected between the grid of corresponding storage unit and the first transistor 10；
N number of first wordline is corresponded with N number of second transistor, each in N number of first wordline is connected to corresponding
The grid of second transistor reads level state for controlling from corresponding storage unit.
Third transistor 30 is connected to by source electrode and drain electrode between the second bit line and power supply or ground；
N number of 4th transistor is corresponded with N number of storage unit, wherein, each in N number of 4th transistor passes through
Source electrode and drain electrode is connected between corresponding storage unit and the grid of third transistor.
N number of second wordline is corresponded with N number of 4th transistor, each in N number of second wordline is connected to corresponding
The grid of 4th transistor reads level state for controlling from corresponding storage unit.
As shown in figure 5, the static random access memory includes N memory modules, each memory module in N number of memory module
50 include storage unit 501, second transistor 502, the first wordline 507, the 4th transistor 504 and the second wordline 508.It is following to press
According to being illustrated for a memory module 50 in N number of storage unit to the present embodiment.
The source electrode ground connection of the first transistor 10,10 grid of the first transistor are connected to the second crystal via internal wiring ILB
The source electrode of pipe 502, the drain electrode of the first transistor 10 are connected to the first bit line 20, and the first bit line 20 is used as output line, and external
Circuit (not shown) is connected, by the data that are stored in 20 output storage of the first bit line or by outer input data
It is written to memory.The drain electrode of second transistor 502 is connected to 501 first end of storage unit, and grid is connected to the first wordline
507, read operation transmission channel of the second transistor 502 as memory, when the first 507 high level of wordline, second crystalline substance
Body pipe 502 is connected, and the data that storage unit 501 stores just are transmitted to the first bit line 20 by second transistor 502, realizes storage
The read operation of device data.The source electrode of third transistor 30 is connected to the ground, and the drain electrode of third transistor 30 is connected to the second bit line 40,
The grid of third transistor 30 is connected to the source electrode of the 4th transistor 504 via internal wiring ILA.The grid of 4th transistor 504
Pole is connected to the second wordline 508, and the drain electrode of the 4th transistor 504 is connected to 501 second end of storage unit.
In the data procedures for reading the Static RAM, when the first 507 high level of wordline, second transistor
502 conductings can read the level state of storage unit 501 from the first bit line 20, due to 10 grid of the first transistor and source
It is off-state between pole, the grid of the first transistor 10 does not have electric current to flow through, therefore brilliant by second transistor 502 and first
The read operation that body pipe 10 performs can keep the level state of storage unit 501 constant.Likewise, when the second wordline 508 is height
During level, the 4th transistor 504 is connected, and the level state that storage unit stores can be read by the second bit line 40, and the
The obstructed electric current of grid of three transistors 30, therefore the operation of the reading memory will not influence depositing for Static RAM
The voltage value of the second end of storage unit 501.The static memory passes through the first bit line 20, the first transistor 10 and second transistor
502 are used as the first read port, are used as the second read port by third transistor 30, the 4th transistor 504 and the second bit line 40, from
Static memory reads data, and read data operation is performed simultaneously so as to fulfill two read ports, improves and is read from memory
The efficiency of data, and the voltage value at storage unit both ends can be kept constant in reading the data, it improves from quiet
The stability of data is read in state random access memory, solves the problems, such as that Static RAM reading data operational stability is low,
In addition, the Static RAM is simple in structure, area is smaller, convenient for Integrated manufacture.
Optionally, each storage unit 501 in above-mentioned N number of storage unit includes：First memory node 5013 and second
Memory node 5014.
First memory node 5013, for storing the level shape with the level state of above-mentioned each storage unit 501 with phase
State.
Second memory node 5014, for storing the level shape with the level state reverse phase of above-mentioned each storage unit 501
State；Wherein, each in above-mentioned N number of second transistor 502 is connected to by source electrode and drain electrode in corresponding storage unit 501
The first memory node 5013 and the first transistor 10 grid between.
It realizes and stores from figure 5 it can be seen that second transistor 502 is connected to the second memory node 5014 by drain electrode
The connection of unit.Storage unit 501 stores the level state identical with the storage unit 501 by the first memory node 5013,
Second memory node 5014 is for storing the level state with 501 reverse phase of storage unit, for example, what storage unit 501 stored
When level state is " 1 ", then the level state of the first memory node 5013 storage is " 1 ", the storage of the second memory node 5014
Level state is " 0 ".
Preferably, the first memory node 5013 and the second memory node 5014 of realization storage unit 501 for convenience
Level state for level state opposite each other, each storage unit 501 in above-mentioned N number of storage unit includes：First is anti-
5011 and second phase inverter 5012 of phase device.
First phase inverter 5011 is connected between the first memory node 5013 and the second memory node 5014.
Second phase inverter 5012 is oppositely connected to the first memory node 5013 and second relative to the first phase inverter 5011
Between memory node 5014.
The first end of first phase inverter 5011 is connected to the first memory node 5013, and the second end of the first phase inverter 5011 connects
It is connected to the second memory node 5014.And the first end of the second phase inverter 5012 is connected to the second memory node 5014, the second reverse phase
The second end of device 5012 is connected to the first memory node 5013, realizes the reverse phase of the first phase inverter 5011 and the second phase inverter 5012
Connection.Phase inverter is used for the level state reverse phase inputted, for example, level state " 1 " obtains level state via phase inverter
“0”.Two opposite level states can easily be obtained by phase inverter, realize the first memory node 5013 and the second storage
The reverse phase of the level state of node 5014.
The concrete structure of memory module in Fig. 5 is as shown in fig. 6, as shown in fig. 6, the memory module includes storage unit
501, it is preferable that in order to reduce the power consumption of Static RAM, each storage unit 501 in above-mentioned N number of storage unit is wrapped
It includes：First PMOS transistor PU-1, the first NMOS transistor PD-1, the second PMOS transistor PU-2 and the second NMOS transistor
PD-2。
First PMOS transistor PU-1 is connected to by source electrode and drain electrode between power vd D and the first memory node Q, the
The grid of one PMOS transistor PU-1 is connected to the second memory node QN.
First NMOS transistor PD-1 is connected to by source electrode and drain electrode between the first memory node Q and ground VSS, first
The grid of NMOS transistor PD-1 is connected to the second memory node QN.
Second PMOS transistor PU-2, by source electrode and drain electrode be connected to power vd D and the second memory node QN it
Between, the grid of the second PMOS transistor PU-2 is connected to the first memory node Q；
Second NMOS transistor PD-2 is connected to by source electrode and drain electrode between the second memory node QN and ground VSS,
The grid of the second NMOS transistor PD-2 is connected to the first memory node Q.
As shown in fig. 6, storage unit 501 includes：First PMOS transistor PU-1, the first NMOS transistor PD-1, second
PMOS transistor PU-2, the second NMOS transistor PD-2, power vd D and ground VSS.Wherein, the first PMOS transistor PU-1 and
The grid of one NMOS transistor PD-1 is commonly connected to the second memory node QN, and the drain electrode of the first PMOS transistor PU-1 is connected to
The source electrode of power vd D, the first PMOS transistor PU-1 are connected to the first memory node Q, the drain electrode of the first NMOS transistor PD-1
The first memory node Q is connected to, the source electrode of the first NMOS transistor PD-1 is connected to the ground VSS.Likewise, the second PMOS transistor
The drain electrode that the grid of PU-2 and the second NMOS transistor PD-2 are connected to the first memory node Q, the second PMOS transistor PU-2 connects
Power vd D is connected to, the drain electrode of the source electrode of the second PMOS transistor PU-2 and the second NMOS transistor PD-2 is connected to the second storage
Node QN, the source electrode of the second NMOS transistor PD-2 are connected to the ground VSS.
It is interconnected to constitute by the first PMOS transistor PU-1, the first NMOS transistor PD-1, power vd D and ground VSS
One CMOS inverter so that the level state reverse phase of the first memory node Q obtains the level state of the second memory node QN.Together
Sample, the second PMOS transistor PU-2, the second NMOS transistor PD-2, power vd D and ground VSS, which are connected with each other, also forms one
CMOS inverter so that the level state reverse phase of the second memory node QN obtains the level state of the first memory node Q.CMOS is anti-
Phase device quiescent dissipation is low, and strong antijamming capability, and storage unit can reduce entire static random using CMOS inverter and deposit
The power consumption and antijamming capability of reservoir.
Preferably, in order to further improve the efficiency of the data writing operation into Static RAM, which deposits
Reservoir further includes：Third bit line 509, N number of 5th transistor and the 4th bit line 510 and N number of third wordline.
N number of 5th transistor is corresponded with N number of storage unit, each in N number of 5th transistor passes through source
Pole and drain electrode are connected between corresponding storage unit and third bit line 509；
N number of 6th transistor is corresponded with N number of storage unit, each in N number of 6th transistor by source electrode and
Drain electrode is connected between corresponding storage unit and the 4th bit line 510；
N number of third wordline is corresponded with N number of 5th transistor and N number of 6th transistor, every in N number of third wordline
One grid for being connected to corresponding 5th transistor and the 6th transistor reads level for controlling from corresponding storage unit
State, and/or control to corresponding storage unit be written level state.
As shown in figure 5, the grid of the 5th transistor 505 is connected to third wordline 511, the 5th transistor 505 passes through source
Pole is connected to third bit line 509, and the drain electrode of the 5th transistor 505 is connected to the first memory node 5013.Third wordline 511 is used
Data are written to storage unit 501 in control.When third wordline 511 is high level, the 5th transistor 505 is connected, and becomes one
At this time level state can be written into storage unit 501 by third bit line 509 in a transmission path.By in above-mentioned static state
Increase the 5th transistor 505 and third bit line 509 in random access memory and be used as a write port, by the write port to static state with
Data are written in machine memory, have reached the efficiency for improving and data being written into Static RAM.
The grid of 5th transistor 505 is connected to third wordline 511, and the 5th transistor 505 is connected to by source electrode
Three bit lines 509, the drain electrode of the 5th transistor 505 are connected to the first memory node 5013 of storage unit 501.6th transistor
506 grid is also connected to third wordline 511, and the 6th transistor 506 is connected to the 4th bit line 510 by source electrode, and the 6th
The drain electrode of transistor 506 is connected to the second end of storage unit 501.Third wordline 511 controls the 5th transistor 505 and the simultaneously
The conducting of six transistors 506 is controlled whether to read the data of the storage of storage unit 501 or be write to storage unit 501 with cut-off
Enter data.During the data read operation of memory, for example, reading " 1 " stored in storage unit 501, storage unit
The level of 501 first end is " 0 ", and the level of the second end of storage unit 501 is " 1 ", first to third bit line 509 and the 4th
Bit line 510 carry out charging reach " 1, third wordline 511 be high level, the 5th transistor 505 and the 6th transistor 506 are led simultaneously
It is logical, at this moment there is electric current to flow through in the 5th transistor 505 and the 6th transistor 506, the level of third bit line 509 is drawn at this time
Low, 509 and the 4th bit line 510 of third bit line generates pressure difference, and when voltage difference reaches predetermined value, then sense amplifier (does not show in figure
Go out) it opens, amplify voltage difference, realize the reading of data.The data that during data obtain, will be written are being written into memory
Loading is on 509 and the 4th bit line 510 of third bit line, such as data " 1 " to be written into storage unit 501, then enables third position
Line 509 load data " 0 ", the 4th bit line 510 loading data " 1 ", when third wordline 511 be high level, 505 He of the 5th transistor
6th transistor 506 simultaneously turns on, and " 0 " that third bit line 509 loads at this time is transmitted to the first end of storage unit 501, and second
The data " 1 " that bit line 307 loads are transmitted to the second end of storage unit 501, realize to storage unit 501 and data are written.
Third wordline 511 controls the 5th transistor 505 and the 6th transistor 506, realizes from storage unit and reads level shape
State, and/or to corresponding storage unit be written level state, increased on the basis of above-mentioned Static RAM the 5th crystalline substance
Body pipe 505, the 6th transistor 506,509 and the 4th bit line 510 of third bit line be used as a memory read/write port, realize from
Read in Static RAM and data or data be written into Static RAM, improve the reading of Static RAM/
Writing speed.
Optionally, which further includes：Processor connects the first bit line 20 and N number of first wordline, is used for
Any first wordline output into N number of first wordline 5 controls signal and is read and any first wordline from the first bit line 20
The level state of corresponding storage unit, control signal be used for control the corresponding second transistor of any first wordline source electrode and
Conducting between drain electrode.
Preferably, the first transistor 10 and second transistor 502 are NMOS.
The power consumption of CMOS transistor is less than the power consumption of TTL transistors, and with stronger anti-interference.CMOS transistor
Including NMOS transistor and PMOS transistor, wherein, NMOS transistor is connected it is required that the voltage difference of grid and source electrode is more than
Certain value could be connected, and suitable for the situation of source electrode ground connection, and PMOS transistor conducting is it is required that the electricity of grid and source electrode
Pressure difference, which is less than certain value, to be connected, and power supply is connect suitable for source electrode.In addition, NMOS transistor conducting resistance is less than PMOS crystal
The conducting resistance of pipe is less than the conduction loss of PMOS transistor, therefore use accordingly so as to the conduction loss of NMOS transistor
NMOS transistor can reduce the loss of Static RAM.
This application provides a kind of preferred embodiments further to be explained to the application, but noticeable
It is that the preferred embodiment is intended merely to preferably describe the application, does not form and the application is improperly limited.
It can be seen from the above description that the application realizes following technique effect：
1) by the way that the grid of the first transistor to be connected to the source electrode of second transistor via internal wiring ILB so that from quiet
The voltage of the second memory node of storage unit can be kept to remain unchanged when reading data in state random access memory, by by the
The grid of three transistors is connected to the source electrode of the 4th transistor via internal wiring ILA so that is read from Static RAM
The voltage of the first memory node of storage unit can be kept to remain unchanged during data, improve and read from Static RAM
The stability for evidence of fetching solves the problems, such as that reading data stability is low from Static RAM.And the static random
Memory transistor negligible amounts, area is smaller, convenient for Integrated manufacture.
2) Static RAM can perform 2 ports and read data and 1 port write data or execution 3 simultaneously
Data are read in a port simultaneously, and the reading data efficiency of the Static RAM is greatly improved.
3) transistor of the Static RAM is formed using MOS transistor, and power consumption is relatively low, reduces static random and deposits
The power consumption of reservoir.
The foregoing is merely the preferred embodiments of the application, are not limited to the application, for the skill of this field
For art personnel, the application can have various modifications and variations.It is all within spirit herein and principle, made any repair
Change, equivalent replacement, improvement etc., should be included within the protection domain of the application.
Claims (7)
1. a kind of Static RAM, which is characterized in that including：
First bit line；
The first transistor is connected to by source electrode and drain electrode between first bit line and power supply or ground；
N number of storage unit, for each in N number of storage unit for memory level state, the level state includes height
Level and low level, N are more than or equal to 1；
N number of second transistor is corresponded with N number of storage unit, each in N number of second transistor passes through source
Pole and drain electrode are connected between the grid of corresponding storage unit and the first transistor；
The first wordline of N items is corresponded with the N number of second transistor, and each in first wordline of N items is connected to pair
The grid for the second transistor answered reads level state for controlling from corresponding storage unit；
Second bit line；
Third transistor is connected to by source electrode and drain electrode between second bit line and power supply or ground；
N number of 4th transistor is corresponded with the N number of storage unit, wherein, each in N number of 4th transistor
It is connected to by source electrode and drain electrode between the grid of corresponding storage unit and the third transistor；And
The second wordline of N items is corresponded with N number of 4th transistor, and each in second wordline of N items is connected to pair
The grid of the 4th transistor answered reads level state for controlling from corresponding storage unit.
2. Static RAM according to claim 1, which is characterized in that each in N number of storage unit deposits
Storage unit includes：
First memory node, for storing the level state with the level state of each storage unit with phase；
Second memory node, for storing the level state with the level state reverse phase of each storage unit；Wherein,
In N number of second transistor each by source electrode and drain electrode be connected in corresponding storage unit first storage
Between the grid of node and the first transistor, alternatively, each in N number of second transistor passes through source electrode and drain electrode
Between the second memory node and the grid of the first transistor that are connected in corresponding storage unit.
3. Static RAM according to claim 2, which is characterized in that each in N number of storage unit deposits
Storage unit includes：
First phase inverter is connected between first memory node and second memory node；
Second phase inverter is oppositely connected to first memory node and the described second storage relative to first phase inverter
Between node.
4. Static RAM according to claim 2, which is characterized in that each in N number of storage unit deposits
Storage unit includes：
First PMOS is connected to by source electrode and drain electrode between power supply and first memory node, the grid of the first PMOS
Pole is connected to second memory node；
First NMOS is connected to by source electrode and drain electrode between first memory node and ground, the grid of the first NMOS
It is connected to second memory node；
2nd PMOS is connected to by source electrode and drain electrode between power supply and second memory node, the grid of the 2nd PMOS
Pole is connected to first memory node；
2nd NMOS is connected to by source electrode and drain electrode between second memory node and ground, the grid of the 2nd NMOS
It is connected to first memory node.
5. Static RAM according to claim 1, which is characterized in that further include：
Third bit line；
N number of 5th transistor is corresponded with N number of storage unit, each in N number of 4th transistor passes through source
Pole and drain electrode are connected between corresponding storage unit and the third bit line；
4th bit line；
N number of 6th transistor is corresponded with N number of storage unit, each in N number of 6th transistor passes through source
Pole and drain electrode are connected between corresponding storage unit and the 4th bit line；
N third wordline is corresponded with N number of 5th transistor and N number of 6th transistor, in the N third wordline
Each be connected to the grid of corresponding 5th transistor and the 6th transistor, read for controlling from corresponding storage unit
Level state, and/or control to corresponding storage unit be written level state.
6. Static RAM according to any one of claim 1 to 5, which is characterized in that further include：
Processor connects first bit line and first wordline of N items, for any the into N articles of first wordline
One wordline output control signal and the electricity that storage unit corresponding with any first wordline is read from first bit line
Level state, the control signal are used between the source electrode and drain electrode for controlling the corresponding second transistor of any first wordline
Conducting.
7. Static RAM according to any one of claim 1 to 5, which is characterized in that the first transistor
It is NMOS with the second transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410539431.5A CN105489241B (en) | 2014-10-13 | 2014-10-13 | Static RAM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410539431.5A CN105489241B (en) | 2014-10-13 | 2014-10-13 | Static RAM |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105489241A CN105489241A (en) | 2016-04-13 |
| CN105489241B true CN105489241B (en) | 2018-07-03 |
Family
ID=55676183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410539431.5A Active CN105489241B (en) | 2014-10-13 | 2014-10-13 | Static RAM |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105489241B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105957552B (en) * | 2016-04-21 | 2018-12-14 | 华为技术有限公司 | memory |
| JP6753138B2 (en) * | 2016-05-16 | 2020-09-09 | ソニー株式会社 | Semiconductor circuits, drive methods, and electronics |
| CN113096702B (en) * | 2020-01-09 | 2024-05-14 | 中芯国际集成电路制造(上海)有限公司 | Memory circuit, reading method and recovery method thereof |
| CN116230053B (en) * | 2023-03-01 | 2023-12-22 | 芯立嘉集成电路(杭州)有限公司 | Four-transistor static random access memory and access method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1808621A (en) * | 2004-12-30 | 2006-07-26 | 国际商业机器公司 | Memory cell having improved read stability, memory array and integrate circuit |
| CN102047339A (en) * | 2008-06-19 | 2011-05-04 | 德克萨斯仪器股份有限公司 | Memory cell employing reduced voltage |
| CN102157195A (en) * | 2011-05-05 | 2011-08-17 | 北京大学 | Low-voltage static random access memory unit, memory and writing operation method |
-
2014
- 2014-10-13 CN CN201410539431.5A patent/CN105489241B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1808621A (en) * | 2004-12-30 | 2006-07-26 | 国际商业机器公司 | Memory cell having improved read stability, memory array and integrate circuit |
| CN102047339A (en) * | 2008-06-19 | 2011-05-04 | 德克萨斯仪器股份有限公司 | Memory cell employing reduced voltage |
| CN102157195A (en) * | 2011-05-05 | 2011-08-17 | 北京大学 | Low-voltage static random access memory unit, memory and writing operation method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105489241A (en) | 2016-04-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101677016B (en) | Dual-port static random access memory unit | |
| US8111542B2 (en) | 8T low leakage SRAM cell | |
| CN101923893B (en) | Static random access memory array | |
| CN105489241B (en) | Static RAM | |
| US20080137440A1 (en) | SRAM cell with separate read and write ports | |
| TWI412037B (en) | Ten - transistor static random access memory architecture | |
| CN101923892A (en) | Stable SRAW cell | |
| CN104183268B (en) | SRAM structure | |
| JP2010510615A (en) | 2-port SRAM with improved write operation | |
| CN103700395B (en) | Memory cell | |
| CN105070315B (en) | SRAM memory cell, SRAM circuit and its reading/writing method | |
| CN105097022B (en) | Nonvolatile memory unit and non-volatile memory unit | |
| CN110415748A (en) | Memory and signal processing method | |
| CN105575421B (en) | Static RAM | |
| CN106098094A (en) | Memory device | |
| CN101877243B (en) | Static RAM | |
| CN107039078A (en) | Non-volatile memory and its reading and writing, storage and restoration methods | |
| CN105575420B (en) | Static RAM | |
| CN101840728B (en) | Dual-end static random access memory (SRMA) unit | |
| CN104575588B (en) | Twins' memory cell | |
| CN105448328B (en) | A kind of SRAM memory cell, SRAM memory and its control method | |
| CN105989874B (en) | Storage unit and its reading/writing method for SRAM | |
| CN114093400B (en) | Low-leakage single-bit memory computing unit and device | |
| CN102117653A (en) | Static random-access memory | |
| CN107591178A (en) | The wordline lifting method and device of SRAM array |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |