CN105472884B

CN105472884B - Circuit board and method for manufacturing the same

Info

Publication number: CN105472884B
Application number: CN201510632836.8A
Authority: CN
Inventors: 闵太泓; 高永宽; 李政韩; 姜明杉
Original assignee: Samsung Electro Mechanics Co Ltd
Current assignee: Samsung Electro Mechanics Co Ltd
Priority date: 2014-09-30
Filing date: 2015-09-29
Publication date: 2020-05-19
Anticipated expiration: 2035-09-29
Also published as: US20160095202A1; KR20160038285A; CN105472884A

Abstract

Provided are a circuit board and a method of manufacturing the same, the circuit board including: a first metal layer having a first via hole penetrating an upper surface of the first metal layer and a lower surface of the first metal layer; a plated portion provided to a surface of the first through-hole; an insulating film provided to a surface of the plating section; and a first via hole formed by disposing a conductive material into at least a part of a region surrounded by an outer surface of the insulating film. Since the circuit board can realize refinement of the first via hole while the first metal layer is formed thicker than in the related art, warpage can be reduced and heat dissipation performance can be improved.

Description

Circuit board and method for manufacturing the same

The present application claims the priority and benefit of korean patent application No. 10-2014-0130868 entitled "Circuit Board and Manufacturing Method thereof", filed in korean intellectual property office at 30.9.2014, the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to a circuit board and a method of manufacturing the same.

Background

In accordance with the trend toward slimness, lightness and high performance of electronic devices, a so-called multi-layer substrate technology of forming a plurality of wiring layers on a circuit board such as a printed circuit board has been developed. In addition, a technique of mounting an electronic device such as an active element or a passive element on a multilayer substrate has been developed.

For example, patent document 1 has disclosed a printed circuit board including an electronic device inserted into a cavity and a plurality of layers, and a manufacturing method thereof.

Meanwhile, according to the tendency of the multi-layered substrate to be slim, the bending phenomenon of the substrate has become a serious problem. The bending phenomenon is also called warping. Since the multi-layered substrate is made of various materials having different thermal expansion coefficients, warpage has been increasingly severe, and research on reducing such warpage has been continuously conducted.

In addition, according to the trend toward multifunction and high performance of Application Processors (APs), etc., the thermal resistance connected to the multi-layered substrate has been significantly increased. As a result, efforts have been made to improve reduction in thermal resistance or improve heat dissipation performance.

In addition, according to the trend of miniaturization of active elements such as application processors, the level of integration has increased and the pitch of external connection terminals of the active elements has been refined. Therefore, there has been a demand to reduce the pitch and increase the level of integration of connection pads (wiring patterns), wiring patterns, and vias included in a multilayer substrate on which active elements are mounted.

[ Prior art documents ]

[ patent document ]

(patent document 1) U.S.2012-0006469a1

(patent document 2) KR 10-2010-0138209A1

Disclosure of Invention

An object of the present disclosure is to provide a circuit board capable of simultaneously refining a via hole penetrating a metal layer and improving heat dissipation performance.

Another object of the present disclosure is to provide a method for manufacturing a circuit board capable of simultaneously refining a via hole penetrating a metal layer and improving heat dissipation performance.

The purpose of the present disclosure is not limited to the purpose described above. That is, other objects not mentioned may be clearly understood by those skilled in the art from the disclosure disclosed in the following description.

According to an exemplary embodiment of the present disclosure, there is provided a circuit board including a first metal layer and a first via penetrating the first metal layer.

The plating section and the insulating film may be disposed between the surface of the first metal layer and the surface of the first via hole.

The plated portion may be realized by multi-stage plating and may include a plurality of plating layers.

The insulating film may be implemented by parylene evaporation.

The first via hole may be realized by a chemical etching method.

According to an embodiment of the present invention, there is provided a circuit board including: a first metal layer having a first via hole penetrating an upper surface of the first metal layer and a lower surface of the first metal layer; a plated portion provided to a surface of the first through-hole; an insulating film provided to a surface of the plating section; and a first via hole formed of a conductive material and disposed on at least a portion of a region surrounded by an outer surface of the insulating film.

According to an embodiment of the present invention, there is provided a circuit board including: a first metal layer having a first via hole penetrating an upper surface of the first metal layer and a lower surface of the first metal layer; a plated portion provided to a surface of the first through-hole; an insulating film provided to a surface of the plating section and having a second through hole surrounded by an outer surface of the insulating film; and the first through hole is arranged in the second through hole.

According to an embodiment of the present invention, there is provided a manufacturing method of a circuit board, the manufacturing method including: forming a first through hole penetrating through the first metal layer; forming a plated portion on a surface of the first through hole; forming an insulating film on a surface of the plated part; a first via hole formed of a conductive material is formed in a space surrounded by at least a part of an outer surface of the insulating film.

According to an embodiment of the present invention, there is provided a circuit board including: a first metal layer including a hole penetrating through a first surface and a second surface of the first metal layer; a conductive via disposed in the hole; a second metal layer interposed between the first metal layer and the conductive via; an electrically insulating layer is based between the second metal layer and the conductive via.

Drawings

Fig. 1 is a sectional view schematically showing a circuit board according to an exemplary embodiment of the present disclosure;

fig. 2 is a cross-sectional view schematically illustrating a circuit board according to another exemplary embodiment of the present disclosure;

fig. 3 is an enlarged sectional view schematically showing a portion a in fig. 1;

fig. 4 is a diagram illustrating a process of forming a second via hole in a method of manufacturing a circuit board according to an exemplary embodiment of the present disclosure;

fig. 5 is a diagram illustrating a process of forming a first via hole in a method of manufacturing a circuit board according to an exemplary embodiment of the present disclosure.

Detailed Description

Various advantages and features of the present disclosure and methods of accomplishing the same will become apparent from the following description of exemplary embodiments, which is to be read in connection with the accompanying drawings. The disclosure may, however, be modified in different forms and are not limited to the exemplary embodiments set forth herein. These exemplary embodiments may be provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout.

The terminology used in the description is for the purpose of describing the exemplary embodiments and is not intended to be limiting of the disclosure. Unless explicitly described to the contrary, singular forms in this specification include plural forms. The words "comprise," "comprising," and/or "consisting of …" when used in this specification are to be understood as implying the inclusion of stated components, steps, operations, and/or elements, but not the exclusion of components, steps, operations, and/or elements.

For simplicity and clarity of illustration, major construction methods will be shown in the drawings, and detailed descriptions of well-known features and techniques in the art will be omitted to prevent unnecessarily obscuring the discussion of the exemplary embodiments of the disclosure. Furthermore, the components shown in the figures are not necessarily shown to scale. For example, the dimensions of the components shown in the figures may be exaggerated relative to other components to help improve understanding of exemplary embodiments of the present disclosure. The same reference numerals denote the same components in different drawings, and the like reference numerals will denote the similar components in different drawings, but it is not limited thereto.

In the description and claims, if terms such as "first", "second", "third", and "fourth", etc., are used to distinguish components similar to each other and to describe a specific order or a production order, however, they are not limited thereto. It is to be understood that these terms are compatible with one another in appropriate circumstances such that the exemplary embodiments of the present disclosure, which will be described below, may operate in different orders than illustrated or described herein. Similarly, in the present specification, in the case where a method is described as having a series of steps, the order of the steps implied herein is not necessarily the order of execution of the steps. That is, any described steps may be omitted and/or any other steps not described herein may be added to the method.

In the description and claims, terms such as "left", "right", "front", "back", "top", "bottom", "above" and "below" do not necessarily denote a constant relative position, but rather are used for descriptive purposes only. It is to be understood that these terms are compatible with one another in appropriate circumstances such that the exemplary embodiments of the disclosure, which will be described below, may operate in different orders than illustrated or described herein. The term "connected," as used herein, is defined as directly or indirectly connected through electrical or non-electrical means. In the context of using the above wording, objects described as being adjacent to each other may be in physical contact with each other, in proximity to each other, or in the same general area or region.

Hereinafter, the configuration and action effects of the exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

Fig. 1 is a sectional view schematically showing a circuit board according to an exemplary embodiment of the present disclosure, fig. 2 is a sectional view schematically showing a circuit board according to another exemplary embodiment of the present disclosure, and fig. 3 is an enlarged sectional view schematically showing a portion a in fig. 1. Further, fig. 4 is a diagram illustrating a process of forming a second through hole in the method of manufacturing the circuit board according to the exemplary embodiment of the present disclosure, and fig. 5 is a diagram illustrating a process of forming a first via hole in the method of manufacturing the circuit board according to the exemplary embodiment of the present disclosure.

The circuit board 100 according to an exemplary embodiment of the present disclosure has a plating part 120 and an insulating film 130 disposed between a via hole penetrating a metal layer and the metal layer. In this case, the plating part 120 may be formed through a multi-stage plating process.

Referring to fig. 1, a circuit board 100 according to an exemplary embodiment of the present disclosure includes a first metal layer 110 and a first via V1. In this case, the circuit board 100 may further include an insulating layer or a wiring pattern as necessary.

According to an exemplary embodiment, the first metal layer 110 may be disposed between the first upper insulation layer 150-1 and the first lower insulation layer 150-2 to serve as a core. That is, since the first metal layer 110 may be much harder than the non-metal layer used to form the conventional circuit board, the first metal layer 110 may serve to reduce warpage of the circuit board 100. In addition, since the first metal layer 110 is formed of a metal material having a higher thermal conductivity than a general insulating material used to form a conventional circuit board, the first metal layer 110 may contribute to improving the heat dissipation performance of the circuit board 100.

Meanwhile, the first via V1 penetrates the first metal layer 110 and serves as an electrical connection path between the upper and lower surfaces of the circuit board 100. In addition, the first via V1 may also serve as a heat transfer channel between the upper and lower surfaces of the circuit board 100.

According to an exemplary embodiment, the plating part 120 and the insulating film 130 are disposed between the surface of the first via hole V1 and the first metal layer 110. That is, in a state where the first via hole VH1 is provided in the first metal layer 110, the plating section 120 may be formed on the surface of the first metal layer 110 and the insulating film 130 may be formed on the outer surface of the plating section 120. In this case, the first metal layer 110 and the plated part 120 formed on the first metal layer 110 may be completely surrounded by the insulating film 130. Therefore, the first metal layer 110 and the plated part 120 formed of a metal different from the first metal may be electrically insulated from the first via hole V1 by the insulating film 130.

Further, the first via hole V1 is formed in the region surrounded by the outer surface of the insulating film 130. Here, an inner portion of a region defined by the first through hole VH1 of the region surrounded by the outer surface of the insulating film 130 may be defined as the second through hole VH 2. Therefore, it can be said that the first via V1 is formed within the second via VH 2. Further, the diameter of the second via VH2 is reduced by the thickness of the plating part 120 and the thickness of the insulating film 130 as compared with the diameter of the first via VH 1.

According to an example embodiment, the first via VH1 may be formed in the first metal layer 110 using a chemical etching process.

In this case, the etching process may be performed on both surfaces of the first metal layer 110, respectively. For example, as shown in fig. 4, in a state in which the plating resist 1 is formed on both surfaces of the first metal layer 110, a first upper via hole VH1-1 may be formed by disposing an etchant into the first opening portion H1-1, and a first lower via hole VH1-2 may be formed by disposing an etchant into the second opening portion H1-2.

In the case of forming a via hole by performing an etching process, since the diameter of the via hole becomes larger than the depth of the via hole, if the first metal layer 110 has the same thickness, refinement of the via hole is facilitated to form the first via hole VH1 by performing etching in the direction from the upper surface to the lower surface of the first metal layer 110 and etching in the direction from the lower surface to the upper surface of the first metal layer 110.

Meanwhile, if the etching process is performed in both directions of the first metal layer 110, the first upper via VH1-1 has a shape whose width decreases in a direction from the upper surface to the lower surface of the first metal layer 110, and the first lower via VH1-2 has a shape whose width decreases in a direction from the lower surface to the upper surface of the first metal layer 110.

According to another exemplary embodiment, the first via VH1 may also be formed in the first metal layer 110 by a laser drilling method. The above laser drilling method can advantageously make the diameter or pitch of the through-holes fine as compared with the above chemical etching method. However, in the case where a large number of through holes need to be machined by the laser drilling method, the production efficiency is lowered as compared with the chemical etching method as described above. In addition, since the thickness of the first metal layer 110 is increased, the efficiency of forming the via hole by the laser drilling method is significantly reduced. Therefore, in the case where the first metal layer 110 having a predetermined thickness or more is required to ensure rigidity required for reducing warpage or improving heat dissipation performance, the first via hole VH1 may be advantageously formed by a chemical etching method rather than a laser drilling method.

Meanwhile, in the case where the first via hole VH1 is formed by using a chemical etching method, the diameter of the first via hole VH1 is proportional to the thickness of the first metal layer 110. It is preferable to use a chemical etching method rather than a laser drilling method in terms of fineness of the via hole, but in the case where the thickness of the first metal layer 110 is increased, the diameter of the first via hole VH1 is increased to a certain level without choice. In addition, as described above, the laser drilling method also has a disadvantage in that process efficiency is significantly reduced due to the thickening of the thickness of the first metal layer 110.

To overcome the above-described limitations, the circuit board 100 according to the exemplary embodiment of the present disclosure has the plating part 120 provided on the first through hole VH 1. Further, an insulating film 130 is provided on the surface of the plated part 120 so as to ensure electrical insulation between the first via hole V1 and the first metal layer 110.

Referring to fig. 1 and 3, the first via hole V1 is formed so as to be in contact with the second via hole VH2 defined through the insulating film 130. Here, in the case where etching is performed on both surfaces of the first metal layer 110 or laser drilling is performed on both surfaces of the first metal layer 110, the first upper via VH1-1 and the first lower via VH1-2 may be classified. Further, in the case where the first upper via VH1-1 and the first lower via VH1-2 are classified as described above, the second via VH2 defined by the insulating film 130 may also be defined as a second upper via VH2-1 and a second lower via VH 2-2. Further, the via formed in the second upper via hole VH2-1 may be defined as a first upper via hole V1-1, and the via formed in the second lower via hole VH2-2 may be defined as a first lower via hole V1-2, wherein the first upper via hole V1-1 and the first lower via hole V1-2 are combined with each other, thereby enabling the first via hole V1 to be formed.

According to an exemplary embodiment, the plating part 120 may be formed through a multi-stage plating process. That is, after the first plating layer 121 is formed by performing a plating process on the surface of the first metal layer 110, the second plating layer 122 is formed by performing another plating process on the surface of the first plating layer 121. Here, each plating layer may be formed by a flash plating method. Although fig. 3 shows the case where the plating part 120 is formed of the first to third plating layers 121 to 123, only two plating layers may be formed or four or more plating layers may be formed as needed. That is, the number of plating layers may be adjusted in consideration of the required diameter of the first via hole V1.

Meanwhile, the insulating film 130 may be applied by evaporating parylene on the surface of the plating section 120. Therefore, by applying the insulating film 130 with parylene deposition, the thickness of the insulating film 130 can be reduced as compared with the case of applying a general insulating material, and an insulating device having a relatively uniform thickness can be provided on the surface of the fine via hole. As a result, when the diameter of the first via V1 is refined, the volume of the first via V1 can be secured to the maximum, and insulation between the first metal layer 110 and the first via V1 can also be secured.

As described above, by forming the plating part 120, the thickness of which is adjusted by the multi-stage plating process, on the surface of the first metal layer (specifically, the surface of the first via hole VH 1), the diameter of the first via hole V1 can be finely adjusted. Further, even in the case where a through hole is formed in a relatively thick metal layer by a chemical etching process, since the diameter of the via hole can be reduced by adjusting the thickness of the plating part 120, the via hole penetrating the metal layer can be refined.

Referring to fig. 1, a first upper conductor pattern P1-1 or an upper inner layer pattern P3 may be disposed on the first metal layer 110. In this case, in order to secure insulation between the first metal layer 110 and the first upper conductor pattern P1-1 or between the first metal layer 110 and the upper inner layer pattern P3, an insulating film 130 may be further provided on the first metal layer 110. Further, the plating part 120 described above may also be provided between the insulating film 130 and the surface of the first metal layer 110. That is, in the process of forming the plating part 120 on the surface of the first through hole VH1, the plating part 120 may also be provided on the upper surface of the first metal layer 110. Further, in the process of forming the insulating film 130 on the plated part 120 formed on the surface of the first through hole VH1, the insulating film 130 may also be provided on the upper surface of the plated part 120 formed on the upper surface of the first metal layer 110.

In addition, an insulating layer may be disposed on the first metal layer 110. According to an exemplary embodiment, a first upper insulating layer 150-1 covering the first metal layer, and the above-described first upper conductor pattern P1-1 and upper inner layer pattern P3, etc. may be provided. Here, the first upper conductor pattern P1-1 may be directly connected to the upper surface of the first via hole V1. In addition, the first upper conductor pattern P1-1 may also be formed such that it integrally forms the first via hole V1 and the first upper conductor pattern P1-1 in the process of forming the first via hole V1.

Meanwhile, a second upper conductor pattern P2-1, an upper outer layer pattern P5, and the like may be further provided on the upper surface of the first upper insulating layer 150-1. In addition, a second upper via hole V2-1 penetrating the first upper insulating layer 150-1 and connecting the second upper conductor pattern P2-1 and the first upper conductor pattern P1-1 may be provided. Further, the upper outer layer pattern P5 may be connected to the upper inner layer pattern P3 through the third via hole V3.

In this case, as shown in fig. 2, the first upper conductor pattern P1-1 may not be provided, and in this case, the upper surfaces of the second upper conductor pattern P2-1 and the first via hole V1 may be connected to each other through the second upper via hole V2-1.

According to an exemplary embodiment, a second upper insulating layer 160-1 is also disposed on the first upper insulating layer 150-1. In this case, the second upper insulating layer 160-1 may be implemented using a solder resist layer, and the second upper insulating layer 160-1 may expose a portion of the second upper conductor pattern P2-1 or a portion of the upper outer layer pattern P5 to the outside of the circuit board 100. Accordingly, a portion exposed outside the second upper insulating layer 160-1 may be connected to other devices, for example, various elements such as active elements, passive elements, and another circuit board 100, and the above devices are illustrated as the first electronic element 200 in fig. 1 and 2. A surface treatment such as a nickel-gold plating layer may be provided to a portion of the second upper conductor pattern P2-1 exposed to the outside of the second upper insulating layer 160-1 or a portion of the upper outer layer pattern P5 exposed to the outside of the second upper insulating layer 160-1, and may be physically or electrically connected to the first electronic component 200 by solder balls SB or wires or the like. Accordingly, the second upper conductor pattern P2-1 or the upper outer layer pattern P5 may serve as the contact pad.

Meanwhile, although the upper portion of the first metal layer 110 is described above, a similar component may be provided to the lower portion of the first metal layer 110. That is, a first lower conductor pattern P1-2, a first lower insulating layer 150-2, a second lower via hole V2-2, a lower inner layer pattern P4, a second lower conductor pattern P2-2, a second lower insulating layer 160-2, and the like may also be provided.

Referring to fig. 1 to 5, a method of manufacturing a circuit board 100 according to an exemplary embodiment of the present disclosure includes: a process of forming a through hole, a process of forming the plating part 120, a process of forming the insulating film 130, and a process of forming a via hole.

First, after the plating resist 1 is formed on the surface of the first metal layer 110, a portion of the plating resist where the first through hole VH1 is to be formed is removed so as to form a first opening portion H1-1 and a second opening portion H1-2.

Next, a first upper via hole VH1-1 and a first lower via hole VH1-2 are formed by applying an etchant to the first opening portion H1-1 and the second opening portion H1-2 formed in the plating resist 1.

Next, the plating part 120 is formed by using the flash plating method, and in this case, the thickness of the plating part 120 can be adjusted by repeatedly performing the plating process.

Next, an insulating film 130 is formed on the surface of the plating section 120. Here, the insulating film 130 may be formed of a parylene material and may be implemented using evaporation. In this case, a space surrounded by the surface of the insulating film 130 may be defined as the second through hole VH 2.

Next, referring to fig. 5, after the plating resist 2 is provided to the first metal layer 110 in which the second via hole VH2 is formed, the first opening portion H1-1 and the second opening portion H1-2 are formed by patterning the plating resist 2.

Next, a first via hole V1 is formed by using the second plating resist 2. In this process, an upper inner layer pattern P3 including a plurality of metal traces or a lower inner layer pattern P4 including a plurality of metal traces may be formed, and a first upper conductor pattern P1-1 and a first lower conductor pattern P1-2 may also be formed, as needed.

Thereafter, the plating resist 2 may be removed, and a typical build-up process may be performed as needed.

According to example embodiments of the present disclosure, the maximum diameter or pitch of the via penetrating the metal layer may be reduced.

In addition, since the via hole can be refined when the metal layer is formed thicker than in the related art, warpage can be reduced and heat dissipation performance can be improved.

Claims

1. A circuit board, comprising:

a first metal layer and a first via hole penetrating the first metal layer, and a conductor pattern is disposed on the first metal layer,

wherein an insulating film and a plated portion are provided between a first metal layer and a first via hole filled in a region surrounded by an outer surface of the insulating film, and

wherein the plating section extends onto a surface of the first metal layer, the insulating film extends onto a surface of a portion of the plating section formed on the surface of the first metal layer, insulating the first metal layer from the conductor pattern,

wherein the plating section includes at least three plating layers.

2. A circuit board, comprising:

a first metal layer on which a conductor pattern is disposed, the first metal layer having a first via hole penetrating an upper surface of the first metal layer and a lower surface of the first metal layer;

a plated portion provided to a surface of the first through-hole;

an insulating film provided to a surface of the plating section;

a first via hole formed of a conductive material and filled on at least a part of a region surrounded by an outer surface of the insulating film,

wherein the plating section includes at least three plating layers.

3. The circuit board according to claim 2, further comprising a second through-hole defined through at least a portion of an outer surface of the insulating film, the second through-hole having a shape corresponding to a shape of the first through-hole and having a diameter smaller than a diameter of the first through-hole.

4. The circuit board of claim 2, wherein each of the at least three plating layers is formed by the same plating process.

5. The circuit board of claim 4, wherein the plating process is performed in a flash plating process.

6. The circuit board of claim 2, further comprising:

a first conductor pattern provided to an outer surface of the first via hole;

a first insulating layer formed on the first metal layer and covering the first conductor pattern;

a second conductor pattern formed on the first insulating layer;

and a second via hole penetrating the first insulating layer and having one end contacting the first conductor pattern and the other end contacting the second conductor pattern.

7. The circuit board of claim 2, further comprising:

a first insulating layer formed on the first metal layer;

a second conductor pattern formed on the first insulating layer;

and a second via hole penetrating the first insulating layer so as to be in contact with the first via hole.

8. The circuit board of claim 7, further comprising:

a second insulating layer exposing at least a portion of the second conductor pattern;

and a connection portion disposed in the second conductor pattern.

9. The circuit board of claim 2, further comprising:

a first upper conductor pattern disposed on the first via hole;

a first upper insulating layer covering the first upper conductor pattern;

a second upper conductor pattern formed on the first upper insulating layer;

and a second upper via hole penetrating the first upper insulating layer and having one end contacting the first upper conductor pattern and the other end contacting the second upper conductor pattern.

10. The circuit board of claim 9, further comprising:

a first lower conductor pattern disposed under the first via hole;

a first lower insulating layer covering the first lower conductor pattern;

a second lower conductor pattern formed on the first lower insulating layer;

and a second lower via hole penetrating the first lower insulating layer and having one end contacting the first lower conductor pattern and the other end contacting the second lower conductor pattern.

11. A circuit board, comprising:

a plated portion provided to a surface of the first through-hole;

an insulating film provided to a surface of the plating section and having a second through hole surrounded by an outer surface of the insulating film;

a first via hole filled in the second via hole,

wherein the plating section includes at least three plating layers.

12. The circuit board of claim 11, wherein the at least three plating layers are each formed by the same plating process.

13. The circuit board of claim 11, wherein the first via comprises:

a first upper via having the following shape: the width is decreasing in a direction from the upper surface of the first metal layer to the lower surface of the first metal layer;

a first lower via having the following shape: the width is reduced in a direction from the lower surface of the first metal layer to the upper surface of the first metal layer.

14. The circuit board of claim 13, wherein the second via has a shape corresponding to a shape of the first via and has a diameter smaller than a diameter of the first via.

15. A method of manufacturing a circuit board, the method comprising:

forming a first through hole penetrating through the first metal layer;

forming a plated portion on a surface of the first through hole;

forming an insulating film on a surface of the plated part;

filling a conductive material in a space surrounded by at least a part of an outer surface of the insulating film to form a first via hole,

wherein the plating section extends onto a surface of the first metal layer, the insulating film extends onto a surface of a portion of the plating section formed on the surface of the first metal layer, insulating the first metal layer from a conductor pattern provided above the first metal layer,

wherein the plating section includes at least three plating layers.

16. The manufacturing method according to claim 15, wherein the second through hole defined by at least a part of the outer surface of the insulating film has a shape corresponding to the shape of the first through hole and has a diameter smaller than the diameter of the first through hole.

17. The manufacturing method according to claim 16, wherein the formation of the at least three plating layers of the plated part is performed by repeating a plating process a plurality of times.

18. The manufacturing method according to claim 17, wherein the plating process is performed in a flash plating method.

19. A circuit board, comprising:

a first metal layer including a hole penetrating through a first surface and a second surface of the first metal layer;

a conductive via filled in the hole;

a second metal layer interposed between the first metal layer and the conductive via;

an electrically insulating layer interposed between the second metal layer and the conductive via, and the electrically insulating layer completely surrounding the first metal layer,

wherein the second metal layer comprises at least three metal layers.

20. The circuit board of claim 19, wherein along the path from the first surface to the second surface of the first metal layer, the area of the conductive via defined at a plane parallel to one of the first surface and the second surface of the first metal layer decreases and then increases.

21. The circuit board of claim 19, further comprising a first upper insulating layer and a first lower insulating layer disposed on the first surface and the second surface of the first metal layer, respectively,

wherein:

the first upper insulating layer and the first lower insulating layer each include a hole overlapping the opening formed in the first metal layer,

the conductive vias further extend along holes formed in the first upper and lower insulating layers.

22. The circuit board of claim 21, further comprising a plurality of metal traces formed on at least one of the first and second surfaces of the first metal layer, and the plurality of metal traces are interposed between the electrically insulating layer and the first upper insulating layer.

23. The circuit board of claim 21, further comprising:

a second upper insulating layer disposed on the first upper insulating layer and including a hole overlapping the hole formed in the first metal layer;

and solder balls filling the holes of the second upper insulating layer.

24. The circuit board of claim 19, wherein the electrically insulating layer is formed of parylene.