CN105470136B - Method, semi-conductor device manufacturing method - Google Patents
Method, semi-conductor device manufacturing method Download PDFInfo
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
A kind of method, semi-conductor device manufacturing method, including：The multiple fins extended in a first direction are formed on substrate；The false grid stacked structure extended in a second direction is formed on fin；In false grid stacked structure grid curb wall is formed along the both sides of first direction；Using grid curb wall as mask, ion implanting is lightly doped in execution, and source drain extension area is formed in both sides fin of the grid curb wall along first direction, wherein ion implanting direction does not have vertical dip angle only with respect to vertical direction, has level inclination also relative to first direction；False grid stacked structure is removed, gate trench is formed；Gate stack structure is formed in gate trench.The uniformity of LDD/SDE structures and lateral junction depth are effectively controlled, the stability of device is improved by adjusting the horizontal sextant angle between angle-tilt ion injection direction and fin structure according to the method, semi-conductor device manufacturing method of the present invention.
Description
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing methods, more particularly to a kind of source and drain with uniformly lateral junction depth
The three-dimensional multi-gate FinFET manufacturing methods of expansion area.
Background technology
In current sub- 20nm technologies, three-dimensional multi-gate device (FinFET or Tri-gate) is main device architecture,
This structure enhances grid control ability, inhibits electric leakage and short-channel effect.
For example, the MOSFET of double gate SOI structure can inhibit short compared with traditional single grid body Si or SOI MOSFET
Channelling effect (SCE) and leakage cause induced barrier to reduce (DIBL) effect, have lower junction capacity, can realize that raceway groove is gently mixed
Miscellaneous, work function that can be by the way that metal gates are arranged can obtain about 2 times of driving current, reduce come adjusting threshold voltage
Requirement for effective gate oxide thickness (EOT).And tri-gate devices are compared with double-gated devices, grid enclose channel region top surface and
Two sides, grid control ability are stronger.Further, loopful is more advantageous around nano wire multi-gate device.
Existing FinFET structure and manufacturing method generally include：Etching is formed multiple in body Si or SOI substrate
The parallel fin extended in a first direction and groove；Ion implanting or deposition doped layer are executed to fin and annealed, in fin
Break-through barrier layer (PTSL) is formed in the middle part of piece to inhibit parasitic channel effect；Fill insulant in the trench is returned and is carved to expose
Part fin forms shallow trench isolation (STI)；At the top of fin and side wall deposition is usually relatively thin (such as only the 1 of silica
~5nm) false grid insulating layer, deposition is usually the false grid layer of polysilicon, non-crystalline silicon on false grid insulating layer；The false grid of etching
Pole layer and false grid insulating layer form the false grid that extends in a second direction and stack, and wherein second direction is preferably perpendicular to the
One direction；It is stacked as mask with false grid, forming lightly doped drain structure (LDD) to the shallow doping of fin progress is especially source drain extension
(SDE) structure with inhibit leakage cause induced barrier reduce effect, doping way may include high inclination-angle shallow junction tilt injection, diffusion or
Person's molecule deposition；It deposits and etches to form grid curb wall along the both sides of first direction what false grid stacked；In grid curb wall
The same or similar material of epitaxial growth forms source-drain area along the fin of the both sides of first direction, it is preferred to use SiGe, SiC etc.
Higher than the material of Si stress to improve carrier mobility；Preferably, contact etching stop layer (CESL) is formed on source-drain area；
Interlayer dielectric layer (ILD) on chip；Etching removal false grid stacks, and gate trench is left in ILD；In gate trench
The grid conducting layer of gate insulating layer and metal/metal alloy/metal nitride (MG) of middle deposited high-k material (HK), and
The gate cap of nitride material is preferably included to protect metal gates.Further, source and drain is formed using mask etching ILD to connect
Contact hole, exposure source-drain area；Optionally, in order to reduce source-drain contact resistance, metal silicide is formed in source and drain contact hole.Filling
Metal/metal nitride forms contact plug, it is usually preferred to the higher metal W of filling rate, Ti.Since CESL, grid curb wall are deposited
Metal W, the Ti of filling can be automatically aligned to source-drain area, ultimately form contact plug.
In general, before forming LDD/SDE structures, such as pass through the preferable depositing operation of the conformalitys such as PECVD, HDPCVD
Insulating dielectric materials layer then using plasma dry etching or the reaction of cvd silicon oxide either nitrogen oxide material first
Ion etching (RIE) technique etches to form the first relatively thin side wall or interim side wall, to be mixed in LDD, SDE or Halo later
Channel region is protected when miscellaneous, minimizes inevitably lateral doping diffusion.Then, it can be formed after LDD is adulterated thicker
The second side wall using as final grid curb wall.
During above-mentioned the first side wall of etching, need strictly to control etch process parameters to accurately control fin top
The bottom width of portion's grid curb wall, because this largely affects the position of LDD, SDE or Halo doped structure later,
Interface location especially between channel region and extension area transverse width.However in characteristic size down to 22nm or less
When, the difficulty that accurately controls for etching especially side wall bottom width increases suddenly.On the other hand, most of dielectric material is being removed
When forming the first side wall, and it is necessary to ensure that and removes completely the medium on false grid insulating layer and at the same time ensuring fin below
Injury-free at the top of piece, which further increases the difficulty of technology controlling and process.
In addition, during above-mentioned injection forms LDD or SDE structures, generally use is angle-tilt ion injection, namely
Relative to substrate normal direction (perpendicular to top surface upward direction) with angle of inclination beta (being referred to Fig. 7) will adulterate from
Required lightly-doped source drain region is formed in son injection fin structure, and in order to enable symmetrical be evenly distributed, often use
Left and right is symmetrical twice to tilt injection.However, with device size continual reductions, grid curb wall is persistently thinned and fin is along ditch
Road direction length also reduces, it is difficult to only obtain equally distributed LDD/SDE structures by controlling vertical tilt angle, it is also difficult to close
The lateral junction depth of reason adjustment is to obtain required channel region and source-drain area interfacial characteristics, and the device of different batches is due to technological parameter
It drifts about and there are performance differences so that the stability of entire block declines.
Invention content
From the above mentioned, it is an object of the invention to overcome above-mentioned technical difficulty, a kind of new FinFET structure manufacture is proposed
Method can effectively control the uniformity of LDD/SDE structures and lateral junction depth, improve the stability of device.
For this purpose, the present invention provides a kind of method, semi-conductor device manufacturing methods, including：It is formed and is prolonged along first direction on substrate
The multiple fins stretched；The false grid stacked structure extended in a second direction is formed on fin；In false grid stacked structure along
The both sides in one direction form grid curb wall；Using grid curb wall as mask, ion implanting is lightly doped in execution, in grid curb wall along first
Source drain extension area is formed in the both sides fin in direction, wherein ion implanting direction does not have only with respect to vertical direction vertically inclines
Angle has level inclination also relative to first direction；False grid stacked structure is removed, gate trench is formed；In gate trench
Form gate stack structure.
Wherein, further comprise before forming false grid stacked structure, execute ion implanting, in the middle part of fin and/or bottom
Portion forms break-through barrier layer.
Wherein, grid curb wall includes horizontal first part and vertical second part.
Wherein, it executes during ion implanting step is lightly doped, using vertical direction as axis, symmetrically rotates ion implanting side
To so that the distribution of Doped ions is uniform relative to first direction and/or second direction in source drain extension area.
Wherein, it executes during ion implanting step is lightly doped, the size of level inclination is adjusted, with voltage input drain extension region edge
The junction depth of first direction.
Wherein, the size of level inclination is 30~60 degree.
Wherein, further comprise before the step of forming gate trench：In grid curb wall along the both sides extension of first direction
Growth promotes source-drain area；Second grid side wall is formed on grid curb wall；Using second grid side wall as mask, ion note is executed
Enter, adjustment promotes the doping type and/or concentration of source-drain area.
Wherein, it is formed after promoting source-drain area and further comprises that forming contact etching stop layer and interlayer on device is situated between
Matter layer.
Wherein, gate stack structure includes the gate insulating layer of hafnium and the grid conducting layer of metal material.
Wherein, execute ion implanting step is lightly doped during, using vertical direction as axis, rotate ion implanting direction and
The size of level inclination is adjusted simultaneously, so that source drain extension area is different along the junction depth of first direction.
According to the method, semi-conductor device manufacturing method of the present invention, by adjusting between angle-tilt ion injection direction and fin structure
Horizontal sextant angle, effectively control the uniformity of LDD/SDE structures and lateral junction depth, improve the stability of device.
Description of the drawings
Carry out the technical solution that the present invention will be described in detail referring to the drawings, wherein：
Fig. 1 to Figure 12 is the schematic diagram according to each step of FinFET manufacturing methods of the present invention；And
Figure 13 is the FinFET structural perspective according to the present invention.
Specific implementation mode
Come the feature and its skill of the present invention will be described in detail technical solution referring to the drawings and in conjunction with schematical embodiment
Art effect discloses the effectively uniformity of control LDD/SDE structures and the three-dimensional multi-gate FinFET manufacturing methods of lateral junction depth.
It should be pointed out that similar reference numeral indicates similar structure, term use herein " first ", " second ",
"upper", "lower" etc. can be used for modifying various device architectures or manufacturing process.These modifications do not imply that institute unless stated otherwise
Modify space, order or the hierarchical relationship of device architecture or manufacturing process.
It is worth noting that, following each attached drawing middle and upper part part is device first direction (fin extension side along Figure 13
To source drain extension direction namely Y-Y ' axis) sectional view, middle section is device (gate stack extension side in a second direction
To perpendicular to first direction namely X-X ' axis) gate stack center line sectional view, low portion is device along being parallel to
Second direction and (namely X1-X1 ' axis) acquisition at position (with certain distance on first direction) except gate stack
Sectional view.
As shown in Figure 1, being formed on substrate 1 between the multiple fin structure 1F and fin structure extended in a first direction
Groove 1G, wherein first direction be future device channel region extending direction (Y-Y ' axis in Figure 13).Substrate 1, lining are provided
Bottom 1 needs according to device application and is reasonably selected, it may include monocrystalline silicon (Si), monocrystal germanium (Ge), strained silicon (Strained
Si), germanium silicon (SiGe) or compound semiconductor materials, for example, gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP),
Indium antimonide (InSb) and carbon-based semiconductors such as graphene, SiC, carbon nanotube etc..It is examined for compatible with CMOS technology
Consider, substrate 1 is preferably body Si.Optional, hard mask layer 2 is formed on substrate 1, such as pass through LPCVD, PECVD, sputtering etc.
Silicon nitride, the silicon oxynitride layer 2 of technique formation.Photoresist is coated on hard mask layer 2 and exposure imaging forms photoetching offset plate figure
(not shown), using photoetching offset plate figure as mask, etch hard mask layer 2 forms hard mask figure, and further with hard mask figure
Shape 2 is mask etching substrate 1, is formed in substrate 1 between multiple groove 1G and groove 1G along first direction parallelly distribute on
The fin 1F that 1 material of remaining substrate is constituted.Etching preferably anisotropic etching, for example, it is plasma dry etch, anti-
Answer ion etching (RIE) or tetramethylammonium hydroxide (TMAH) wet etching so that the depth-to-width ratio of groove 1G is preferably more than
5:1.The width of fin 1F in a second direction is for example only 5~50nm and preferably 10~20nm.
As shown in Fig. 2, forming spacer medium layer 3 on fin structure 1F and substrate 1.For example, the ditch between fin 1F
It is, for example, oxygen to fill material by the process deposits such as PECVD, HDPCVD, RTO (rapid thermal oxidation), spin coating, FlowCVD in slot 1G
SiClx, silicon oxynitride, silicon hydroxide, organic matter etc. are dielectrically separated from dielectric layer 3.As shown in Fig. 2, depositing due to fin structure 1F
There is protrusion at the top of fin structure 1F in the layer 3 of, deposition.Preferably, using flat chemical industry such as CMP, time quarters (etch-back)
Skill process layer 3, until exposure hard mask layer 2.
As shown in figure 3, in fin 1F and/or bottom formed break-through barrier layer (PTSL) 4.Structure shown in Fig. 2 is flat
Change expose hard mask layer 2 after, execute ion implanting, may include N, C, F, P, Cl, As, B, In, Sb, Ga, Si, Ge etc. and its
Combination.Annealing is then executed, such as is heat-treated 1ms~10min under 500~1200 degrees Celsius so that the element and fin of injection
Piece 1F reaction forms (such as the oxygen doped with above-mentioned element of highly doped (Si of doping above-mentioned material) or insulating materials
SiClx) break-through barrier layer 4.In an embodiment of the invention, Implantation Energy and dosage are controlled, is only formd in fin 1F
Channel punchthrough barrier layer 4A, as shown in figure 3, to inhibit channel region to pass through the leakage of the sides STI.However, another excellent in the present invention
It selects in embodiment, controls Implantation Energy and dosage so that break-through barrier layer 4 is also distributed in the bottoms fin 1F and 1 interface of substrate
As STI break-through barrier layer 4B, effectively to completely cut off the leakage between channel region in fin 1F, source-drain area and adjacent fin active area
Electric current.Layer 4B materials can be identical as layer 4A materials, can also include the different component (but including at least oxygen) in above-mentioned element.
Layer 4B can disposably injection forms (different element injection depth are different) simultaneously from layer 4A, can also be successively different twice deep
The injection of degree, dosage, such as first deep distance forming layer 4B can be injected, rear shallow distance injection forming layer 4A, vice versa.This
Outside, other than above-mentioned highly doped break-through barrier layer, a large amount of oxygen (O) can also be injected to form the insulating layer of oxidation silicon substrate
Using as break-through barrier layer (can also further adulterate above-mentioned impurity in the silicon oxide layer).It is worth noting that, channel punchthrough
Height of the barrier layer 4A apart from (or bottom) at the top of fin 1F can arbitrarily be set, in an embodiment of the invention preferably fin
The 1/3~1/2 of piece 1F oneself heights.STI break-through barrier layer 4B and channel punchthrough barrier layer 4A thickness are, for example, 5~30nm.Layer
4A width (along first and/or second direction) set according to entire device active region width, the width of layer 4A then with fin
1F is identical namely the width of layer 4B is significantly greater than the width of layer 4A.
As shown in figure 4, selective etch separation layer 3, forms groove 1G again, a fin 1F parts are exposed.It can adopt
Figure or other hard mask figures with photoresist, select anisotropic lithographic method, such as plasma dry etch,
RIE etches separation layer 3 so that remaining separation layer 3 constitutes shallow trench isolation (STI) 3.Preferably, the depth of groove 1G,
Namely the distance at the top of 3 distance from top fin 1F of STI, it is more than or equal at the top of the 4A distance from top fins 1F of channel punchthrough barrier layer
Distance, to completely inhibit the break-through between channel region.Then, wet etching eliminates hard mask 2.
As shown in figure 5, forming the false grid stacked structure 5 extended in a second direction at the top of fin 1F.In entire device
It is upper to pass through the techniques such as LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, thermal oxide, chemical oxidation, evaporation, sputtering
False grid insulating layer 5A and false grid material layer 5B is formed, and includes preferably further hard mask layer 5C.Layer 5A is, for example, to aoxidize
Silicon, layer 5B are, for example, polysilicon, non-crystalline silicon, amorphous carbon, silicon nitride etc., and layer 5C is, for example, silicon nitride.To have perpendicular to first
The mask plate of the rectangular aperture of the second direction in direction, (similarly, etching is anisotropic to photoetching/etching, preferably etc. successively
Gas ions dry etching, RIE) hard mask layer 5C, false grid material layer 5B and false grid insulating layer 5A, the shape at the top of fin 1F
5 are stacked at the false grid extended in a second direction.As shown in the tops Fig. 5 and middle part, false grid stacks 5 (5C/5B/5A) and only divides
Cloth is not distributed within the scope of the one fixed width along X-X ' axis at the X1-X1 ' axis except certain distance.
As shown in fig. 6, forming first grid side wall 6A on entire device.On entire device by LPCVD, PECVD,
The techniques such as HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, (magnetic control) sputtering form insulation material layer 6, material such as nitrogen
SiClx, silicon oxynitride, silica, containing silicon oxide carbide, amorphous carbon, diamond-like amorphous carbon (DLC) etc. and combinations thereof.In this hair
In bright one embodiment, preferred silicon nitride.Then, using anisotropic etch process, etching insulating material layer 6, only in false grid
Pole stacked structure 5 leaves first grid side wall 6A along the both sides of first direction.Although it is worth noting that, the first grid shown in Fig. 6
Pole side wall 6A is triangle, but in another preferred embodiment of the present invention, side wall 6A preferably has L-type, namely with level
First part and vertical second part, so as to false grid stack 5 keep it is good conformal, to conducive to be thinned grid
The thickness of side wall 6A, further to reduce device size, improve Device uniformity.In a preferred embodiment of the invention, layer
The thickness of 6A such as only 1~5nm, preferably 2~4nm and most preferably 3nm.Layer 6A defines cross during SDE doping later
To diffusion width and protect at the top of fin to reduce defect.
As shown in fig. 7, using first grid side wall layer 6A as mask, fin 1F is carried out angle-tilt ion injection is lightly doped,
At the top of fin 1F and lateral wall circumference forms lightly-doped source drain region (LDD structures or SDE structures) 1LS and 1LD, between the two
Fin 1F constitute channel region 1C.Wherein, vertical dip angle β (injection direction and the sharp angle folded by vertical direction) can example
Such as 0~45 ± 0.5 degree).As shown in fig. 7, in the prior art, generally by the way that using vertical direction as axis, 180 degree rotates chip lining
Bottom 1 rotates nozzle in ion implanting chamber and realizes and formed symmetrically along first direction both sides in false grid stacked structure 5
LDD/SDE structures.Furthermore, it is possible to adjust vertical dip angle β to adjust longitudinal direction (vertically) junction depth of LDD/SDE structures, from
And control bottom interface characteristic between source-drain area and fin 1F.However, as described in the application background technology part, this routine
Adjustment be often limited to first grid side wall 6A thickness and tilt implant angle craft precision limitation, it tends to be difficult to obtain
Obtain higher symmetry and uniformity.
For this purpose, the applicant passes through theory deduction and verification experimental verification, improvement work as shown in Figure 8 A and 8 B is used
Skill is to further increase the uniformity and controllability of LDD/SDE structures.
Specifically, with reference to shown in the plan view of Fig. 8 A, relative to vertical direction in addition to there is vertical dip angle β in ion implanting direction
Except, also there is the water relative to horizontal first direction (fin 1F extending directions, source region-channel region-drain region extending direction)
Flat inclination alpha (angle is only the numerical value of acute angle minimum in folded multiple angles between injection direction and the first direction of level,
Its space direction is not represented).The transverse direction (along first direction) that so, it is possible effectively to obtain uniform lightly-doped source drain region is tied
It is deep.Preferably, as shown in Figure 8 A, in an embodiment of the invention, more with vertical direction (1 normal direction of substrate) for axis
Secondary rotation ion implanting direction is cut down the fluctuation of some direction injection technology will pass through the symmetrical injection of all directions, is made
It is not uniform only about first direction to obtain LDD/SDE structures, and about horizontal second direction (false grid stacked structure 5
Extending direction) it is also uniform, and about vertical direction or uniform.For example, every time 90 degree rotate four times or eight times, or
Person rotates eight times or 16 times for 45 degree every time, or every time 180 degree rotation twice or four times etc. so that rotating every time
The multiple that the product of angle and number of revolutions is 360 degree.In a preferred embodiment of the invention, level inclination α is big in Fig. 8 A
Small is 30~60 degree and preferably 45 degree.
It, can by adjusting the size of level inclination α with reference to shown in Fig. 8 B left side plan views and corresponding right side cross-sectional view
To control transverse direction (along the first direction) junction depth in lightly-doped source drain region.As shown in the tops Fig. 8 B, when level inclination α 1 is smaller, note
The Doped ions entered obtain (smaller relative to horizontal second direction relative to the kinetic energy component of horizontal first direction bigger
Kinetic energy component), the depth for injecting first direction is deeper, and the horizontal line junction depth of LDD/SDE structures is larger namely lightly-doped source drain region
The distance goed deep into below grid curb wall 6A is bigger, and channel region length is smaller.As shown in the lower parts Fig. 8 B, when level inclination α 2 is smaller
When, the Doped ions of injection obtain the kinetic energy component smaller relative to horizontal first direction (relative to horizontal second party
To larger kinetic energy component), the depth for injecting first direction is shallower, and the horizontal line junction depth of LDD/SDE structures is smaller, namely is lightly doped
The distance that source-drain area gos deep into below grid curb wall 6A is smaller, and channel region length is bigger.In a preferred embodiment of the invention, when
When level inclination α magnitude ranges are 30~60 degree, it can control so that lateral junction depth variation range is 0.5~5nm.
It is worth noting that, although symmetrical rotary level inclination and adjustment level inclination is set forth in Fig. 8 A, Fig. 8 B
Size is to obtain the different embodiments of uniform, controllable LDD/SDE structures, as long as but actually ion implanting direction has relatively
In the level inclination of first direction can be realized the present invention it is uniform (dopant along first direction and/or in a second direction uniformly
Distribution) lightly-doped source drain region technical though.Furthermore it is preferred that can combine Fig. 8 A, Fig. 8 B, symmetrical rotary is horizontal
The size of level inclination, such as 30 degree of first time level inclination, second of level inclination 45 are also further finely tuned while inclination angle
Degree, 30 degree of third time level inclination, the 4th 45 degree of sub-level inclination angle can so obtain asymmetric lightly-doped source drain region, be
To being suitable for highly doped source-drain area, to which the various different MOSFET element types needed for obtaining (such as increase drain electrode side
Lateral junction depth and length, to increase driving capability etc.).
As shown in figure 9, stacking epitaxial growth on the region except 5 covering parts by false grid on fin 1F promotes source and drain
1HS and 1HD.Such as it by techniques such as PECVD, MOCVD, MBE, ALD, thermal decomposition, evaporation, sputterings, is gently mixed at the top of fin 1F
Epitaxial growth promotes drain region 1HD and promotes source region 1HS above miscellaneous area 1LS and 1LD.Wherein, promoting source-drain area 1HS/1HD materials can
With identical as substrate 1, fin 1F, such as be Si, can also material it is different, such as with more heavily stressed SiGe, Si:C,
Si:H,SiSn,GeSn,SiGe:C etc. and combinations thereof.Optionally, it is further formed second grid side on first grid side wall 6A
Wall 6B, material technique are similar to first grid side wall.Optionally, in situ mix is carried out while epitaxial growth promotes source and drain
Carry out ion implanting (with second grid side wall 6B) after miscellaneous or extension and heavy doping so that promoting source and drain 1HD/1HS has
Higher than the impurity concentration that source and drain 1LD/1LS is lightly doped.Then, annealing is to activate the impurity of doping.
As shown in Figure 10, contact etching stop layer (CESL) 7A and interlayer dielectric layer (ILD) are formed on entire device
7B.Preferably, the contact etching stop layer 7A of silicon nitride is first formed by techniques such as PECVD, HDPCVD, sputterings on device
(can be omitted).Then, the ILD of silica, low-k materials is formed by the techniques such as spin coating, spraying, silk-screen printing, CVD, PVD
7B, wherein low-k materials include but not limited to organic low-k materials (such as organic polymer containing aryl or polynary ring), inorganic
Low-k materials (such as amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silica glass, BSG, PSG, BPSG), porous low k material (example
Such as Quito hole two silicon three oxygen alkane (SSQ) low-k materials, porous silica, porous SiOCH, mix that C silica, to mix the porous nothings of F fixed
Shape carbon, porous diamond, porous organic polymer).Then, using techniques planarization ILD 7B and hard masks such as CMP, time quarters
Layer 5C is until exposure false grid stacks 5 false grid material layer 5B.
As shown in figure 11, removal false grid stacks 5, forms gate trench 7C.It removes false grid and stacks 5, may be used wet
Method is corroded, such as hot phosphoric acid is directed to silicon nitride, and TMAH is for polysilicon, non-crystalline silicon, strong acid (sulfuric acid, nitric acid) and strong oxidizer
(ozone, hydrogen peroxide) combination is for amorphous carbon, DLC, and (dilution HF or BOE, BOE are sustained release etching agent, NH4F to HF bases corrosive liquid
With HF mixed solutions) it is directed to silica, false grid material layer 5B and false grid insulating layer 5A is thus removed, until exposure fin
At the top of 1F.In addition it is also possible to using anisotropic dry etching (X-X ' axis only in a second direction), the fluorine-based gas of carbon is adjusted
The proportioning of body so that bottom etch rate is more than side wall etch rate, and (etching ratio is greater than 5:1 and preferably 10~15:1), by
This etches the gate trench 7C for forming vertical sidewall pattern.
As shown in figure 12, final gate stack 8 is formed in gate trench 7C.For example, using PECVD, HDPCVD,
The techniques such as MOCVD, MBE, ALD, evaporation, sputtering form gate stack 8 in gate trench.Gate stack 8 includes at least height
The gate insulating layer 8A of the k materials and grid conducting layer 10B of metal_based material.High-g value includes but not limited to including being selected from
HfO2、HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、HfLaSiOxHafnium sill (wherein, each material
Different according to multi-element metal component proportion and chemical valence, oxygen atom content x can be adjusted rationally, be may be, for example, 1~6 and be not limited to
Integer), or including being selected from ZrO2、La2O3、LaAlO3、TiO2、Y2O3Rare-earth-based high K dielectric material, or including Al2O3,
With the composite layer of its above-mentioned material.Grid conducting layer 8B can be then polysilicon, poly-SiGe or metal, and wherein metal may include
The metal simple-substances such as Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La or these metals
Alloy and these metals nitride, can also be doped with elements such as C, F, N, O, B, P, As to adjust in grid conducting layer 10B
Save work function.Between grid conducting layer 8B and gate insulating layer 8A further preferably nitrogen is formed by conventional methods such as PVD, CVD, ALD
The barrier layer (not shown) of compound, barrier layer material are MxNy、MxSiyNz、MxAlyNz、MaAlxSiyNz, wherein M be Ta, Ti, Hf,
Zr, Mo, W or other element.
Common process may be used later and complete device interconnection.For example, being sequentially etched ILD 7B, contact etching stop layer
7A, until exposure source-drain area 1HS/1HD, forms contact hole.The preferably anisotropic dry etching of lithographic method, such as plasma
Dry etching or RIE.Preferably, metal silicide (not shown) is formed on the source-drain area of contact holes exposing to reduce contact
Resistance.For example, in the contact hole evaporation, sputtering, MOCVD, MBE, ALD formed metal layer (not shown), material such as Ni,
The metals such as Pt, Co, Ti, W and metal alloy.Anneal 1ms~10min under 250~1000 degrees Celsius so that metal or metal
Alloy forms metal silicide with Si element reactions contained in source-drain area, to reduce contact resistance.Then fill out in the contact hole
Contact metal layer is filled, such as by techniques such as MOCVD, MBE, ALD, evaporation, sputterings, forms contact metal layer, material is excellent
Select ductility preferably, filling rate is higher and the material of relatively low cost, such as including W, Ti, Pt, Ta, Mo, Cu, Al, Ag, Au
Equal metals, the alloy of these metals and the corresponding nitride of these metals.Then, it is planarized using techniques such as CMP, time quarters
Contact metal layer, until CESL layers of 7A of exposure.
According to the method, semi-conductor device manufacturing method of the present invention, by adjusting between angle-tilt ion injection direction and fin structure
Horizontal sextant angle, effectively control the uniformity of LDD/SDE structures and lateral junction depth, improve the stability of device.
Although illustrating the present invention with reference to one or more exemplary embodiments, those skilled in the art, which could be aware that, to be not necessarily to
It is detached from the scope of the invention and various suitable changes and equivalents is made to device architecture.In addition, can by disclosed introduction
The modification of particular condition or material can be can be adapted to without departing from the scope of the invention by making many.Therefore, the purpose of the present invention does not exist
In being limited to as the preferred forms for realizing the present invention and disclosed specific embodiment, and disclosed device architecture
And its manufacturing method is by all embodiments including falling within the scope of the present invention.
Claims (8)
1. a kind of method, semi-conductor device manufacturing method, including：
The multiple fins extended in a first direction are formed on substrate；
The false grid stacked structure extended in a second direction is formed on fin；
In false grid stacked structure grid curb wall is formed along the both sides of first direction；
Using grid curb wall as mask, ion implanting is lightly doped in execution, is formed in both sides fin of the grid curb wall along first direction
Source drain extension area, wherein ion implanting direction does not have vertical dip angle only with respect to vertical direction, has also relative to first direction
There is level inclination, using vertical direction as axis, rotates ion implanting direction and at the same time adjusting the size of level inclination, so that
Source drain extension area is different along the junction depth of first direction；
False grid stacked structure is removed, gate trench is formed；
Gate stack structure is formed in gate trench.
2. method, semi-conductor device manufacturing method as claimed in claim 1, wherein further comprise before forming false grid stacked structure,
Ion implanting is executed, in the middle part of fin and/or break-through barrier layer is formed on bottom.
3. method, semi-conductor device manufacturing method as claimed in claim 1, wherein grid curb wall includes horizontal first part and vertical
Second part.
4. method, semi-conductor device manufacturing method as claimed in claim 1, wherein during ion implanting step is lightly doped in execution, adjust water
The size at flat inclination angle, with voltage input drain extension region along the junction depth of first direction.
5. method, semi-conductor device manufacturing method as claimed in claim 1, wherein the size of level inclination is 30~60 degree.
6. method, semi-conductor device manufacturing method as claimed in claim 1, wherein further comprise before the step of forming gate trench：
In grid curb wall source-drain area is promoted along the both sides epitaxial growth of first direction；
Second grid side wall is formed on grid curb wall；
Using second grid side wall as mask, ion implanting is executed, adjustment promotes the doping type and/or concentration of source-drain area.
7. method, semi-conductor device manufacturing method as claimed in claim 6, wherein formed after promoting source-drain area and further comprised in device
Upper formation contact etching stop layer and interlayer dielectric layer.
8. method, semi-conductor device manufacturing method as claimed in claim 1, wherein gate stack structure includes the gate insulator of hafnium
The grid conducting layer of layer and metal material.
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