CN105450342A - LDPC codeword interleaving and mapping method and de-interleaving and de-mapping method - Google Patents

Abstract

An LDPC codeword interleaving and mapping method and a de-interleaving and de-mapping method are disclosed. Included are the steps of bit-interleaving a parity portion in an LDPC codeword for the first time to obtain a parity bit stream; splicing an information bit portion in the LDPC codeword and the parity bit stream into an LDPC codeword bit-interleaved for the first time; dividing the LDPC codeword bit-interleaved for the first time into a plurality of successive bit sub-blocks according to a predetermined length, and changing the arrangement sequence of the bit sub-blocks in accordance with a corresponding bit exchange pattern to form an LDPC codeword bit-interleaved for the second time; writing the LDPC codeword bit-interleaved for the second time in accordance with a column sequence, and reading out in accordance with a row sequence to obtain an LDPC codeword bit-interleaved for the third time; and carrying out constellation mapping of the LDPC codeword bit-interleaved for the third time according to a constellation map to obtain a symbol stream. The interleaving and mapping method and the de-interleaving and de-mapping method are selected for different LDPC code tables so that the system performance can be better improved.

Description

The intertexture of LDPC code word and mapping method and deinterleaving de-mapping method

Technical field

The present invention relates to digital television techniques field, particularly a kind of intertexture of LDPC code word and mapping method and deinterleaving de-mapping method.

Background technology

In existing broadcast communication standard, LDPC coding, Bit Interleave and constellation mapping are code modulation modes the most common.In different emission systems, LDPC coding, Bit Interleave and constellation mapping all need independent design, and combined debugging, to obtain best channel performance.Therefore, how forming Bit Interleave targetedly for specific LDPC code word and constellation mapping mode, is a technical barrier of this area.

Summary of the invention

The problem that the present invention solves cannot form Bit Interleave targetedly for specific LDPC code word and constellation mapping mode in prior art.

For solving the problem, embodiments providing a kind of intertexture and mapping method of LDPC code word, comprising the steps: the check part in described LDPC code word to carry out first time Bit Interleave to obtain check bit stream; Information bit part in described LDPC code word and described check bit stream are spliced into the LDPC code word after first time Bit Interleave; LDPC code word after described first time Bit Interleave is divided into the multiple sub-blocks of bits of continuous print by predetermined length, and puts in order the LDPC code word after forming second time Bit Interleave according to sub-blocks of bits described in corresponding bit exchange pattern change; LDPC code word column major order write memory space after described second time Bit Interleave is also sequentially read the LDPC code word after obtaining third time Bit Interleave by row in this memory space; Constellation mapping is carried out to obtain symbol stream according to corresponding planisphere to the LDPC code word after described third time Bit Interleave.

The embodiment of the present invention additionally provides a kind of deinterleaving de-mapping method of LDPC code word, comprises the steps: to carry out soft demapping process to obtain bit soft value data to symbol stream soft value data according to corresponding planisphere; Wherein said symbol stream soft value data are the symbol stream that interlace map method that receiving terminal receives LDPC code word described above obtains; Described bit soft value data are sequentially written in memory space by row and column major order reads to obtain first time than the bit soft value data after deinterleave in this memory space; Described first time is divided into the multiple bit soft value data sub-block of continuous print than the bit soft value data after deinterleave by predetermined length, and according to bit soft value data sub-block described in corresponding bit exchange pattern change put in order form second time than the bit soft value data after deinterleave; Described second time is carried out third time than deinterleave to obtain third time than the bit soft value data after deinterleave than the bit soft value data of the check part corresponded in LDPC code word in the bit soft value data after deinterleave; Described second time is spliced into bit soft value data flow with described third time than the bit soft value data after deinterleave than in the bit soft value data after deinterleave; LDPC decoding process is carried out to obtain decoded bitstream data to described bit soft value data flow.

Compared with prior art, technical solution of the present invention has the following advantages:

Corresponding interlace map and deinterleaving de-mapping method is selected better to be promoted to make systematic function for specific LDPC code table.

Accompanying drawing explanation

Fig. 1 is the schematic flow sheet of the embodiment of the interlace map method of a kind of LDPC code word of the present invention;

Fig. 2 is the schematic flow sheet of the embodiment of the deinterleaving de-mapping method of a kind of LDPC code word of the present invention;

Fig. 3 be in the interlace map method of a kind of LDPC code word of the present invention to the check part in LDPC code word carry out first time Bit Interleave to obtain the schematic diagram of check bit stream;

Fig. 4 is the schematic diagram put in order according to sub-blocks of bits described in bit exchange pattern change in the interlace map method of a kind of LDPC code word of the present invention.

Embodiment

Inventor finds in prior art, cannot form Bit Interleave targetedly for specific LDPC code word and constellation mapping mode.

For the problems referred to above, inventor is through research, provide a kind of interlace map method and deinterleaving de-mapping method of LDPC code word, select corresponding interlace map and deinterleaving de-mapping method better to be promoted to make systematic function for different LDPC code tables.

For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.

In embodiments of the present invention, transmitter terminal is: first the bit stream after message sink coding, Bose-Chaudhuri-Hocquenghem Code is input to the coding that LDPC encoder carries out the LDPC code word of specific code check code length, input bit interleaver afterwards, interleaving treatment is carried out according to certain specific Bit Interleave patterning method, subsequently the data after Bit Interleave process are carried out the 64QAM constellation mapping of corresponding code check, modulate afterwards, launch, experience channel.Receiver end is: the data after channel are carried out demodulation, and the data input De-mapping module then after demodulation, carries out 64QAM demapping.Afterwards the bit soft value information that De-mapping module exports is input to de-interleaving block and carries out deinterleaving, output to ldpc decoder afterwards, the decoding based on specific LDPC code word is carried out to it, output bit flow of finally decoding.

As shown in Figure 1 be the schematic flow sheet of the embodiment of the interlace map method of a kind of LDPC code word of the present invention.With reference to figure 1, the interlace map method of LDPC code word comprises the steps:

Step S11: the check part in described LDPC code word is carried out first time Bit Interleave to obtain check bit stream;

Step S12: the information bit part in described LDPC code word and described check bit stream are spliced into the LDPC code word after first time Bit Interleave;

Step S13: the LDPC code word after described first time Bit Interleave is divided into the multiple sub-blocks of bits of continuous print by predetermined length, and put in order the LDPC code word after forming second time Bit Interleave according to sub-blocks of bits described in corresponding bit exchange pattern change;

Step S14: the LDPC code word column major order write memory space after described second time Bit Interleave is also sequentially read the LDPC code word after obtaining third time Bit Interleave by row in this memory space;

Step S15: constellation mapping is carried out to obtain symbol stream according to corresponding planisphere to the LDPC code word after described third time Bit Interleave.

In the present embodiment, described step S11 specifically comprises the steps: the check part column major order write memory space in described LDPC code word and sequentially reads to obtain check bit stream in this memory space by row.

Particularly, the check portion generating LDPC code word is divided and carries out Bit Interleave: check part M the bit altogether of LDPC code word, write in a memory space by row, often arrange Q bit, altogether L row, that is M=Q*L, then sequentially reads by row.Its specific implementation process is with reference to shown in figure 3.

In described step S13, the LDPC code word after described first time Bit Interleave is divided into the multiple sub-blocks of bits of continuous print by predetermined length, and wherein said predetermined length is 320.Further, according to sub-blocks of bits described in corresponding bit exchange pattern change put in order formed second time Bit Interleave after LDPC code word.Its detailed process is detailed as shown in Figure 4, in the diagram, and (m ₀, m ₁..., m _n/320-1) be the bit exchange pattern of 320 length bits sub-blocks.

Particularly, the code length of the LDPC code word in LDPC code table is 57600, and corresponding bit exchange pattern is:

17711653615083651455127163198063

100147446728153911511854148382159

1358412010914016215682190183011993

1251692477178142271334210188137

15711659828133337311226216791555095

130717599515635924617964401170154

14596110254869604112416429131176

104761285170571065211313173722370

111178610121661266741216826781514

9711108156143611231021747139

144152944515816698134175731388

871498516011249136431728916753146

58471611321031051713491321412022

10712939114

It should be noted that, in the present embodiment, each numerical value in described bit exchange pattern refers to the position without sub-blocks of bits described before bit exchange.Such as, first numerical value 177 implication in above-mentioned bit exchange pattern refers to and original after bit exchange, nowadays becomes first sub-blocks of bits without the 178th sub-blocks of bits before bit exchange.

Corresponding planisphere is:

Constellation point	Complex symbol
		0	1.4327+0.3305i
1	1.0898+0.3010i
		2	1.2422+0.7866i
3	0.9757+0.5712i
		4	0.3305+1.4327i
5	0.3010+1.0898i
		6	0.7866+1.2422i
7	0.5712+0.9757i
		8	0.3881+0.2101i
9	0.5513+0.2471i
		10	0.3825+0.2202i
11	0.5339+0.2828i

12	0.2101+0.3881i
		13	0.2471+0.5513i
14	0.2202+0.3825i
		15	0.2828+0.5339i
16	-1.4327+0.3305i
		17	-1.0898+0.3010i
18	-1.2422+0.7866i
		19	-0.9757+0.5712i
20	-0.3305+1.4327i
		21	-0.3010+1.0898i
22	-0.7866+1.2422i
		23	-0.5712+0.9757i
24	-0.3881+0.2101i
		25	-0.5513+0.2471i
26	-0.3825+0.2202i
		27	-0.5339+0.2828i
28	-0.2101+0.3881i
		29	-0.2471+0.5513i
30	-0.2202+0.3825i
		31	-0.2828+0.5339i
32	1.4327-0.3305i
		33	1.0898-0.3010i

34	1.2422-0.7866i
		35	0.9757-0.5712i
36	0.3305-1.4327i
		37	0.3010-1.0898i
38	0.7866-1.2422i
		39	0.5712-0.9757i
40	0.3881-0.2101i
		41	0.5513-0.2471i
42	0.3825-0.2202i
		43	0.5339-0.2828i
44	0.2101-0.3881i
		45	0.2471-0.5513i
46	0.2202-0.3825i
		47	0.2828-0.5339i
48	-1.4327-0.3305i
		49	-1.0898-0.3010i
50	-1.2422-0.7866i
		51	-0.9757-0.5712i
52	-0.3305-1.4327i
		53	-0.3010-1.0898i
54	-0.7866-1.2422i
		55	-0.5712-0.9757i

56	-0.3881-0.2101i
		57	-0.5513-0.2471i
58	-0.3825-0.2202i
		59	-0.5339-0.2828i
60	-0.2101-0.3881i
		61	-0.2471-0.5513i
62	-0.2202-0.3825i
		63	-0.2828-0.5339i

In described step S14, such as, be the LDPC code word (the LDPC code word after second time Bit Interleave) of 57600 bits for code length, its column major order write memory space is also sequentially read by row in this memory space, wherein every row 9600 bit, totally 6 row.

Afterwards to the bitstream data (b after above-mentioned Bit Interleave ₀, b ₁..., b _n-1), according to 64QAM planisphere, the decimal number corresponding to every six binary bit sequence is mapped to some constellation point, obtains symbol stream (the corresponding constellation point of each complex symbol).Such as, two corresponding decimal numbers of bit ' 001101 ' of input are 13, then correspond to the constellation point of the 0.2471+0.5513i in 64QAM planisphere, this constellation point being shown as on real number axis and axis of imaginaries, real number axis 0.2471, axis of imaginaries 0.5513.Then utilize symbol stream to carry out generation OFDM symbol at modulation module, finally launch.

In the present embodiment, described LDPC code word be to message sink coding after bit stream obtain after specific LDPC coding, wherein said specific LDPC coding can adopt prior art to realize.

Particularly, the code word of this LDPC is with L × L (L is generally 320) for sub-block size, and code table is as follows:

Table 1 code check 1/3N _ldpc=57600, L × L=320 × 320,

Q＝120,M1＝1280,M2＝37120

Its coding method is as follows:

By the bit stream after message sink coding, be split as block of information one by one, each block of information is made up of K information bit, is expressed as S=(s ₀, s ₁..., s _k-1).By the specific LDPC coding in Fig. 1, be will according to S=(s ₀, s ₁..., s _k-1) generate M ₁+ M ₂individual check bit namely the code word Λ=(λ of N number of bit is obtained ₀, λ ₁..., λ _n-1), wherein N=K+M ₁+ M ₂.Λ can be expressed as again,

The step of coding is:

1) initialization λ _i=s _i, i=0,1 ..., K-1.p _j＝0，j＝0,1,...,M ₁+M ₂-1

2) to information bit λ ₀, add up for the check bit of address to the first row numeral in code table, lift table 1 code check 1/3, the code table of code length 57600 is example:

Because its first row numeral is:

6326571119608615618260272686631291330923502635421

$\begin{array}{c}{p}_{632}=p_{632}\⊕{\mathrm{\λ}}_0,p_{657}=p_{657}\⊕{\mathrm{\λ}}_0,p_{1119}=p_{1119}\⊕{\mathrm{\λ}}_0,......,\\ p_{35026}=p_{35026}\⊕{\mathrm{\λ}}_0,p_{35421}=p_{35421}\⊕{\mathrm{\λ}}_0\end{array}.$

3) for an ensuing L-1 information bit, (usual L=320), λ _m, m=1,2 ...., L-1, adds up with the check bit according to following y being address respectively by each information bit:

$y=\left\{\begin{array}{c}(x+m\&times;Q_1)\mathrm{mod}{M}_1\mathrm{ifx}<M_1\\ M_1+\left\{(x-M_1+m\&times;Q_2)\mathrm{mod}{M}_2\right\}\mathrm{ifx}>M_1\end{array}\right.$

Wherein, x refers to and λ ₀relevant check digit address, act table 1 is example, the numeral 6326571119608615618260272686631291330923502635421 of the first row in x and code table.And $Q_1=\frac{M_1}{L},Q_2=\frac{M_2}{L}.$

Code word for table 1 is example,

$Q_1=\frac{M_1}{L}=\frac{1280}{320}=4,Q_2=\frac{M_2}{L}=\frac{37120}{320}=116.$

$\begin{array}{c}{p}_{632}=p_{632}\&CirclePlus;{\mathrm{\&lambda;}}_0,p_{657}=p_{657}\&CirclePlus;{\mathrm{\&lambda;}}_0,p_{1119}=p_{1119}\&CirclePlus;{\mathrm{\&lambda;}}_0,......,\\ p_{35026}=p_{35026}\&CirclePlus;{\mathrm{\&lambda;}}_0,p_{35421}=p_{35421}\&CirclePlus;{\mathrm{\&lambda;}}_0\end{array}.$

4) for L information bit λ _l, according to the second line number word address in code table, check bit is added up.Same for an ensuing L-1 information bit, to continue according to step 3) in formula check bit is added up, the at this time numeral of the second row in the x of the formula of step 3 kind and code table.

5) in like manner, for 2L, 3L, 4L ... iL ... individual information bit, according to difference the 3rd in code table, 4, 5, (i+1) add up to check bit in the address that L.... is capable, L-1 information bit after its information bit is then respectively according to step 3) in formula check bit is added up, note the x of the formula of at this time step 3 kind corresponding be row in code table corresponding to a current i-th L information bit, L-1 bit after such as the i-th L information bit, its applying step 3) in formula time corresponding x address be (i+1) in code table OK.

6) step 5 is finished) after, be done as follows:

wherein i=1,2 ..., M ₁-1

The embodiment of the present invention additionally provides a kind of deinterleaving de-mapping method of LDPC code word.As shown in Figure 2 be the schematic flow sheet of the embodiment of the deinterleaving de-mapping method of a kind of LDPC code word of the present invention.With reference to figure 2, the deinterleaving de-mapping method of LDPC code word comprises the steps:

Step S21: soft demapping process is carried out to obtain bit soft value data according to corresponding planisphere to symbol stream soft value data;

Step S22: described bit soft value data are sequentially written in memory space by row and column major order reads to obtain first time than the bit soft value data after deinterleave in this memory space;

Step S23: described first time is divided into the multiple bit soft value data sub-block of continuous print than the bit soft value data after deinterleave by predetermined length, and according to bit soft value data sub-block described in corresponding bit exchange pattern change put in order form second time than the bit soft value data after deinterleave;

Step S24: described second time is carried out third time than deinterleave to obtain third time than the bit soft value data after deinterleave than the bit soft value data of the check part corresponded in LDPC code word in the bit soft value data after deinterleave;

Step S25: described second time is spliced into bit soft value data flow with described third time than the bit soft value data after deinterleave than in the bit soft value data after deinterleave;

Step S26: LDPC decoding process is carried out to obtain decoded bitstream data to described bit soft value data flow.

In the present embodiment, described step S24 specifically comprises: described second time is sequentially written in memory space by row than the bit soft value data of the check part corresponded in LDPC code word in the bit soft value data after deinterleave and column major order reads to obtain third time than the bit soft value data after deinterleave in this memory space.

By the coding of above-mentioned LDPC, intertexture and modulation system, the thresholding of system under awgn channel can be made to reach 6.08, and the thresholding under rayleigh fading channel reaches 7.82, effectively can increase coverage rate.

Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.

Claims (7)

1. an interlace map method for LDPC code word, is characterized in that, comprise the steps:

Check part in described LDPC code word is carried out first time Bit Interleave to obtain check bit stream;

Information bit part in described LDPC code word and described check bit stream are spliced into the LDPC code word after first time Bit Interleave;

LDPC code word after described first time Bit Interleave is divided into the multiple sub-blocks of bits of continuous print by predetermined length, and puts in order the LDPC code word after forming second time Bit Interleave according to sub-blocks of bits described in corresponding bit exchange pattern change;

LDPC code word column major order write memory space after described second time Bit Interleave is also sequentially read by row in this memory space, obtains the LDPC code word after third time Bit Interleave;

Constellation mapping is carried out to obtain symbol stream according to corresponding planisphere to the LDPC code word after described third time Bit Interleave; Wherein, described bit exchange pattern and described planisphere are all corresponding from the LDPC code table of different code check.

2. the interlace map method of LDPC code word as claimed in claim 1, is characterized in that, the check part in described LDPC code word is carried out first time Bit Interleave and comprises to obtain check bit stream:

Check part column major order write memory space in described LDPC code word also is sequentially read to obtain check bit stream by row in this memory space.

3. the interlace map method of LDPC code word as claimed in claim 1, it is characterized in that, described predetermined length is 320 bits.

4. the interlace map method of LDPC code word as claimed in claim 1, is characterized in that, in described LDPC code table, the code length of LDPC code word is 57600 bits, code check is 1/3;

Code table is:

Corresponding bit exchange pattern is: 17711653615083651455

1271631980631001474467281539115

1185414838215913584120109140162

15682190183011993125169247717814227

13342101881371571165982813333731

12262167915550951307175995156359246

17964401170154145961102548696041124

164291311761047612851705710652

113131737223701111786101216612667412

16826781514971110815614361123

1021747139144152944515816698

13417573138887149851601124913643

17289167531465847161132103105

171349132141202210712939114

Corresponding planisphere is:

Constellation point Complex symbol 0 1.4327+0.3305i 1 1.0898+0.3010i 2 1.2422+0.7866i 3 0.9757+0.5712i 4 0.3305+1.4327i 5 0.3010+1.0898i

6 0.7866+1.2422i 7 0.5712+0.9757i 8 0.3881+0.2101i 9 0.5513+0.2471i 10 0.3825+0.2202i 11 0.5339+0.2828i 12 0.2101+0.3881i 13 0.2471+0.5513i 14 0.2202+0.3825i 15 0.2828+0.5339i 16 -1.4327+0.3305i 17 -1.0898+0.3010i 18 -1.2422+0.7866i 19 -0.9757+0.5712i 20 -0.3305+1.4327i 21 -0.3010+1.0898i 22 -0.7866+1.2422i 23 -0.5712+0.9757i 24 -0.3881+0.2101i 25 -0.5513+0.2471i 26 -0.3825+0.2202i

27 -0.5339+0.2828i 28 -0.2101+0.3881i 29 -0.2471+0.5513i 30 -0.2202+0.3825i 31 -0.2828+0.5339i 32 1.4327-0.3305i 33 1.0898-0.3010i 34 1.2422-0.7866i 35 0.9757-0.5712i 36 0.3305-1.4327i 37 0.3010-1.0898i 38 0.7866-1.2422i 39 0.5712-0.9757i 40 0.3881-0.2101i 41 0.5513-0.2471i 42 0.3825-0.2202i 43 0.5339-0.2828i 44 0.2101-0.3881i 45 0.2471-0.5513i 46 0.2202-0.3825i 47 0.2828-0.5339i

48 -1.4327-0.3305i 49 -1.0898-0.3010i 50 -1.2422-0.7866i 51 -0.9757-0.5712i 52 -0.3305-1.4327i 53 -0.3010-1.0898i 54 -0.7866-1.2422i 55 -0.5712-0.9757i 56 -0.3881-0.2101i 57 -0.5513-0.2471i 58 -0.3825-0.2202i 59 -0.5339-0.2828i 60 -0.2101-0.3881i 61 -0.2471-0.5513i 62 -0.2202-0.3825i 63 -0.2828-0.5339i

5. the interlace map method of LDPC code word as claimed in claim 1, it is characterized in that, the number of described column major order is 6 row.

6. a deinterleaving de-mapping method for LDPC code word, is characterized in that, comprise the steps:

Soft demapping process is carried out to obtain bit soft value data according to corresponding planisphere to symbol stream soft value data; Wherein said symbol stream soft value data are the symbol stream that interlace map method that receiving terminal receives LDPC code word as claimed in claim 1 obtains;

Described bit soft value data are sequentially written in memory space by row and column major order reads to obtain first time than the bit soft value data after deinterleave in this memory space;

Described first time is divided into the multiple bit soft value data sub-block of continuous print than the bit soft value data after deinterleave by predetermined length, and according to bit soft value data sub-block described in corresponding bit exchange pattern change put in order form second time than the bit soft value data after deinterleave;

Described second time is carried out third time than deinterleave to obtain third time than the bit soft value data after deinterleave than the bit soft value data of the check part corresponded in LDPC code word in the bit soft value data after deinterleave;

Described second time is spliced into bit soft value data flow with described third time than the bit soft value data after deinterleave than in the bit soft value data after deinterleave;

LDPC decoding process is carried out to obtain decoded bitstream data to described bit soft value data flow.

7. the deinterleaving de-mapping method of LDPC code word as claimed in claim 6, it is characterized in that, describedly described second time is carried out third time than the bit soft value data of the check part corresponded in LDPC code word in the bit soft value data after deinterleave comprise than the bit soft value data after deinterleave to obtain third time than deinterleave:

Described second time is sequentially written in memory space by row than the bit soft value data of the check part corresponded in LDPC code word in the bit soft value data after deinterleave and column major order reads in this memory space, the described columns that also column major order reads of write is by row 6 row, obtains third time than the bit soft value data after deinterleave.