CN105450237A - Digital intermediate-frequency dynamic range expansion method - Google Patents

Abstract

The invention provides a digital intermediate-frequency dynamic range expansion method. A significance bit detection unit, a data left shift unit and an output data gain adjusting unit are included. The method comprises the following steps of sending a group of integer ADC sampling data with n-bit resolution into an RAM of a FPGA, and simultaneously carrying out data significance bit detection; when input of the group of the ADC sampling data is completed, acquiring a maximum significant bit digit and taking as a M; sending a difference of n-M into an operation streamline of the FPGA and successively carrying out left shift n-M bit on each ADC data in the data left shift unit; sending the data after left shift into an intermediate-frequency digital signal processing unit, in the intermediate-frequency digital signal processing unit, intercepting output data of all the integer data multiplication operations, except for a last level of multiplication operation; converting a data format of the output data of the intermediate-frequency digital signal processing unit from the integer into a floating point type; for floating point type output data, according to a left shift digit n-M in a data left shift unit, carrying out gain adjusting.

Description

A kind of digital intermediate frequency dynamic rage extension method

Technical field

The present invention relates to radio art, particularly a kind of digital intermediate frequency dynamic rage extension method.

Background technology

Based on the time-frequency conversion process of principle of Software Radio, its digital intermediate frequency preliminary treatment comprises the processes such as down-conversion, filtering, windowing, and time-frequency conversion generally takes FFT computing, and implementation completes in DSP or FPGA.For ensureing that data handling procedure exports the signal to noise ratio of data and the consistent of input data, need the data type using operational precision high, i.e. real-coded GA.

Integer sampled data is converted to floating type feeding Floating-point DSP and carries out computing by prior art, or carries out computing with real-coded GA form in FPGA, and as shown in Figure 1, its data processing performing step is as follows:

First, adc data form is carried out data type conversion, converts floating type to from integer;

Then, real-coded GA is sent into digital medium-frequency signal processing unit and carry out data calculating.

The shortcoming of prior art is as follows:

(1), when realizing digital medium-frequency signal process based on Floating-point DSP, because DSP is single command cycle serial operational mode, when data transfer rate is higher, DSP cannot realize the requirement of real-time processing speed;

(2) if all carry out computing with real-coded GA form in FPGA, same multiplying, shared by real-coded GA, stock number is far more than integer data, and under the pressure of limited logical resource, this technology is not suitable for digital medium-frequency signal process.

Summary of the invention

For solving the deficiencies in the prior art, the invention provides a kind of new digital intermediate frequency dynamic rage extension method, the deterioration of data cutout to digital intermediate frequency signal to noise ratio is reduced under the prerequisite not changing the computing of original FPGA integer data and data cutout, dynamic range expanded, meet the real-time of data processing simultaneously.

Technical scheme of the present invention is achieved in that

A kind of digital intermediate frequency dynamic rage extension method, also comprise significance bit detecting unit, data shift cells left and export data gain adjustment unit, performing step is as follows:

Step (1), is that the integer ADC sampled data of n position sends into the RAM of FPGA simultaneously by one group of resolution, synchronously carries out data valid bit detection, obtain most significant digit number, be designated as M when one group of ADC sampled data input is complete;

Step (2), the difference of n-M is sent into the arithmetic pipelining of FPGA, move to left each adc data successively n-M position in data shift cells left;

Data after moving to left are sent into digital intermediate frequency signal processing unit, in this element, except afterbody multiplying, are intercepted the output data of all integer data multiplyings by step (3);

Step (4), is converted to floating type by the data format of the output data of digital intermediate frequency signal processing unit from integer;

Step (5), exports data to floating type and carries out Gain tuning according to the figure place n-M that moves to left in data shift cells left.

Alternatively, if a sampled data is A (n)=a ₀2 ⁰+ a ₁2 ¹+ a ₂2 ²+ ... + a _n-22 ^n-2+ a _n-12 ^m-1, a _i∈ { 0,1 }, 0≤i≤n-1, a total n position, most significant digit number is M, and the n-M position that moves to left retains computing number of significant digit to greatest extent, and the data after moving to left are designated as A ' (n);

The binary data be multiplied with it is set to m position, is expressed as follows:

B (m)=b ₀2 ⁰+ b ₁2 ¹+ b ₂2 ²+ ... + b _m-22 ^m-2+ b _m-12 ^m-1, wherein b _i∈ { 0,1 }, 0≤i≤m-1;

Then A (n) with B (n) its coefficient matrix mutually multiplied is:

Because A (n) and the most significant digit of B (n) are M and m, therefore a respectively _m-1b _m-1=1, A (n) B (m)>=2 ^m+m-2;

As M > m, A (n) is as follows with the product representation of B (n):

A(n)·B(m)＝a _M-1b _m-1·2 ^M+m-2+(a _M-1b _m-2+a _M-2b _m-1)·2 ^M+m-3+…

+(a _M-mb _m-1+a _M-m+1b _m-2+…+a _M-2b ₁+a _M-1b ₀)·2 ^M-1

≤2 ^M-1·(2 ^m-1+2·2 ^m-2+3·2 ^m-3+…+m·2 ⁰)

＝2 ^M-1·(2 ^m+1-m-2)＜2 ^M+m

So have 2 ^m+m-2≤ A (n) B (m) < 2 ^m+m;

As M < m, A (n) is as follows with the product representation of B (n):

A(n)·B(m)＝a _M-1b _m-1·2 ^M+m-2+(a _M-1b _m-2+a _M-2b _m-1)·2 ^M+m-2+…

+(a ₀b _m-1+a ₁b _m-2+…+a _M-2b _m-M+1a _M-1b _m-M)·2 ^M-1

≤2 ^m-1·(2 ^M-1+2·2 ^M-2+3·2 ^M-3+…+M·2 ⁰)

＝2 ^m-1·(2 ^M+1-M-2)＜2 ^M+m

So have 2 ^m+m-2≤ A (n) B (m) < 2 ^m+m;

Therefore, the highest significant position of A (n) B (m) is 2 ^m+m-2or 2 ^m+m-1;

When the highest significant position of A (n) B (m) is 2 ^m+m-2time:

The result of A (n) B (m) is expressed as $A\left(n\right)\&CenterDot;B\left(m\right)={\mathrm{\&Sigma;}}_{k=0}^{M+m-2}{X}_k\&CenterDot;2^k,X_k\&Element;\{0,1\};$

With [] _trepresent cut position process, if cut out low K position, then ${\&lsqb;A\left(n\right)\&CenterDot;B\left(m\right)\&rsqb;}_T={\mathrm{\&Sigma;}}_{k=K}^{M+m-2}{X}_k\&CenterDot;2^k;$

If E _tfor cut position error, then the cut position error of A (n) B (m) is $E_T={\&lsqb;A\left(n\right)\&CenterDot;B\left(m\right)\&rsqb;}_T-A\left(n\right)\&CenterDot;B\left(m\right)=-{\mathrm{\&Sigma;}}_{k=0}^{K-1}{X}_k\&CenterDot;2^k,$ Work as X _kwhen being 1, cut position error is maximum, now E _t=-(2 ^k-1), 2 ^k> > 1, and make q=2 ^k, i.e.-q < E _t≤ 0;

N number of n position sampled data is carried out multiplying and after intercepting, is generated N number of E in FPGA _tform and intercept error sequence, be set to e (j), j=0,1,2 ..., N-1;

So the probability density function of e (j) is

Its average is $m_e={\&Integral;}_{-q}^0\frac{1}{q}e\left(j\right)de\left(j\right)=-\frac{q}{2}=\frac{2^K}{2},$ Variance is ${\mathrm{\&sigma;}}_e^2={\&Integral;}_{-q}^0{\&lsqb;e\left(j\right)+\frac{q}{2}\&rsqb;}^2\frac{1}{q}de\left(j\right)=\frac{q^2}{12}=\frac{2^{2K}}{12};$

If the power of A (n) B (m) is then the logarithm of the signal to noise ratio of A (n) B (m) is expressed as:

A (n) the sequence sequence behind n-M position that moves to left is A ' (n)=A (n) 2 ^n-M, the result of A ' (n) B (m) is expressed as $A^{\&prime;}\left(n\right)\&CenterDot;B\left(m\right)={\mathrm{\&Sigma;}}_{k=n-M}^{n+m-2}{X}_k\&CenterDot;2^k,$ Cut out low K position, K > n-M, then ${\&lsqb;A^{\&prime;}\left(n\right)\&CenterDot;B\left(m\right)\&rsqb;}_T={\mathrm{\&Sigma;}}_{k=K}^{n+m-2}{X}_k\&CenterDot;2^k,$ The cut position error of A ' (n) B (m) is its maximum is set to q ', q '=-(2 ^k-2 ^n-M);

So the logarithm of the signal to noise ratio of A ' (n) B (m) is expressed as:

Alternatively, export data carry out Gain tuning according to the figure place n-M that moves to left of data shift cells left to floating type, floating type exports data divided by 2 ^n-M.

Alternatively, e (j) has following statistical nature:

(a) stationary random sequence;

B () has nothing to do with the sequence participating in multiplying;

Uncorrelated between any two values of (c) e (j);

D () is be uniformly distributed in error range.

The invention has the beneficial effects as follows:

(1), while adc data sends into FPGA, synchronously carry out the identification of most significant digit number, execution efficiency is high;

(2) data cutout is reduced to greatest extent to the deterioration of digital intermediate frequency signal to noise ratio;

(3) data output is converted to floating type and significantly extends data representation scope, and ensures that the data processing gain of design is constant.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

Fig. 1 is existing digital medium-frequency signal processing procedure principle schematic;

Fig. 2 is digital intermediate frequency dynamic rage extension method principle schematic of the present invention.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.

In FPGA, integer data multiplying outputs data bits is wide equals two input data bit width sums, and when realizing multistage multiplying, bit wide increase can cause the consumption of rear class logical resource to increase substantially; Because the logical resource of FPGA is limited, therefore need to intercept the output data of every grade of multiplying.The data precision loss that a large amount of multiplying and data cutout bring makes the signal to noise ratio exporting data be less than the signal to noise ratio of input data.

The present invention reduces the deterioration of data cutout to digital intermediate frequency signal to noise ratio, thus expanding digital intermediate frequency dynamic range.

The principle of digital intermediate frequency dynamic rage extension method of the present invention as shown in Figure 2, except existing digital medium-frequency signal processing procedure, also comprises significance bit detecting unit, data shift cells left and exports data gain adjustment unit.

Performing step of the present invention is as follows:

Step (1), is that the integer ADC sampled data of n position sends into the RAM of FPGA simultaneously by one group of resolution, synchronously carries out data valid bit detection, can obtain most significant digit number, be designated as M when one group of ADC sampled data input is complete;

Step (2), the difference of n-M is sent into the arithmetic pipelining of FPGA, move to left each adc data successively n-M position in data shift cells left;

Data after moving to left are sent into digital intermediate frequency signal processing unit, in this element, except afterbody multiplying, are intercepted the output data of all integer data multiplyings by step (3);

Step (4), is converted to floating type by the data format of the output data of digital intermediate frequency signal processing unit from integer;

Step (5), exports data to floating type and carries out Gain tuning according to the figure place n-M that moves to left in data shift cells left, make the structure of structure shown in Fig. 2 and Fig. 1 have same gain.

The present invention can reduce the deterioration of data cutout to digital intermediate frequency signal to noise ratio, dynamic range expanded, and its principle is as follows:

If a sampled data is A (n)=a ₀2 ⁰+ a ₁2 ¹+ a ₂2 ²+ ... + a _n-22 ^n-2+ a _n-12 ^n-1, a _i∈ { 0,1 }, 0≤i≤n-1, a total n position, most significant digit number is M, and the n-M position that moves to left can retain computing number of significant digit to greatest extent, and the data after moving to left are designated as A ' (n).The binary data be multiplied with it is set to m position, is expressed as follows:

B (m)=b ₀2 ⁰+ b ₁2 ¹+ b ₂2 ²+ ... + b _m-22 ^m-2+ b _m-12 ^m-1, wherein b _i∈ { 0,1 }, 0≤i≤m-1.

Then A (n) with B (n) its coefficient matrix mutually multiplied is:

Because A (n) and the most significant digit of B (n) are M and m, therefore a respectively _m-1b _m-1=1, i.e. A (n) B (m)>=2 ^{m + m-2}.As M > m, A (n) can be expressed as follows with the product of B (n):

A(n)·B(m)＝a _M-1b _m-1·2 ^M+m-2+(a _M-1b _m-2+a _M-2b _m-1)·2 ^M+m-3+…

+(a _M-mb _m-1+a _M-m+1b _m-2+…+a _M-2b ₁+a _M-1b ₀·2 ^M-1

≤2 ^M-1·(2 ^m-1+2·2 ^m-2+3·2 ^m-3+…+m·2 ⁰)

＝2 ^M-1·(2 ^m+1-m-2)＜2 ^M+m

So have 2 ^m+m-2≤ A (n) B (m) < 2 ^m+m.

As M < m, A (n) can be expressed as follows with the product of B (n):

A(n)·B(m)＝a _M-1b _m-1·2 ^M+m-2+(a _M-1b _m-2+a _M-2b _m-1)·2 ^M+m-3+…

+(a ₀b _m-1+a ₁b _m-2+…+a _M-2b _m-M+1+a _M-1b _m-M)·2 ^M-2

≤2 ^m-1·(2 ^M-1+2·2 ^M-2+3·2 ^M-3+…+M·2 ⁰)

＝2 ^m-1·(2 ^M+1-M-2)＜2 ^M+m

So have 2 ^m+m-2≤ A (n) B (m) < 2 ^m+m.

Therefore, the highest significant position of A (n) B (m) is 2 ^m+m-2or 2 ^m+m-1.

Below with the highest significant position of A (n) B (m) for 2 ^m+m-2object of the present invention is described.

The result of A (n)-B (m) can be expressed as with [] _trepresent cut position process, if cut out low K position, then if E _tfor cut position error, then the cut position error of A (n) B (m) is $E_T={\&lsqb;A\left(n\right)\&CenterDot;B\left(m\right)\&rsqb;}_T-A\left(n\right)\&CenterDot;B\left(m\right)=-{\mathrm{\&Sigma;}}_{k=0}^{K-1}{X}_k\&CenterDot;2^k,$ Work as X _kwhen being 1, cut position error is maximum, now E _t=-(2 ^k-1), general 2 ^k> > 1, and make q=2 ^k, i.e.-q < E _t≤ 0.N number of n position sampled data is carried out multiplying and after intercepting, is generated N number of E in FPGA _tform and intercept error sequence, be set to e (j), j=0,1,2 ..., N-1.E (j) generally has following statistical nature:

(a) stationary random sequence;

B () has nothing to do with the sequence participating in multiplying;

C uncorrelated between any two values of () e (j), namely e (j) is white noise sequence;

D () is be uniformly distributed in error range.

So the probability density function of e (j) is

Its average is $m_e={\&Integral;}_{-q}^0\frac{1}{q}e\left(j\right)de\left(j\right)=-\frac{q}{2}=\frac{2^K}{2},$ Variance is ${\mathrm{\&sigma;}}_e^2={\&Integral;}_{-q}^0{\&lsqb;e\left(j\right)+\frac{q}{2}\&rsqb;}^2\frac{1}{q}de\left(j\right)=\frac{q^2}{12}=\frac{2^{2K}}{12}.$

If the power of A (n) B (m) is then the logarithm of the signal to noise ratio of A (n) B (m) is expressed as:

A (n) the sequence sequence behind n-M position that moves to left is A ' (n)=A (n) 2 ^n-M, the result of A ' (n) B (m) can be expressed as $A^{\&prime;}\left(n\right)\&CenterDot;B\left(m\right)={\mathrm{\&Sigma;}}_{k=n-M}^{n+m-2}{X}_k\&CenterDot;2^k,$ Cut out low K position, K > n-M, then ${\&lsqb;A^{\&prime;}\left(n\right)\&CenterDot;B\left(m\right)\&rsqb;}_T={\mathrm{\&Sigma;}}_{k=K}^{n+m-2}{X}_k\&CenterDot;2^k,$ The cut position error of A ' (n) B (m) is its maximum is set to q ', q '=-(2 ^k-2 ^n-M).So the logarithm of the signal to noise ratio of A ' (n) B (m) is expressed as:

Contrast 1. 2. formula, the figure place n-M that can move to left is larger, and the signal to noise ratio of multiplication output data affects less by truncated error.

Export data to floating type and carry out Gain tuning according to the figure place n-M that moves to left of data shift cells left, namely floating type exports data divided by 2 ^n-M, make the system of Fig. 2 and the system of Fig. 1 have same gain.This is because:

A ' (n) B (m)=A (n) 2 ^n-Mb (m)=A (n) B (m) 2 ^n-M, therefore

Digital intermediate frequency dynamic rage extension method of the present invention, while adc data sends into FPGA, synchronously carry out the identification of most significant digit number, execution efficiency is high; Reduce data cutout to greatest extent to the deterioration of digital intermediate frequency signal to noise ratio; Data output is converted to floating type and significantly extends data representation scope, and ensures that the data processing gain of design is constant.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (4)

1. a digital intermediate frequency dynamic rage extension method, is characterized in that, also comprise significance bit detecting unit, data shift cells left and export data gain adjustment unit, performing step is as follows:

Step (1), is that the integer ADC sampled data of n position sends into the RAM of FPGA simultaneously by one group of resolution, synchronously carries out data valid bit detection, obtain most significant digit number, be designated as M when one group of ADC sampled data input is complete;

Step (2), the difference of n-M is sent into the arithmetic pipelining of FPGA, move to left each adc data successively n-M position in data shift cells left;

Data after moving to left are sent into digital intermediate frequency signal processing unit, in this element, except afterbody multiplying, are intercepted the output data of all integer data multiplyings by step (3);

Step (4), is converted to floating type by the data format of the output data of digital intermediate frequency signal processing unit from integer;

Step (5), exports data to floating type and carries out Gain tuning according to the figure place n-M that moves to left in data shift cells left.

2. digital intermediate frequency dynamic rage extension method as claimed in claim 1, is characterized in that,

If a sampled data is A (n)=a ₀2 ⁰+ a ₁2 ¹+ a ₂2 ²+ ... + a _n-22 ^n-2+ a _n-12 ^n-1, a _i{ most significant digit number is M to ∈, and the n-M position that moves to left retains computing number of significant digit to greatest extent, and the data after moving to left are designated as A ' (n) for 0,1}, 0≤i≤n-1, a total n position;

The binary data be multiplied with it is set to m position, is expressed as follows:

B (m)=b ₀2 ⁰+ b ₁2 ¹+ b ₂2 ²+ ... + b _m-22 ^m-2+ b _m-12 ^m-1, wherein b _i∈ { 0,1}, 0≤i≤m-1;

Then A (n) with B (n) its coefficient matrix mutually multiplied is:

$\left[\begin{array}{cccccc}{a}_0{b}_0& a_0{b}_1& a_0{b}_2& ...& a_0{b}_{m-2}& a_0{b}_{m-1}\\ a_1{b}_0& a_1{b}_1& a_1{b}_2& ...& a_1{b}_{m-2}& a_1{b}_{m-1}\\ a_2{b}_0& a_2{b}_1& a_2{b}_2& ...& a_2{b}_{m-2}& a_2{b}_{m-1}\\ & & & \&CenterDot;& & \\ & & & \&CenterDot;& & \\ & & & \&CenterDot;& & \\ a_{M-1}{b}_0& a_{M-1}{b}_1& a_{M-1}{b}_2& ...& a_{M-1}{b}_{m-2}& a_{M-1}{b}_{m-1}\\ & & & 0& & \end{array}\right]$

Because A (n) and the most significant digit of B (n) are M and m, therefore a respectively _m-1b _m-1=1, A (n) B (m)>=2 ^m+m-2;

As M > m, A (n) is as follows with the product representation of B (n):

A(n)·B(m)＝a _M-1b _m-1·2 ^M+m-2+(a _M-1b _m-2+a _M-2b _m-1)·2 ^M+m-3+…

+(a _M-mb _m-1+a _M-m+1b _m-2+…+a _M-2b ₁+a _M-1b ₀)·2 ^M-1

≤2 ^M-1·(2 ^m-1+2·2 ^m-2+3·2 ^m-3+…+m·2 ⁰)

＝2 ^M-1·(2 ^m+1-m-2)＜2 ^M+m

So have 2 ^m+m-2≤ A (n) B (m) < 2 ^m+m;

As M < m, A (n) is as follows with the product representation of B (n):

A(n)·B(m)＝a _M-1b _m-1·2 ^M+m-2+(a _M-1b _m-2+a _M-2b _m-1)·2 ^M+m-3+…

+(a ₀b _m-1+a ₁b _m-2+…+a _M-2b _m-M+1+a _M-1b _m-M)·2 ^M-1

≤2 ^m-1·(2 ^M-1+2·2 ^M-2+3·2 ^M-3+…+M·2 ⁰)

＝2 ^m-1·(2 ^M+1-M-2)＜2 ^M+m

So have 2 ^m+m-2≤ A (n) B (m) < 2 ^m+m, therefore, the highest significant position of A (n) B (m) is 2 ^m+m-2or 2 ^m+m-1;

When the highest significant position of A (n) B (m) is 2 ^m+m-2time:

The result of A (n) B (m) is expressed as $A\left(n\right)\&CenterDot;B\left(m\right)={\mathrm{\&Sigma;}}_{k=0}^{M+m-2}{X}_k\&CenterDot;2^k,X_k\&Element;\{0,1\};$

With [] _trepresent cut position process, if cut out low K position, then

If E _tfor cut position error, then the cut position error of A (n) B (m) is $E_T={\&lsqb;A\left(n\right)\&CenterDot;B\left(m\right)\&rsqb;}_T-A\left(n\right)\&CenterDot;B\left(m\right)=-{\mathrm{\&Sigma;}}_{k=0}^{K-1}{X}_k\&CenterDot;2^k,$ Work as X _kwhen being 1, cut position error is maximum, now E _t=-(2 ^k-1), 2 ^k> > 1, and make q=2 ^k, i.e.-q < E _t≤ 0;

N number of n position sampled data is carried out multiplying and after intercepting, is generated N number of E in FPGA _tform and intercept error sequence, be set to e (j), j=0,1,2 ..., N-1;

So the probability density function of e (j) is

Its average is $m_e={\&Integral;}_{-q}^0\frac{1}{q}e\left(j\right)de\left(j\right)=-\frac{q}{2}=\frac{2^K}{2},$ Variance is ${\mathrm{\&sigma;}}_e^2={\&Integral;}_{-q}^0{\&lsqb;e\left(j\right)+\frac{q}{2}\&rsqb;}^2\frac{1}{q}de\left(j\right)=\frac{q^2}{12}=\frac{2^{2K}}{12};$

If the power of A (n) B (m) is then the logarithm of the signal to noise ratio of A (n) B (m) is expressed as:

$\frac{S}{N}=10{\log }_{10}\left(\frac{{\mathrm{\&sigma;}}_{AB}^2}{{\mathrm{\&sigma;}}_e^2}\right)=10.79-20{\log }_{10}{2}^K+10{\log }_{10}{\mathrm{\&sigma;}}_{AB}^2$ ………①

A (n) the sequence sequence behind n-M position that moves to left is A ' (n)=A (n) 2 ^n-M, the result of A ' (n) B (m) is expressed as $A^{\&prime;}\left(n\right)\&CenterDot;B\left(m\right)={\mathrm{\&Sigma;}}_{k=m-M}^{n+m-2}{X}_k\&CenterDot;2^k,$ Cut out low K position, K > n-M, then ${\&lsqb;A^{\&prime;}\left(n\right)\&CenterDot;B\left(m\right)\&rsqb;}_T={\mathrm{\&Sigma;}}_{k=K}^{n+m-2}{X}_k\&CenterDot;2^k,$ The cut position error of A ' (n) B (m) is its maximum is set to q ', q '=-(2 ^k-2 ^n-M);

So the logarithm of the signal to noise ratio of A ' (n) B (m) is expressed as:

$\frac{S}{N^{\&prime;}}=10{\log }_{10}\left(\frac{{\mathrm{\&sigma;}}_{AB}^2}{{{\mathrm{\&sigma;}}^{\&prime;}}_e^2}\right)=10.79-20{\log }_{10}(2^K-2^{n-M})+10{\log }_{10}{\mathrm{\&sigma;}}_{AB}^2$ ………②。

3. digital intermediate frequency dynamic rage extension method as claimed in claim 2, is characterized in that, exports data carry out Gain tuning according to the figure place n-M that moves to left of data shift cells left to floating type, and floating type exports data divided by 2 ^n-M.

4. digital intermediate frequency dynamic rage extension method as claimed in claim 2, it is characterized in that, e (j) has following statistical nature:

(a) stationary random sequence;

B () has nothing to do with the sequence participating in multiplying;

Uncorrelated between any two values of (c) e (j);

D () is be uniformly distributed in error range.