CN105450182A - Power-on POP sound inhibiting circuit for D-type power amplification chip - Google Patents
Power-on POP sound inhibiting circuit for D-type power amplification chip Download PDFInfo
- Publication number
- CN105450182A CN105450182A CN201610013438.2A CN201610013438A CN105450182A CN 105450182 A CN105450182 A CN 105450182A CN 201610013438 A CN201610013438 A CN 201610013438A CN 105450182 A CN105450182 A CN 105450182A
- Authority
- CN
- China
- Prior art keywords
- electric capacity
- nmos tube
- circuit branch
- preamplifier
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a power-on POP sound inhibiting circuit for a D-type power amplification chip. The power-on POP sound inhibiting circuit comprises a first circuit branch and a second circuit branch which are symmetrical mutually. Each circuit branch comprises a three-input NAND gate, a comparator, a POMS (P-channel metal oxide semiconductor) tube, three NMOS (N-channel metal oxide semiconductor) tubes and three phase inverters. The first and second circuit branches are connected to the positive phase and inverse phase input terminals of a pre-amplifier of the D-type power amplification chip and between a pole plate of a first capacitance and a pole plate of a second capacitance, detect whether voltages on the pole plate of the first capacitance and on the pole plate of the second capacitance are lower than a common mode voltage of the pre-amplifier under the action of a starting signal and a control signal, and enable a power supply voltage to charge the first and second capacitances when a detection result is yes. According to the power-on POP sound inhibiting circuit for the D-type power amplification chip, which is disclosed by the invention, charging of a large current on input capacitances can be achieved in the power-on stage of the D-type power amplification chip; and even though starting time is short, power-on POP sound also can be well inhibited.
Description
Technical field
The present invention relates to category D amplifier chip, particularly relate to a kind of POP sound that powers on for category D amplifier chip and suppress circuit.
Background technology
As shown in Figure 1, category D amplifier chip comprises preamplifier PRE and two input capacitance, the C-of the C+ being namely connected to the normal phase input end of preamplifier PRE and the inverting input being connected to preamplifier PRE, it has a process of charging to input capacitance C+, C-at power up phase, if the terminal voltage of input capacitance C+, C-can not be charged to the common-mode voltage of preamplifier PRE in start-up time Ton, just likely produce POP sound (" puff puff " sound sent when namely the audio system such as earphone or loudspeaker is just opened).
The POP sound that powers on for category D amplifier chip of prior art suppresses circuit as shown in Figure 1, comprise the circuit branch that two-way is mutually symmetrical, they access at the normal phase input end of preamplifier PRE, inverting input and between electric capacity C+, C-respectively, each circuit branch comprises the resistance and NMOS tube that connect successively, and enabling signal Ton acts on the grid of the NMOS tube of each circuit branch.In the prior art, general is all that (namely enabling signal Ton is high level in start-up time, Ton=1) in, by preamplifier PRE being connected into unit gain, input capacitance C+, C-are charged, because in charging process, IN1+ is the common-mode voltage of preamplifier PRE, charging current is less, therefore will reduce POP sound, is all generally the mode by increasing Ton start-up time.But such method is in some conditional occasions of maximum to Ton start-up time, just inapplicable.
Therefore, those skilled in the art is devoted to develop a kind of POP sound that powers on for category D amplifier chip and suppresses circuit, also can well suppress the POP sound that powers on when start-up time is shorter.
Summary of the invention
For achieving the above object, the invention provides a kind of POP sound that powers on for category D amplifier chip and suppress circuit, described category D amplifier chip comprises preamplifier, second electric capacity of the first electric capacity being connected to the normal phase input end of described preamplifier and the inverting input being connected to described preamplifier, it is characterized in that, the POP sound that powers on for category D amplifier chip suppresses circuit to comprise the first circuit branch between normal phase input end and described first electric capacity being connected to described preamplifier and the second circuit branch road be connected between the inverting input of described preamplifier and described second electric capacity, described first circuit branch and described second point road branch road are mutually symmetrical,
Described first circuit branch is connected with supply voltage, comprise the first switching tube between normal phase input end and described first electric capacity being connected to described preamplifier, described first switching tube accepts enabling signal from the external world whether to control conducting between the normal phase input end of described preamplifier and described first electric capacity; Described first circuit branch also accepts control signal from the external world the terminal voltage of described first electric capacity and the common-mode voltage of described preamplifier to be compared under the control of said control signal, and obtain comparative result be the terminal voltage of described first electric capacity lower than making described supply voltage to described first capacitor charging during described common-mode voltage, and;
Described second circuit branch road is connected with described supply voltage, comprise the second switch pipe between inverting input and described second electric capacity being connected to described preamplifier, described second switch pipe accepts described enabling signal whether to control conducting between the inverting input of described preamplifier and described second electric capacity; Described second circuit branch road also accepts described control signal the terminal voltage of described second electric capacity and the described common-mode voltage of described preamplifier to be compared under the control of said control signal, and is that the terminal voltage of described second electric capacity is lower than making described supply voltage to described second capacitor charging during described common-mode voltage at the comparative result obtained.
Further, described first switching tube is the first NMOS tube, and the source electrode of described first NMOS tube is connected to the normal phase input end of described preamplifier, and drain electrode is connected to a pole plate of described first electric capacity; Described second switch pipe is the second NMOS tube, and the source electrode of described second NMOS tube is connected to the inverting input of described preamplifier, and drain electrode is connected to a pole plate of described second electric capacity; Described enabling signal acts on the grid of described first NMOS tube and described second NMOS tube;
The terminal voltage of described first electric capacity is the voltage on the described pole plate of described first electric capacity, and the terminal voltage of described second electric capacity is the voltage on the described pole plate of described second electric capacity.
Further, described control signal is clock signal; When to receive described clock signal be high level to first, second circuit branch described, the common-mode voltage of the terminal voltage of first, second electric capacity described and described preamplifier is compared; When first, second circuit branch described receive described clock signal be low level and the comparative result obtained before be the terminal voltage of first, second electric capacity described lower than described common-mode voltage time, make described supply voltage to first, second capacitor charging described.
Further, described first circuit branch also comprises the first PMOS, the source electrode of described first PMOS is connected to described supply voltage, to the charging of described first electric capacity whether drain electrode is connected to the described pole plate of described first electric capacity, control described supply voltage by the break-make of described first PMOS; Described second circuit branch road also comprises the second PMOS, and the source electrode of described second PMOS is connected to described supply voltage, and to the charging of described second electric capacity whether to control described supply voltage between described second electric capacity.
Further, described first circuit branch also comprises the first comparator and the 3rd NMOS tube, the inverting input of described first comparator of described common-mode voltage input, whether to control conducting between the two between the normal phase input end that described 3rd NMOS tube is connected to described first electric capacity and described first comparator; Described second circuit branch road also comprises the second comparator and the 4th NMOS tube, the inverting input of described second comparator of described common-mode voltage input, whether to control conducting between the two between the normal phase input end that described 4th NMOS tube is connected to described second electric capacity and described second comparator.
Further, described first circuit branch also comprises the first NAND gate of three inputs, the first inverter and the 3rd inverter, the first input end of described first NAND gate of described clock signal input, the output of described first comparator is connected to the second input of described first NAND gate through described first inverter, described enabling signal is through the 3rd input of described first NAND gate of described 3rd inverter input, and the output of described first NAND gate is connected to the grid of described first PMOS and the grid of described 3rd NMOS tube; The source electrode of described 3rd NMOS tube is connected to the positive input of described first comparator, and drain electrode is connected to the described pole plate of described first electric capacity;
Described second circuit branch road also comprises the second NAND gate of three inputs, the second inverter and the 4th inverter, the first input end of described second NAND gate of described clock signal input, the output of described second comparator is connected to the second input of described second NAND gate through described second inverter, described enabling signal is through the 3rd input of described second NAND gate of described 4th inverter input, and the output of described second NAND gate is connected to the grid of described second PMOS and the grid of described 4th NMOS tube; The source electrode of described 4th NMOS tube is connected to the positive input of described second comparator, and drain electrode is connected to the described pole plate of described second electric capacity.
Further, described first circuit branch also comprises the 5th inverter and the 5th NMOS tube, the output of described first NAND gate is connected to the grid of described 5th NMOS tube through described 5th inverter, the drain electrode of described 5th NMOS tube is connected to the positive input of described first comparator, the source ground of described 5th NMOS tube; Described second circuit branch road also comprises hex inverter and the 6th NMOS tube, the output of described second NAND gate is connected to the grid of described 6th NMOS tube through described hex inverter, the drain electrode of described 6th NMOS tube is connected to the positive input of described second comparator, the source ground of described 6th NMOS tube.
In better embodiment of the present invention, provide a kind of POP sound that powers on for category D amplifier chip and suppress circuit, comprise the first circuit branch and second circuit branch road that are mutually symmetrical, each circuit branch all comprises the NAND gate of one three input, a comparator, POMS pipe, three NMOS tube and three inverters.First circuit branch is connected between the normal phase input end of the preamplifier of category D amplifier chip and a pole plate of the first electric capacity, under the effect of enabling signal and control signal, detect voltage on this pole plate of the first electric capacity whether lower than the common-mode voltage of preamplifier, and make when testing result is for being supply voltage to the first capacitor charging; Second circuit branch road is connected between the inverting input of the preamplifier of category D amplifier chip and a pole plate of the second electric capacity, under the effect of enabling signal and control signal, detect voltage on this pole plate of the second electric capacity whether lower than the common-mode voltage of preamplifier, and make when testing result is for being supply voltage to the second capacitor charging.Thus, the POP sound suppression circuit that powers on for category D amplifier chip of the present invention can realize big current at category D amplifier chip power up phase and charge to input capacitance (i.e. first, second electric capacity), like this, even if shortlyer also can well suppress the POP sound that powers on start-up time.
Be described further below with reference to the technique effect of accompanying drawing to design of the present invention, concrete structure and generation, to understand object of the present invention, characteristic sum effect fully.
Accompanying drawing explanation
The POP sound that powers on for category D amplifier chip that Fig. 1 shows prior art suppresses circuit.
Fig. 2 shows the POP sound that powers on for category D amplifier chip of the present invention and suppresses circuit.
Embodiment
As shown in Figure 2, the POP sound suppression circuit that powers on for category D amplifier chip of the present invention comprises two symmetrical circuit branch, i.e. the first circuit branch 10 and second circuit branch road 20.Wherein, first circuit branch 10 is connected between the normal phase input end of the preamplifier PRE of category D amplifier chip and a pole plate of the first electric capacity C1, second circuit branch road 20 is connected between the inverting input of the preamplifier PRE of category D amplifier chip and a pole plate of the second electric capacity C2, and the first electric capacity C1 and the second electric capacity C2 is the input capacitance of this category D amplifier chip.
First circuit branch 10 and second circuit branch road 20 all comprise the NAND gate of one three input, a comparator, POMS pipe, three NMOS tube and three inverters, NAND gate wherein in the first circuit branch 10 is the first NAND gate, comparator is the first comparator CMP1, PMOS is the first PMOS MP1, three NMOS tube are the first, the 3rd and the 5th NMOS tube MN1, MN3 and MN5, and three inverters are the first, the 3rd and the 5th inverters; NAND gate in second circuit branch road 20 is the second NAND gate, comparator is the second comparator CMP2, PMOS is the second PMOS MP2, and three NMOS tube are the second, the 4th and the 6th NMOS tube MN2, MN4 and MN6, and three inverters are second, the 4th and hex inverter.Because the first circuit branch 10 and second circuit branch road 20 are two circuit be mutually symmetrical, below for the first circuit branch 10, the annexation of wherein each element is described.
As shown in Figure 2, in the first circuit branch 10, the source electrode of the first PMOS MP1 is connected to supply voltage, drains to be connected with this pole plate of the first electric capacity C1, and grid is connected to the output of the first NAND gate; The source electrode of the first NMOS tube MN1 is connected to the normal phase input end of preamplifier PRE, drains to be connected with this pole plate of the first electric capacity C1, and grid is used for accepting enabling signal Ton; The source electrode of the 3rd NMOS tube MN3 is connected to the normal phase input end of the first comparator CMP1, drains to be connected with this pole plate of the first electric capacity C1, and grid is connected to the output of the first NAND gate; The source ground of the 5th NMOS tube MN5, drain electrode is connected to the normal phase input end of the first comparator, and grid is connected with the output of the 5th inverter; The reverse input end of the first comparator CMP1 is for accepting the common-mode voltage PRE_COMMON of preamplifier, the output of the first comparator CMP1 is connected with the input of the first inverter, and the output of the first inverter is connected to the second input of the first NAND gate; The input of the second inverter accepts above-mentioned enabling signal Ton, and output is connected to the 3rd input of the first NAND gate; The first input end of the first NAND gate is for accepting the control signal from the external world, and in the present embodiment, this control signal is clock signal clk.
In second circuit branch road 20, the connected mode of each element is identical with the situation of the first above-mentioned circuit branch 10, just the drain electrode of the second PMOS MP2, the second NMOS tube MN2 wherein and the 4th NMOS tube MN4 is connected to this pole plate of the second electric capacity C2, and the source electrode of the second PMOS MP2 is connected to supply voltage.Be not repeated herein.
Above-mentioned enabling signal Ton is exactly the enabling signal to category D amplifier chip, and when it is low level (representing with 0 below), category D amplifier chip is activated, and starts power up.The time of its effect is exactly start-up time.Above-mentioned control signal adopts clock signal clk, and it is alternately high level (representing with 1 below) and low level (representing with 0 below).Control signal is used for the break-make of each metal-oxide-semiconductor in control first circuit branch 10 and second circuit branch road 20, thus the first electric capacity C1 and the terminal voltage of the second electric capacity C2 and the common-mode voltage of preamplifier can be realized to compare, and correspondingly control supply voltage the first electric capacity C1 and the second electric capacity C2 is charged.So can know, also other forms of control signal can be adopted in other embodiments of the invention.
Below describe in the present embodiment, the POP sound that powers on for category D amplifier chip of the present invention suppresses the course of work of circuit, equally because the first circuit branch 10 and second circuit branch road 20 are two circuit be mutually symmetrical, be described for the first circuit branch 10 below:
Within start-up time, enabling signal Ton=0, now the first NMOS tube MN1 pipe turns off, the voltage IN1+ of the first PMOS MP1 drain electrode place and the voltage IN3+ at preamplifier PRE normal phase input end place disconnects, and the POP sound that powers on for category D amplifier chip of the present invention suppresses the first circuit branch 10 of circuit to be started working; In like manner second circuit branch road 20 is also started working.
As control signal CLK=0, the output of the first NAND gate is 1 (high level), first PMOS MP1 turns off, 3rd NMOS tube MN3 conducting, 5th NMOS tube MN5 turns off, have the voltage IN2+=IN1+=IN+ at the first comparator normal phase input end place thus, wherein IN+ is the voltage (terminal voltage of the first electric capacity C1) on first this pole plate of electric capacity C1.Now enter detection-phase, compare by the terminal voltage IN+ of the first electric capacity C1 and the common-mode voltage PRE_COMMON of preamplifier, when obtain comparative result be terminal voltage IN+ lower than common-mode voltage PRE_COMMON time, the output of the first comparator CMP1 is 0.
As control signal CLK=1, if the comparative result that detection-phase before (stage of a CLK=0 namely before this CLK=1) obtains is that the terminal voltage IN+ of the first electric capacity C1 is lower than common-mode voltage PRE_COMMON, then the output of the first NAND gate is 0, first PMOS MP1 conducting, 3rd NMOS tube MN3 turns off, 5th NMOS tube MN5 conducting, the voltage IN2+ at the first comparator normal phase input end place pulled down to ground, and the output of the first comparator CMP1 is 0.Now enter the charging stage, because the voltage IN1+ of the first PMOS drain electrode place is directly pulled to supply voltage, charging current is comparatively large, and the terminal voltage IN+ of the first electric capacity C1 faster can be charged to common-mode voltage PRE_COMMON.
Because control signal CLK is replace 0 and 1, therefore under its effect, first circuit branch 10 repeats the above-mentioned process alternately detecting and charge, until the terminal voltage IN+ that the comparative result obtained at some detection-phases is the first electric capacity C1 is not less than common-mode voltage PRE_COMMON, at this moment the first comparator CMP1 exports 1, the charging of the first electric capacity C1 is stopped, first circuit branch 10 will be in detecting pattern always, until when the terminal voltage IN+ of the first electric capacity C1 again being detected lower than common-mode voltage PRE_COMMON, then recover the charging to the first electric capacity C1.So just can ensure that the terminal voltage IN+ of the first electric capacity C1 within start-up time follows common-mode voltage PRE_COMMON always, and it is shorter to make the terminal voltage IN+ of the first electric capacity C1 follow the required time of common-mode voltage PRE_COMMON.
The situation of second circuit branch road 20 is similar, just the terminal voltage IN-of the second electric capacity C2 is the voltage on this pole plate of the second electric capacity C2, the voltage of the second PMOS MP2 drain electrode place is IN1-, the voltage at the second comparator normal phase input end place is IN2-, the voltage IN3-at preamplifier PRE inverting input place.Be not repeated herein.
More than describe preferred embodiment of the present invention in detail.Should be appreciated that those of ordinary skill in the art just design according to the present invention can make many modifications and variations without the need to creative work.Therefore, all those skilled in the art, all should by the determined protection range of claims under this invention's idea on the basis of existing technology by the available technical scheme of logical analysis, reasoning, or a limited experiment.
Claims (7)
1. one kind is suppressed circuit for the POP sound that powers on of category D amplifier chip, described category D amplifier chip comprises preamplifier, be connected to the first electric capacity of the normal phase input end of described preamplifier and be connected to second electric capacity of inverting input of described preamplifier, it is characterized in that, the POP sound that powers on for category D amplifier chip suppresses circuit to comprise the first circuit branch between normal phase input end and described first electric capacity being connected to described preamplifier and the second circuit branch road be connected between the inverting input of described preamplifier and described second electric capacity; Described first circuit branch and described second point road branch road are mutually symmetrical;
Described first circuit branch is connected with supply voltage, comprise the first switching tube between normal phase input end and described first electric capacity being connected to described preamplifier, described first switching tube accepts enabling signal from the external world whether to control conducting between the normal phase input end of described preamplifier and described first electric capacity; Described first circuit branch also accepts control signal from the external world the terminal voltage of described first electric capacity and the common-mode voltage of described preamplifier to be compared under the control of said control signal, and obtain comparative result be the terminal voltage of described first electric capacity lower than making described supply voltage to described first capacitor charging during described common-mode voltage, and;
Described second circuit branch road is connected with described supply voltage, comprise the second switch pipe between inverting input and described second electric capacity being connected to described preamplifier, described second switch pipe accepts described enabling signal whether to control conducting between the inverting input of described preamplifier and described second electric capacity; Described second circuit branch road also accepts described control signal the terminal voltage of described second electric capacity and the described common-mode voltage of described preamplifier to be compared under the control of said control signal, and is that the terminal voltage of described second electric capacity is lower than making described supply voltage to described second capacitor charging during described common-mode voltage at the comparative result obtained.
2. suppress circuit for the POP sound that powers on of category D amplifier chip as claimed in claim 1, wherein said first switching tube is the first NMOS tube, the source electrode of described first NMOS tube is connected to the normal phase input end of described preamplifier, and drain electrode is connected to a pole plate of described first electric capacity; Described second switch pipe is the second NMOS tube, and the source electrode of described second NMOS tube is connected to the inverting input of described preamplifier, and drain electrode is connected to a pole plate of described second electric capacity; Described enabling signal acts on the grid of described first NMOS tube and described second NMOS tube;
The terminal voltage of described first electric capacity is the voltage on the described pole plate of described first electric capacity, and the terminal voltage of described second electric capacity is the voltage on the described pole plate of described second electric capacity.
3. suppress circuit for the POP sound that powers on of category D amplifier chip as claimed in claim 2, wherein said control signal is clock signal; When to receive described clock signal be high level to first, second circuit branch described, the common-mode voltage of the terminal voltage of first, second electric capacity described and described preamplifier is compared; When first, second circuit branch described receive described clock signal be low level and the comparative result obtained before be the terminal voltage of first, second electric capacity described lower than described common-mode voltage time, make described supply voltage to first, second capacitor charging described.
4. suppress circuit for the POP sound that powers on of category D amplifier chip as claimed in claim 3, wherein said first circuit branch also comprises the first PMOS, the source electrode of described first PMOS is connected to described supply voltage, to the charging of described first electric capacity whether drain electrode is connected to the described pole plate of described first electric capacity, control described supply voltage by the break-make of described first PMOS; Described second circuit branch road also comprises the second PMOS, and the source electrode of described second PMOS is connected to described supply voltage, and to the charging of described second electric capacity whether to control described supply voltage between described second electric capacity.
5. suppress circuit for the POP sound that powers on of category D amplifier chip as claimed in claim 4, wherein said first circuit branch also comprises the first comparator and the 3rd NMOS tube, the inverting input of described first comparator of described common-mode voltage input, whether to control conducting between the two between the normal phase input end that described 3rd NMOS tube is connected to described first electric capacity and described first comparator; Described second circuit branch road also comprises the second comparator and the 4th NMOS tube, the inverting input of described second comparator of described common-mode voltage input, whether to control conducting between the two between the normal phase input end that described 4th NMOS tube is connected to described second electric capacity and described second comparator.
6. suppress circuit for the POP sound that powers on of category D amplifier chip as claimed in claim 5, wherein said first circuit branch also comprises the first NAND gate of three inputs, first inverter and the 3rd inverter, the first input end of described first NAND gate of described clock signal input, the output of described first comparator is connected to the second input of described first NAND gate through described first inverter, described enabling signal is through the 3rd input of described first NAND gate of described 3rd inverter input, the output of described first NAND gate is connected to the grid of described first PMOS and the grid of described 3rd NMOS tube, the source electrode of described 3rd NMOS tube is connected to the positive input of described first comparator, and drain electrode is connected to the described pole plate of described first electric capacity,
Described second circuit branch road also comprises the second NAND gate of three inputs, the second inverter and the 4th inverter, the first input end of described second NAND gate of described clock signal input, the output of described second comparator is connected to the second input of described second NAND gate through described second inverter, described enabling signal is through the 3rd input of described second NAND gate of described 4th inverter input, and the output of described second NAND gate is connected to the grid of described second PMOS and the grid of described 4th NMOS tube; The source electrode of described 4th NMOS tube is connected to the positive input of described second comparator, and drain electrode is connected to the described pole plate of described second electric capacity.
7. suppress circuit for the POP sound that powers on of category D amplifier chip as claimed in claim 6, wherein said first circuit branch also comprises the 5th inverter and the 5th NMOS tube, the output of described first NAND gate is connected to the grid of described 5th NMOS tube through described 5th inverter, the drain electrode of described 5th NMOS tube is connected to the positive input of described first comparator, the source ground of described 5th NMOS tube; Described second circuit branch road also comprises hex inverter and the 6th NMOS tube, the output of described second NAND gate is connected to the grid of described 6th NMOS tube through described hex inverter, the drain electrode of described 6th NMOS tube is connected to the positive input of described second comparator, the source ground of described 6th NMOS tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610013438.2A CN105450182B (en) | 2016-01-08 | 2016-01-08 | POP sound suppression circuits are powered on for category D amplifier chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610013438.2A CN105450182B (en) | 2016-01-08 | 2016-01-08 | POP sound suppression circuits are powered on for category D amplifier chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105450182A true CN105450182A (en) | 2016-03-30 |
| CN105450182B CN105450182B (en) | 2018-06-22 |
Family
ID=55560048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610013438.2A Active CN105450182B (en) | 2016-01-08 | 2016-01-08 | POP sound suppression circuits are powered on for category D amplifier chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105450182B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040222845A1 (en) * | 2003-05-10 | 2004-11-11 | Samsung Electronics Co., Ltd. | Class-D power amplifier capable of eliminating excessive response phenomenon when returning to a steady state from an abnormal state and an amplification method thereof |
| CN102801390A (en) * | 2012-09-07 | 2012-11-28 | 电子科技大学 | POP noise suppression circuit in D audio frequency amplifier |
| CN105119574A (en) * | 2015-08-20 | 2015-12-02 | 深圳创维－Rgb电子有限公司 | D-type power amplification circuit with POP noise suppression |
-
2016
- 2016-01-08 CN CN201610013438.2A patent/CN105450182B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040222845A1 (en) * | 2003-05-10 | 2004-11-11 | Samsung Electronics Co., Ltd. | Class-D power amplifier capable of eliminating excessive response phenomenon when returning to a steady state from an abnormal state and an amplification method thereof |
| CN102801390A (en) * | 2012-09-07 | 2012-11-28 | 电子科技大学 | POP noise suppression circuit in D audio frequency amplifier |
| CN105119574A (en) * | 2015-08-20 | 2015-12-02 | 深圳创维－Rgb电子有限公司 | D-type power amplification circuit with POP noise suppression |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105450182B (en) | 2018-06-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8957706B2 (en) | Dynamic comparator with equalization function | |
| CN102025263B (en) | Power supply starting detection circuit | |
| CN103956981B (en) | A kind of operation amplifier circuit eliminating DC offset voltage | |
| CN105915207B (en) | A kind of level shift circuit | |
| CN103475352A (en) | Detection circuit of capacitor touch key | |
| CN106374745A (en) | Single-inductor dual-path output DC-DC boosting converter based on voltage intermodulation suppression | |
| CN103178820B (en) | Electrify restoration circuit | |
| CN101719757A (en) | Over-current protection circuit of power amplifier and implementing method | |
| CN105185404A (en) | Charge transfer type sense amplifier | |
| CN108282083B (en) | Hybrid structure charge pump circuit | |
| CN102496988A (en) | Battery control circuit, system and method | |
| CN102999081B (en) | Current mirror circuit | |
| CN102130681B (en) | A kind of differential phase lock loop | |
| CN104205650A (en) | Inverter-and-switched-capacitor-based squelch detector apparatus and method | |
| CN102983825A (en) | Category D amplifier chip | |
| CN103616924B (en) | Sensor circuit | |
| CN105450182A (en) | Power-on POP sound inhibiting circuit for D-type power amplification chip | |
| CN108233701A (en) | A kind of buck voltage conversion circuit | |
| CN102006018B (en) | Opening control circuit used for AB class audio amplifier | |
| CN103051289A (en) | Preliminary amplifier with low clock crosstalk, dynamic comparator and circuit | |
| CN110380710A (en) | A kind of waveform convertion circuit of double Schmidt's structures | |
| CN104919703A (en) | Single-ended high voltage input-capable comparator circuit | |
| CN115051694A (en) | Dynamic comparator and chip | |
| CN210444203U (en) | Three-phase motor drive circuit | |
| CN110417383A (en) | Comparator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |