CN105448968B - Method for manufacturing fin field effect transistor - Google Patents
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- CN105448968B CN105448968B CN201510662851.7A CN201510662851A CN105448968B CN 105448968 B CN105448968 B CN 105448968B CN 201510662851 A CN201510662851 A CN 201510662851A CN 105448968 B CN105448968 B CN 105448968B
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 230000005669 field effect Effects 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 230000002093 peripheral effect Effects 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
Abstract
The invention provides a method for manufacturing a fin field effect transistor, which comprises the following steps: providing a semiconductor substrate, wherein at least one fin-shaped structure and a dielectric layer positioned around the fin-shaped structure are formed on the semiconductor substrate; etching partial dielectric layers on two sides of the fin-shaped structure to form grooves on two sides of the fin-shaped structure; filling the gate layer; etching the gate layer to form a gate structure covering the bottom of the groove and the surface of the fin-shaped structure between the grooves, wherein the gate structure is in an inverted U shape; the length of the upper part of the grid structure of the fin field effect transistor along the channel direction is defined by grid etching; the length of the lower portion of the gate structure of the fin field effect transistor along the channel direction is defined by a groove.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a method for manufacturing a fin field effect transistor.
Background
Since the 21 st century, the semiconductor process technology has been rapidly developed, the process has been developed to a node below 40nm, and the mass production of 28nm node process has been mature in the field of application to central processing units and image processors. In the process of developing the process below the 20nm node, the traditional 2D planar transistor structure has the defects of performance and process, so that Intel, TSMC and Samsung successively propose that the 16nm and 14nm process nodes adopt fin field effect transistors (FinFet) with 3D structures, and longer effective channel length is realized in the same physical length, thereby greatly improving the performance of the chip.
Referring to fig. 1 to 4, fig. 1 to 4 are schematic structural diagrams illustrating steps of fabricating a fin field effect transistor in the prior art. In the prior art, a substrate 100 is provided, a fin structure 110 is formed on the substrate 100, a first dielectric layer 200 covers the fin structure 110, the upper surface of the first dielectric layer 200 is flush with the upper surface of the fin structure 110, in fig. 2 to 4, the first dielectric layers 200 on two sides of the fin structure 110 are etched to form a groove 300 extending in the Y direction, a gate layer 400 is laid, the gate layer 400 covers the first dielectric layer 200 and the groove 300, and the gate layer 400 is etched to form a gate structure 410 of a fin field effect transistor; in the prior art, the groove 200 extends to the fin-shaped structure, the shape and the range are large, the gate layer 400 needs to be etched to the bottom of the groove 300 in the process of forming the gate structure 410 by etching, the continuous gate layer 400 is broken immediately, the required process difficulty is high, the etching precision is difficult to control, the groove is difficult to etch and clean the region without the gate layer, and the well-shaped and controllable gate structure is difficult to form. Therefore, how to form a gate region with a good interface and a controllable shape in the formation of the fin field effect transistor, reduce the etching difficulty of a gate layer and improve the performance of the transistor is an urgent problem to be solved in the industry.
Disclosure of Invention
In order to improve the performance of a fin field effect transistor and particularly solve the problem of higher difficulty in a process for forming a gate structure, the invention provides: a method for manufacturing a fin field effect transistor (FinFET), the method comprising:
providing a semiconductor substrate, wherein at least one fin-shaped structure and a dielectric layer positioned around the fin-shaped structure are formed on the semiconductor substrate; etching partial dielectric layers on two sides of the fin-shaped structure to form grooves on two sides of the fin-shaped structure; filling the gate layer; etching the gate layer to form a gate structure covering the bottom of the groove and the surface of the fin-shaped structure between the grooves, wherein the gate structure is in an inverted U shape; the length of the upper part of the grid structure of the fin field effect transistor along the channel direction is defined by grid etching; the length of the lower portion of the gate structure of the fin field effect transistor along the channel direction is defined by a groove.
Preferably, the width of the bottom of the gate structure is greater than the width of the top.
Preferably, the distance from the bottom of the groove to the bottom of the fin-shaped structure is as follows: 200 angstroms to 2000 angstroms.
Preferably, in the step of etching the gate layer, a part of the gate layer corresponding to the area around the groove is etched until the dielectric layer is exposed, and the dielectric layer plays a role in reducing the etching difficulty of the gate layer.
Preferably, a nitride layer or an oxynitride layer is formed on the upper surface of the fin-shaped structure, and the nitride layer or the oxynitride layer plays a role of a hard mask in the step of forming the groove by etching.
Preferably, in the formed fin field effect transistor structure, a nitride layer or an oxynitride layer is arranged between the gate structure and the upper surface of the fin structure.
Preferably, at least three adjacent fin-shaped structures and a dielectric layer positioned around the fin-shaped structures are formed; wherein, middle fin-shaped structure is defined as the channel region, and peripheral fin-shaped structure is supplementary fin-shaped structure, and the side slope of middle fin-shaped structure is: greater than or equal to 82 degrees.
Preferably, etching a part of the dielectric layer between the middle fin-shaped structure and the auxiliary fin-shaped structure to form a groove; and filling the gate layer, and etching the gate layer to form a gate structure covering the bottom of the groove and the surface of the fin-shaped structure between the grooves, wherein the gate structure is in an inverted U shape.
Preferably, the peripheral fin-shaped structures are symmetrical based on the middle fin-shaped structure;
etching part of the dielectric layer between the middle fin-shaped structure and the auxiliary fin-shaped structure to form grooves with symmetrical shapes and structures; and filling the gate layer, and etching the gate layer to form a symmetrical gate structure covering the bottom of the groove and the surface of the fin-shaped structure between the grooves, wherein the gate structure is in an inverted U shape.
The grid electrode structure formed by the invention has better shape and interface, greatly reduces the process difficulty, can be realized on the existing equipment, and can be compatible with the planar process.
Drawings
Other features and advantages of the present invention will be apparent from, or are set forth in more detail in, the accompanying drawings, which together with the description serve to explain certain principles of the invention. Wherein:
fig. 1 to 4 are schematic structural diagrams illustrating steps of fabricating a finfet in the prior art;
FIGS. 5-7 are schematic structural diagrams illustrating steps in fabricating a FinFET device according to an embodiment of the present invention;
fig. 8 to 10 are schematic structural diagrams illustrating steps of fabricating a finfet in accordance with another embodiment of the present invention.
Detailed Description
In order to solve the problems that the grid electrode structure of a fin field effect transistor (FinFET) in the prior art is difficult to process and the grid electrode layer is difficult to etch, the invention provides a manufacturing method of the fin field effect transistor, which comprises the following steps: providing a semiconductor substrate, wherein at least one fin-shaped structure and a dielectric layer positioned around the fin-shaped structure are formed on the semiconductor substrate; etching partial dielectric layers on two sides of the fin-shaped structure to form grooves on two sides of the fin-shaped structure; filling the gate layer; etching the gate layer to form a gate structure covering the bottom of the groove and the surface of the fin-shaped structure between the grooves, wherein the gate structure is in an inverted U shape; the length of the upper part of the grid structure of the fin field effect transistor along the channel direction is defined by grid etching; the length of the lower portion of the gate structure of the fin field effect transistor along the channel direction is defined by a groove.
The first embodiment:
referring to fig. 5 to 7, fig. 5 to 7 are schematic structural diagrams illustrating steps of fabricating a fin field effect transistor according to an embodiment of the invention; in fig. 5, a fin structure 110 ' is formed on a semiconductor substrate 100 ' in the prior art, a dielectric layer 200 ' is laid around the fin structure 110 ', wherein an upper surface of the dielectric layer 200 ' is flush with an upper surface of the fin structure 110 ', a portion of the dielectric layer 200 ' is etched in a portion of regions on both sides of the fin structure 110 ', grooves 300 ' are formed on both sides of the surface of the fin structure 110 ', and the above steps are completed by using photoresist, exposing, developing and etching, wherein the size of the groove 300 ' corresponds to the size of a gate structure to be formed, the width of the groove is 100nm in this embodiment, and the width range of the groove is: 30nm ~100um, the degree of depth of recess is: 1500A, the range of groove depths is: 500A to 2000A. Referring to fig. 6, in fig. 6, the surface of the dielectric layer 200 'and the surface of the recess 300' are covered with a gate layer 400 ', and the gate layer 400' may be made of polysilicon, metal, or High-K material; in this embodiment, a polysilicon material is used. In fig. 7, the gate layer 400 'is etched to form a gate structure 410' covering the bottom of the recess 300 'and the surface of the fin structure 110' between the recesses 300 ', the gate structure 410' being in an inverted U shape; the upper length of the fin field effect transistor gate structure 410' in the channel direction Y is defined by gate etching; the lower length of the gate structure of the fin field effect transistor along the channel direction Y is defined by the groove. Namely, the gate layer 400 'in the area which is not etched to the groove 300' is etched by etching the gate, and the dielectric layer 200 'can play a role in assisting in etching the gate layer 400'; in the area etched to the recess 300 ', the etching of the gate layer 400 ' is defined by the recess 300 ', and at this time, the recess 300 ' plays a role of assisting in etching the gate layer 400 ', and a portion of the gate layer 400 ' corresponding to the area around the recess is etched until the dielectric layer 200 ' is exposed. In the process of etching the gate layer 400 ', the area around the recess 300' is etched to the surface of the dielectric layer 200 ', and the area inside the recess 300' can control the progress of etching the gate layer 400 'and the shape of the etched gate structure 410'. In the first embodiment, the gate structure 410 'is formed to completely cover the bottom and sidewalls of the recess 300'; in the second embodiment, the gate structure 410 is formed to cover the bottom of the recess 300 'and partially cover the sidewalls of the recess 300'; in the third embodiment, the gate structure 410 is formed to cover the bottom of the recess 300 'without covering the sidewalls of the recess 300'; in the second and third embodiments, the gate structure 410 'covers the position of the recess 300' at the boundary between the upper portion and the lower portion corresponding to the channel direction Y. The sidewalls of the gate structure 410 ' have a curvature, the bottom width of the gate structure 410 ' is greater than the top width, and the shape and range of the etched gate layer are controlled to form a symmetrical gate structure 410 '. The distance from the bottom of the recess 300 'to the bottom of the fin structure 110' is: 200A to 2000A, in this embodiment greater than 500A. The technical difficulty of forming the gate structure 410' can be reduced through the scheme, the gate layer etching difficulty is reduced by assisting the etching of the gate layer through the groove and the surface of the dielectric layer, the technical difficulty is greatly reduced, the method can be realized on the existing equipment, and the method can be compatible with a plane process.
In the second embodiment, at least three adjacent fin-shaped structures and a dielectric layer positioned around the fin-shaped structures are formed; wherein, middle fin-shaped structure is defined as the channel region, and peripheral fin-shaped structure is supplementary fin-shaped structure, and the side slope of middle fin-shaped structure is: greater than or equal to 82 degrees. Etching part of the dielectric layer between the middle fin-shaped structure and the auxiliary fin-shaped structure to form a groove; and filling the gate layer, and etching the gate layer to form a gate structure covering the bottom of the groove and the surface of the fin-shaped structure between the grooves, wherein the gate structure is in an inverted U shape. Other steps and implementation methods are the same as the first embodiment.
In the third embodiment, at least three adjacent fin-shaped structures and a dielectric layer positioned around the fin-shaped structures are formed; wherein, middle fin-shaped structure is defined as the channel region, and peripheral fin-shaped structure is supplementary fin-shaped structure, and the side slope of middle fin-shaped structure is: greater than or equal to 82 degrees. The peripheral fin-shaped structures are symmetrical based on the middle fin-shaped structure; etching part of the dielectric layer between the middle fin-shaped structure and the auxiliary fin-shaped structure to form grooves with symmetrical shapes and structures; and filling the gate layer, and etching the gate layer to form a symmetrical gate structure covering the bottom of the groove and the surface of the fin-shaped structure between the grooves, wherein the gate structure is in an inverted U shape. Other steps and implementation method are the same as the first embodiment.
Referring to fig. 8 to 10, a fourth embodiment of the invention is shown, in which fig. 8 to 10 are schematic structural diagrams of steps of fabricating a finfet in another embodiment of the invention; in fig. 8, a fin structure 110 'is formed on a semiconductor substrate 100' in the prior art, a hard mask layer 120 'is formed on the top of the fin structure 110', a dielectric layer 200 'is laid around the fin structure 110', wherein the upper surface of the dielectric layer 200 'is flush with the upper surface of the hard mask layer 120', partial dielectric layers 200 'are etched in partial areas on both sides of the fin structure 110', grooves 300 'located on both sides of the surface of the fin structure 110' are formed, wherein the hard mask layer 120 'plays a role in assisting in etching the grooves 300', the hard mask layer 120 'is a nitride layer or an oxynitride layer, the size of the groove 300' corresponds to the size of the formed gate structure, the width of the groove 300 'is 100nm in the present embodiment, and the width of the groove 300' is in a range of 30nm to 100 nm: the depth of the groove 300' is: 1500A, the depth of the groove 300' ranges from: 500A to 2000A. With reference to fig. 9, the hard mask layer 120 ' is removed, and the gate layer 400 ' is covered on the surface of the dielectric layer 200 ' and the surface of the recess 300 ', and the gate layer 400 ' may be made of polysilicon, metal, or High-K material; in this embodiment, a polysilicon material is used. In fig. 10, the gate layer 400 'is etched to form a gate structure 410' covering the bottom of the recess 300 'and the surface of the fin structure 110' between the recesses 300 ', wherein the gate structure 410' is in an inverted U shape; the upper length of the gate structure 410' of the fin field effect transistor along the channel direction Y is defined by gate etching; the length of the lower part of the grid structure of the fin field effect transistor along the channel direction Y is defined by a groove. Namely, the gate layer 400 'in the area which is not etched to the groove 300' is etched by etching the gate, the part of the gate layer 400 'corresponding to the area around the groove is etched to expose the dielectric layer 200', and the dielectric layer 200 'can play a role of auxiliary etching of the gate layer 400'; in the area etched to the recess 300 ', the etching of the gate layer 400 ' is defined by the recess 300 ', and the recess 300 ' now serves as an auxiliary etching for the gate layer 400 '. By etching the gate layer 400 'in the area surrounding the recess 300' to the surface of the dielectric layer 200 ', the area inside the recess 300' can control the progress of the etching of the gate layer 400 'and the shape of the etched gate structure 410'. In the fourth embodiment, the gate structure 410 'is formed to completely cover the bottom and sidewalls of the recess 300'; in the fifth embodiment, the gate structure 410 ' is formed to cover the bottom of the recess 300 ' and partially cover the sidewalls of the recess 300 '; in the sixth embodiment, the gate structure 410 ' is formed to cover the bottom of the recess 300 ' and not to cover the sidewalls of the recess 300 '; in the fifth and sixth embodiments, the gate structure 410 'is covered to the position of the recess 300' as a decomposition of the upper and lower portions corresponding to the channel direction Y. The sidewall of the gate structure 410 'has a curvature, the bottom width of the gate structure 410' is larger than the top width, and the shape and range of the gate layer 400 'are controlled to be etched, so that a symmetrical gate structure 410' is formed. The distance from the bottom of the recess 300 'to the bottom of the fin structure 110' is: 200A to 2000A, in this embodiment greater than 500A. In yet another embodiment, the hard mask layer 120 ' is not removed after the formation of the recess 300 ', and the gate layer 400 ' is directly formed on the surface of the hard mask layer 120 ', and the hard mask layer 120 ' remains between the finally formed gate structure 410 ' and the upper surface of the fin structure 110 '. The technical difficulty of forming the grid structure 410' can be reduced through the scheme, the etching is assisted through the groove and the surface of the dielectric layer, the etching difficulty of the grid layer is reduced, the technical difficulty is greatly reduced, the method can be realized on the existing equipment, and the method can be compatible with a plane process.
In the fifth embodiment, at least three adjacent fin-shaped structures and a dielectric layer located around the fin-shaped structures are formed; wherein, middle fin-shaped structure is defined as the channel region, and peripheral fin-shaped structure is supplementary fin-shaped structure, and the side slope of middle fin-shaped structure is: greater than or equal to 82 degrees. Etching part of the dielectric layer between the middle fin-shaped structure and the auxiliary fin-shaped structure to form a groove; and filling the gate layer, and etching the gate layer to form a gate structure covering the bottom of the groove and the surface of the fin-shaped structure between the grooves, wherein the gate structure is in an inverted U shape. Other steps and implementation methods are the same as those of the fourth embodiment.
In the sixth embodiment, at least three adjacent fin-shaped structures and a dielectric layer located around the fin-shaped structures are formed; wherein, middle fin-shaped structure is defined as the channel region, and peripheral fin-shaped structure is supplementary fin-shaped structure, and the side slope of middle fin-shaped structure is: greater than or equal to 82 degrees. The peripheral fin-shaped structures are symmetrical based on the middle fin-shaped structure; etching part of the dielectric layer between the middle fin-shaped structure and the auxiliary fin-shaped structure to form grooves with symmetrical shapes and structures; and filling the gate layer, and etching the gate layer to form a symmetrical gate structure covering the bottom of the groove and the surface of the fin-shaped structure between the grooves, wherein the gate structure is in an inverted U shape. Other steps and implementation methods are the same as those of the fourth embodiment.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. A method for manufacturing a fin field effect transistor (FinFET), the method comprising:
providing a semiconductor substrate, wherein at least three adjacent fin-shaped structures and a dielectric layer positioned around the fin-shaped structures are formed on the semiconductor substrate; wherein, middle fin-shaped structure is defined as the channel region, and peripheral fin-shaped structure is supplementary fin-shaped structure, and the side slope of middle fin-shaped structure is: greater than or equal to 82 degrees;
etching partial dielectric layers on two sides of the fin-shaped structure to form grooves on two sides of the fin-shaped structure;
filling the gate layer;
etching the gate layer to form a gate structure covering the bottom of the groove and the surface of the fin-shaped structure between the grooves, wherein the gate structure is in an inverted U shape;
the length of the upper part of the grid structure of the fin field effect transistor along the channel direction is defined by grid etching; the length of the lower portion of the gate structure of the fin field effect transistor along the channel direction is defined by a groove.
2. The method of claim 1, wherein a bottom width of the gate structure is greater than a top width of the gate structure.
3. The method of claim 1, wherein the distance between the bottom of the trench and the bottom of the fin structure is: 200 angstroms to 2000 angstroms.
4. The method of claim 1, wherein in the step of etching the gate layer, a portion of the gate layer corresponding to the area around the recess is etched to expose the dielectric layer, and the dielectric layer serves to reduce the difficulty of etching the gate layer.
5. The method of claim 1, further comprising: and forming a nitride layer or an oxynitride layer on the upper surface of the fin-shaped structure, wherein the nitride layer or the oxynitride layer plays a role of a hard mask in the step of forming the groove by etching.
6. The method of claim 5, wherein the FinFET structure is formed such that a nitride or oxynitride layer remains between the gate structure and the top surface of the fin structure.
7. The method of claim 6, wherein the fin field effect transistor is formed on the substrate,
etching part of the dielectric layer between the middle fin-shaped structure and the auxiliary fin-shaped structure to form a groove;
and filling the gate layer, and etching the gate layer to form a gate structure covering the bottom of the groove and the surface of the fin-shaped structure between the grooves, wherein the gate structure is in an inverted U shape.
8. The method of claim 1, wherein the peripheral fin structure is symmetric based on a middle fin structure;
etching part of the dielectric layer between the middle fin-shaped structure and the auxiliary fin-shaped structure to form grooves with symmetrical shapes and structures;
and filling the gate layer, and etching the gate layer to form a symmetrical gate structure covering the bottom of the groove and the surface of the fin-shaped structure between the grooves, wherein the gate structure is in an inverted U shape.
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| CN201510662851.7A CN105448968B (en) | 2015-10-15 | 2015-10-15 | Method for manufacturing fin field effect transistor |
| PCT/CN2016/078741 WO2017063347A1 (en) | 2015-10-15 | 2016-04-07 | Method for manufacturing fin field-effect transistor |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102104069A (en) * | 2009-12-16 | 2011-06-22 | 中国科学院微电子研究所 | Fin-type transistor structure and manufacturing method thereof |
| CN103578988A (en) * | 2012-07-20 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | Fin part and finned-type field-effect transistor and forming method thereof |
| CN103681330A (en) * | 2012-09-10 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Fin and fin forming method |
| CN104103506A (en) * | 2013-04-11 | 2014-10-15 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
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| CN104392917B (en) * | 2014-11-17 | 2017-09-29 | 上海集成电路研发中心有限公司 | A kind of forming method of all-around-gate structure |
| CN105448968B (en) * | 2015-10-15 | 2020-05-12 | 格科微电子（上海）有限公司 | Method for manufacturing fin field effect transistor |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102104069A (en) * | 2009-12-16 | 2011-06-22 | 中国科学院微电子研究所 | Fin-type transistor structure and manufacturing method thereof |
| CN103578988A (en) * | 2012-07-20 | 2014-02-12 | 中芯国际集成电路制造(上海)有限公司 | Fin part and finned-type field-effect transistor and forming method thereof |
| CN103681330A (en) * | 2012-09-10 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Fin and fin forming method |
| CN104103506A (en) * | 2013-04-11 | 2014-10-15 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
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