CN105448839B - The photolithography method of semiconductor devices, the production method of flush memory device and flush memory device - Google Patents
The photolithography method of semiconductor devices, the production method of flush memory device and flush memory device Download PDFInfo
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Abstract
This application discloses a kind of photolithography method of semiconductor devices, the production method of flush memory device and flush memory devices.The semiconductor devices includes area to be etched and non-etched area, which includes: to form mask layer on the semiconductor device；The first optical resistance glue layer of ion implanted processing is formed on the exposure mask for being located at non-etched area；Form in the first optical resistance glue layer and on the exposure mask in area to be etched second optical resistance glue layer；The second optical resistance glue layer for being located at area to be etched is exposed and is performed etching.In the photolithography method, before the step of the second optical resistance glue layer for being located at area to be etched is exposed and is performed etching, the first optical resistance glue layer of ion implanted processing is formed on the exposure mask for being located at non-etched area.First optical resistance glue layer can reduce photoetching process damage caused by non-etched features area, and then improve the performance of semiconductor devices.
Description
Technical field
The present invention relates to semiconductor integrated circuit technology fields, in particular to a kind of photoetching side of semiconductor devices
Method, the production method of flush memory device and flush memory device.
Background technique
In the manufacturing process of semiconductor integrated circuit, the height of some devices is not identical, so that with different performance
Isolation is formed between device, and then improves the anti-breakdown voltage and other performances of transistor.However, the device of different height can be led
Chip is caused to appear on the stage the generation of stage structure, this step structure usually will affect the technical process such as subsequent photoetching and ion implanting,
The manufacturing process of especially step-like grid.For example, when carrying out the techniques such as photoetching and etching to the lower grid in position, position
Higher grid will receive damage, and then influence the stability of chip.
Step structure also exists in flash memory.Flash memory includes memory cell areas and logic circuit area,
Wherein memory cell areas includes the floating gate and control gate set gradually along the direction far from memory cell areas, and logic circuit area includes
Logic gate.Wherein, floating gate and control gate 100nm higher than logic gate or so, so as to form step-like gate structure.Work as flash
When the processing procedure of memory is greater than 55nm, the KrF light source (wavelength 248nm) or I-line light with larger wavelength are usually utilized
Source (wavelength 365nm) carries out photoetching to logic gate, and in order to avoid control gate is by overetch, usually face is coated on the control gate
One layer of photoresist glue (0.4 μm~3 μm) with adequate thickness.When flash memory reaches 55nm even more small processing procedure, usually
ArF laser light source (wavelength 193nm) is selected to carry out photoetching to logic gate.However, in order to improve the film thickness of chip entirety equalization
Change, when carrying out photoetching using ArF laser light source, the thickness of commonly required photoresist glue is smaller (0.2 μm~0.5 μm), therefore right
Logic circuit area carries out in photoetching and etching process, will certainly floating gate to memory cell areas and control gate cause to damage.
In order to avoid photoetching and etching process cause to damage to memory cell areas, there are two types of ways at present: first is that controlling
One layer of hard exposure mask is deposited on grid as protective layer, but need to be removed with wet etching after the completion of photoetching and etching technics covers firmly
Film, wet-etching technology can further result in grid damage；Second is that depositing multilayer photoresist glue on the control gate, subsequent technique is prevented
Damage, but using ArF laser light source carry out photoetching when photoresist glue between can dissolve, cause blocking effect unknown
It is aobvious.
Summary of the invention
The application is intended to provide a kind of photolithography method of semiconductor devices, the production method of flush memory device and flush memory device,
To reduce photoetching process damage caused by device.
To solve the above-mentioned problems, this application provides a kind of photolithography method of semiconductor devices, the semiconductor devices packets
Area to be etched and non-etched area are included, which includes: to form mask layer on the semiconductor device；It is being located at non-etched area
The first optical resistance glue layer of ion implanted processing is formed on exposure mask；In the first optical resistance glue layer and the shape on the exposure mask in area to be etched
At the second optical resistance glue layer；The second optical resistance glue layer for being located at area to be etched is exposed and is performed etching.
Further, in above-mentioned photolithography method, formed the first optical resistance glue layer the step of include: that first is formed on mask layer
Photoresist glue preparation layers；Ion implanting processing is carried out to the first photoresist glue preparation layers, forms the first photoresist glue transition zone；Removal is located at
The first photoresist glue transition zone in area to be etched forms the first optical resistance glue layer.
Further, in above-mentioned photolithography method, ion implanting processing the step of in, injection ion energy for 15keV~
50keV, injection ion concentration are 1E+13atoms/cm3~1E+16atoms/cm3。
Further, in above-mentioned photolithography method, injection ion is preferably phosphonium ion or boron ion.
Further, it in above-mentioned photolithography method, in the step of forming the first optical resistance glue layer, is formed with a thickness of 0.2~3 μm
The first optical resistance glue layer；In the step of forming the second optical resistance glue layer, the second optical resistance glue layer with a thickness of 50~200nm is formed.
Further, it in above-mentioned photolithography method, is formed after the first optical resistance glue layer, the first optical resistance glue layer is toasted.
Further, in above-mentioned photolithography method, the step of baking in, the temperature of baking is 100~300 DEG C, baking when
Between be 1~3min.
Further, in above-mentioned photolithography method, mask layer is anti-reflection coating or amorphous carbon layer.
Present invention also provides a kind of production method of flush memory device, which includes: that substrate is divided into core
Memory block and logic circuit area；First grid is formed in core memory area, and formation second grid is pre- on logic circuit area
Standby layer, the upper surface of first grid are higher than the upper surface of second grid preparation layers；Photoetching and quarter are carried out to second grid preparation layers
To form second grid, the method for photoetching is the above-mentioned photolithography method of the application for erosion.
Further, in above-mentioned production method, first grid includes floating gate and the control gate on floating gate, second gate
Extremely logic gate.
Present invention also provides a kind of flush memory device, the flush memory device by the above-mentioned flush memory device of the application production method system
It forms.
Using technical scheme, what the second optical resistance glue layer for being located at area to be etched was exposed and was performed etching
Before step, the first optical resistance glue layer of ion implanted processing is formed on the exposure mask for being located at non-etched area.By injecting ion
The intermolecular distance in the first optical resistance glue layer can be shortened, so that the compact structure of the first optical resistance glue layer is improved.Therefore, should
First optical resistance glue layer can prevent the etching ion during subsequent photoetching from entering non-etched features area, to reduce photoetching process
It is damaged caused by device, and then improves the performance of semiconductor devices.
Detailed description of the invention
The attached drawing for constituting a part of the invention is used to provide further understanding of the present invention, schematic reality of the invention
It applies example and its explanation is used to explain the present invention, do not constitute improper limitations of the present invention.In the accompanying drawings:
Fig. 1 shows the flow diagram of the photolithography method of semiconductor devices provided by the application embodiment；
Fig. 2 shows in the photolithography method of semiconductor devices provided by the application embodiment, on the semiconductor device
The schematic diagram of the section structure of matrix after forming mask layer；
Fig. 3 shows the first photoresist that ion implanted processing is formed on the exposure mask for being located at non-etched area shown in Fig. 2
The schematic diagram of the section structure of matrix after glue-line；
Fig. 3-1 shows the cross-section structure of the matrix after forming the first photoresist glue preparation layers on mask layer shown in Fig. 2
Schematic diagram；
Fig. 3-2, which is shown, carries out ion implanting processing the first photoresist of formation to the first photoresist glue preparation layers shown in Fig. 3-1
The schematic diagram of the section structure of matrix after glue transition zone；
Fig. 4 shows the first optical resistance glue layer shown in Fig. 3 and forms the second photoresist glue on the exposure mask in area to be etched
The schematic diagram of the section structure of matrix after layer；
Fig. 5 show to be located at area to be etched shown in Fig. 4 the second optical resistance glue layer be exposed and perform etching after
The schematic diagram of the section structure of matrix.
Specific embodiment
An exemplary embodiment of the present invention is more fully described below with reference to accompanying drawings.However, these exemplary realities
Applying example can be implemented by many different forms, and should not be construed to be limited solely to the embodiments set forth herein.It answers
When these embodiments that are to provide of understanding are in order to enable disclosure of the invention is thoroughly and complete, and by these exemplary realities
The design for applying example is fully conveyed to those of ordinary skill in the art.But the present invention can be defined by the claims and cover it is more
Kind different modes are implemented.
For ease of description, spatially relative term can be used herein, as " ... on ", " ... top ",
" ... upper surface ", " above " etc., for describing such as a device shown in the figure or feature and other devices or spy
The spatial relation of sign.It should be understood that spatially relative term is intended to comprising the orientation in addition to device described in figure
Except different direction in use or operation.For example, being described as if the device in attached drawing is squeezed " in other devices
It will be positioned as " under other devices or construction after part or construction top " or the device of " on other devices or construction "
Side " or " under other devices or construction ".Thus, exemplary term " ... top " may include " ... top " and
" in ... lower section " two kinds of orientation.The device can also be positioned with other different modes and (is rotated by 90 ° or in other orientation), and
And respective explanations are made to the opposite description in space used herein above.
It can be seen from background technology that photoetching process can cause to damage to step-like device.Present inventor is for above-mentioned
Problem is studied, and a kind of photolithography method of semiconductor devices is proposed, which includes area to be etched and non-etching
Area, as shown in Figure 1, the photolithography method includes: to form mask layer on the semiconductor device；The shape on the exposure mask for being located at non-etched area
At the first optical resistance glue layer of ion implanted processing；Form in the first optical resistance glue layer and on the exposure mask in area to be etched second light
Hinder glue-line；The second optical resistance glue layer for being located at area to be etched is exposed and is performed etching.
In above-mentioned photolithography method, in the step of the second optical resistance glue layer for being located at area to be etched is exposed and is performed etching
Before, the first optical resistance glue layer of ion implanted processing is formed on the exposure mask for being located at non-etched area.Injection ion can shorten
Intermolecular distance in first optical resistance glue layer, so that the compact structure of the first optical resistance glue layer is improved.Therefore, first photoresist
Glue-line can prevent the etching ion during subsequent photoetching from entering non-etched features area, make to reduce photoetching process to device
At damage, and then improve semiconductor devices performance.
The illustrative embodiments according to the application are described in more detail below.However, these illustrative embodiments
It can be implemented by many different forms, and should not be construed to be limited solely to embodiments set forth herein.It should
These embodiments that are to provide understood are in order to enable disclosure herein is thoroughly and complete, and by these exemplary realities
The design for applying mode is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expands layer and region
Thickness, and make that identical device is presented with like reference characters, thus description of them will be omitted.
Fig. 2 to Fig. 5, which is shown, to be formed after each step in the photolithography method of semiconductor devices provided by the present application
The schematic diagram of the section structure.It is further below in conjunction with Fig. 2 to Fig. 5 in order to further illustrate photolithography method provided herein
Illustrate the photolithography method of semiconductor devices provided by the present application.
Firstly, forming mask layer 30 on the semiconductor device, and then form base structure as shown in Figure 2.Above-mentioned exposure mask
Layer 30 can be mask material common in this field, and in a preferred embodiment, the material of above-mentioned mask layer 30 is
Anti-reflection coating BARC or agraphitic carbon.The technique for forming above-mentioned mask layer 30 can be spin coating etc..It is formed when using spin coating
When stating mask layer 30, in a kind of optional embodiment, comprising the following steps: mask material is added dropwise on wafer, accelerates rotation
Turn, mask material is evenly coated in area 23 and non-etched area 21 to be etched.It, can in above-mentioned semiconductor device formation and substrate 10
Selection of land, above-mentioned semiconductor device are grid, and the non-etched area 21 of semiconductor devices is first grid, semiconductor devices it is to be etched
Erosion area 23 is second grid preparation layers, and the upper surface of non-etched area 21 is higher than the upper surface of etched area.As an example, below will
It is described with structure shown in Fig. 2.
After completing the step of forming mask layer 30 on the semiconductor device, formed on the exposure mask for being located at non-etched area 21
First optical resistance glue layer 40 of ion implanted processing, and then form base structure as shown in Figure 3.In a kind of preferred embodiment party
In formula, the step of forming the first optical resistance glue layer 40 includes: that the first photoresist glue preparation layers 40 ' are formed on mask layer 30, and then shape
At base structure as shown in figure 3-1；Ion implanting processing is carried out to the first photoresist glue preparation layers 40 ' and forms the first photoresist glue mistake
Cross layer 40 ", and then form base structure as shown in figure 3-2；Removal is located at the first photoresist glue transition zone in area 23 to be etched
40 ", the first optical resistance glue layer 40 is formed, and then forms base structure as shown in Figure 3.
The material of above-mentioned first photoresist glue preparation layers 40 ' can be DUV 248nm photoresist or DUV 365nm photoresist, be formed
The technique of above-mentioned first photoresist glue preparation layers 40 ' can be spin coating etc..When use spin coating forms above-mentioned first photoresist glue preparation layers
When 40 ', in a kind of optional embodiment, comprising the following steps: photoresist is added dropwise on wafer, accelerates rotation, photoresist
Material is evenly coated in area 23 and non-etched area 21 to be etched.
Above-mentioned photoresist is mainly mixed by three kinds of resin, emulsion and solvent ingredients.In existing multilayer photoresist material
In the spin coating proceeding of material, the solvent in photoresist coated afterwards can dissolve the resin in preceding layer photoresist, so that light
It dissolves each other between resistance material, influences the accuracy of subsequent photoetching process.In order to reduce dissolving each other between above-mentioned photoresist, this
Application carries out ion implanting, technical process principle to the first photoresist glue preparation layers 40 ' are as follows: the ion for generating ion source is through adding
High 40 ' surface of fast direction the first photoresist glue preparation layers after speed, when ion enters surface, will in the first photoresist glue preparation layers 40 '
Atomic collision, hence into the first photoresist glue preparation layers 40 '；Injection ion is handed over the first photoresist glue preparation layers 40 '
Connection reaction, forms X-C6H5(X is injection ion), thus in the middle formation " X-C of the first photoresist glue preparation layers 40 '6H5Cross-linked layer ".
In " X-C6H5In cross-linked layer ", injection ion can occupy the position of the molecule of part the first photoresist glue preparation layers 40 ', so as to shorten
The intermolecular distances of first photoresist glue preparation layers 40 ', so that the middle network structure of the first photoresist glue preparation layers 40 ' is finer and close, from
And the first photoresist glue preparation layers 40 ' will not be dissolved by the solvent in the photoresist of rear coating.Preferably, above-mentioned ion note
The process conditions entered are as follows: injection ion energy is 15~50keV, and injection ion concentration is 1E+13atoms/cm3~1E+
16atoms/cm3, injection ion is preferably phosphonium ion or boron ion.
In a kind of optional embodiment, removal is located at the above-mentioned first photoresist glue preparation layers 40 ' in area 23 to be etched
The step of include: that processing is exposed to the first photoresist glue preparation layers 40 ' after ion implanted, remove the photoresist on etched area
Glue forms the first optical resistance glue layer 40.Preferably, the first optical resistance glue layer 40 with a thickness of 0.2~3 μm.
After forming above-mentioned first optical resistance glue layer 40, the first photoresist glue can also be toasted, to improve the first photoresist
Adhesion between the compactness of glue-line 40, and the first optical resistance glue layer 40 of enhancing and area to be etched 23.Above-mentioned baking process
Step includes: that the chip comprising the first photoresist glue is placed on hot plate so that chip surface is in contact with hot plate, then certain
The first photoresist glue is toasted under the conditions of temperature, evaporates the solvent in the first optical resistance glue layer 40.Preferably, the temperature of baking
It is 100 DEG C~300 DEG C, the time of baking is 1~3min.
It completes the step of forming the first optical resistance glue layer 40 of ion implanted processing on the exposure mask for being located at non-etched area 21
Later, second optical resistance glue layer 50 is formed in the first optical resistance glue layer 40 and on the exposure mask in area 23 to be etched, and then forms such as Fig. 4
Shown in base structure.The material of above-mentioned second optical resistance glue layer 50 can be DUV 193nm photoresist, form above-mentioned second photoresist glue
The technique of layer 50 can be spin coating etc..When forming above-mentioned second optical resistance glue layer 50 using spin coating, a kind of optional embodiment
In, comprising the following steps: by photoresist be added dropwise on wafer, accelerate rotating wafer so that photoresist painting be evenly coated in
On etched area 23 and non-etched area 21, to form the second optical resistance glue layer 50.Preferably, the second photoresist glue with a thickness of 50~
200nm。
The second optical resistance glue layer 50 for being located at area 23 to be etched is exposed and is performed etching, and then is formed as shown in Figure 5
Base structure.Above-mentioned steps include: to be exposed development to the second photoresist layer, then with the second photoresist glue after exposure development
Layer 50 is exposure mask, performs etching mask layer 30 and area to be etched 23 to form required device.Above-mentioned etching can be wet process
Etching, above-mentioned technique are state of the art, and details are not described herein.
Present invention also provides a kind of production method of flush memory device, which includes: that substrate is divided into core
Memory block and logic circuit area；First grid is formed in core memory area, and formation second grid is pre- on logic circuit area
Standby layer, the upper surface of first grid are higher than the upper surface of second grid preparation layers；Photoetching and quarter are carried out to second grid preparation layers
To form second grid, the method for photoetching is the above-mentioned photolithography method of the application for erosion.Using photolithography method institute provided by the present application
The gate structure of obtained flush memory device is intact, and the stability of device is improved.
In a preferred embodiment, above-mentioned first grid includes floating gate and the control gate on floating gate, on
Stating second grid is logic gate.Above-mentioned production method further comprises: in the above-mentioned production position in the core memory area of semiconductor substrate
Line and wordline, interlayer dielectric layer, planarization, deposit passivation layer and subsequent encapsulating process.These techniques are existing for this field
There is technology, details are not described herein.
Present invention also provides a kind of flush memory device, the flush memory device by the above-mentioned flush memory device of the application production method system
It forms.The gate structure of the flush memory device is intact, and the stability of device is improved.
The production side of photolithography method and flush memory device provided herein will be further illustrated with specific embodiment below
Method.
Embodiment 1
The production method of flush memory device provided in this embodiment the following steps are included:
Substrate is divided into core memory area and logic circuit area, and forms first grid in core memory area, and
Second grid preparation layers are formed on logic circuit area, the upper surface of first grid is higher than the upper surface of second grid preparation layers；
Anti-reflection coating and the first photoresist glue preparation layers (DUV are sequentially formed on first grid and second grid preparation layers
248nm photoresist), wherein anti-reflection coating with a thickness of 0.4 μm, the first photoresist glue preparation layers with a thickness of 0.2 μm；To the first light
It hinders glue preparation layers and carries out ion implanting processing, form the first photoresist glue transition zone, injection ion is phosphonium ion, injects ion energy
For 15keV, injection ion concentration is 1E+13atoms/cm3；Removal is located at the first photoresist glue transition in second grid preparation layers
Layer forms the first optical resistance glue layer；First optical resistance glue layer is toasted, wherein the temperature toasted be 100 DEG C, the baking when
Between be 3min；
The second optical resistance glue layer is formed in the first optical resistance glue layer and exposure mask positioned at logic circuit area, wherein the second photoresist glue
Layer with a thickness of 50nm；The second optical resistance glue layer for being located at logic circuit area is exposed and is performed etching to form opening, and edge
Opening etching anti-reflection coating and second grid preparation layers form second grid.
Embodiment 2
The production method of flush memory device provided in this embodiment the following steps are included:
Substrate is divided into core memory area and logic circuit area, and forms first grid in core memory area, and
Second grid preparation layers are formed on logic circuit area, the upper surface of first grid is higher than the upper surface of second grid preparation layers；
Anti-reflection coating and the first photoresist glue preparation layers (DUV are sequentially formed on first grid and second grid preparation layers
248nm photoresist), wherein anti-reflection coating with a thickness of 0.4 μm, the first photoresist glue preparation layers with a thickness of 3 μm；To the first photoresist
Glue preparation layers carry out ion implanting processing, form the first photoresist glue transition zone, and injection ion is phosphonium ion, and injection ion energy is
50keV, injection ion concentration are 1E+16atoms/cm3；Removal is located at the first photoresist glue transition in second grid preparation layers
Layer forms the first optical resistance glue layer；First optical resistance glue layer is toasted, wherein the temperature toasted be 300 DEG C, the baking when
Between be 1min；
The second optical resistance glue layer is formed in the first optical resistance glue layer and exposure mask positioned at logic circuit area, wherein the second photoresist glue
Layer with a thickness of 200nm；The second optical resistance glue layer for being located at logic circuit area is exposed and is performed etching to form opening, and edge
Opening etching anti-reflection coating and second grid preparation layers form second grid.
Embodiment 3
The production method of flush memory device provided in this embodiment the following steps are included:
Substrate is divided into core memory area and logic circuit area, and forms first grid in core memory area, and
Second grid preparation layers are formed on logic circuit area, the upper surface of first grid is higher than the upper surface of second grid preparation layers；
Anti-reflection coating and the first photoresist glue preparation layers (DUV are sequentially formed on first grid and second grid preparation layers
248nm photoresist), wherein anti-reflection coating with a thickness of 0.4 μm, the first photoresist glue preparation layers with a thickness of 1 μm；To the first photoresist
Glue preparation layers carry out ion implanting processing, form the first photoresist glue transition zone, and injection ion is boron ion, and injection ion energy is
30keV, injection ion concentration are 1E+15atoms/cm3；Removal is located at the first photoresist glue transition in second grid preparation layers
Layer forms the first optical resistance glue layer；First optical resistance glue layer is toasted, wherein the temperature toasted be 200 DEG C, the baking when
Between be 2min；
The second optical resistance glue layer is formed in the first optical resistance glue layer and exposure mask positioned at logic circuit area, wherein the second photoresist glue
Layer with a thickness of 100nm；The second optical resistance glue layer for being located at logic circuit area is exposed and is performed etching to form opening, and edge
Opening etching anti-reflection coating and second grid preparation layers form second grid.
Embodiment 4
The production method of flush memory device provided in this embodiment the following steps are included:
Substrate is divided into core memory area and logic circuit area, and forms first grid in core memory area, and
Second grid preparation layers are formed on logic circuit area, the upper surface of first grid is higher than the upper surface of second grid preparation layers；
Anti-reflection coating and the first photoresist glue preparation layers (DUV are sequentially formed on first grid and second grid preparation layers
248nm photoresist), wherein anti-reflection coating with a thickness of 0.4 μm, the first photoresist glue preparation layers with a thickness of 3.2 μm；To the first light
It hinders glue preparation layers and carries out ion implanting processing, form the first photoresist glue transition zone, injection ion is phosphonium ion, injects ion energy
For 52keV, injection ion concentration is 1.2E+16atoms/cm3；Removal is located at the first photoresist glue mistake in second grid preparation layers
Layer is crossed, the first optical resistance glue layer is formed；First optical resistance glue layer is toasted, wherein the temperature toasted is 320 DEG C, the baking
Time is 4min；
The second optical resistance glue layer is formed in the first optical resistance glue layer and exposure mask positioned at logic circuit area, wherein the second photoresist glue
Layer with a thickness of 220nm；The second optical resistance glue layer for being located at logic circuit area is exposed and is performed etching to form opening, and edge
Opening etching anti-reflection coating and second grid preparation layers form second grid.
Comparative example 1
The production method of flush memory device provided in this embodiment the following steps are included:
Substrate is divided into core memory area and logic circuit area, and forms first grid in core memory area, and
Second grid preparation layers are formed on logic circuit area, the upper surface of first grid is higher than the upper surface of second grid preparation layers；
Anti-reflection coating and optical resistance glue layer (DUV 248nm light are sequentially formed on first grid and second grid preparation layers
Resistance), wherein anti-reflection coating with a thickness of 0.4 μm, optical resistance glue layer with a thickness of 2 μm；
The optical resistance glue layer for being located at logic circuit area is exposed and is performed etching to form opening, and etches anti-reflective along opening
It penetrates coating and second grid preparation layers forms second grid.
Test: the microscopic appearance of device is obtained using scanning electron microscopic observation embodiment 1 to 4 and comparative example 1, and is measured
The depth of pothole on first grid surface, to characterize photoetching process damage caused by first grid.Dependence test result see
Table 1.
Table 1
| The depth of pothole | |
| Embodiment 1 | 12nm |
| Embodiment 2 | 11nm |
| Embodiment 3 | 13nm |
| Embodiment 4 | 16nm |
| Comparative example 1 | 54nm |
From the data in table 1 can be seen that pothole on the first grid surface that embodiment 1 to 4 obtains depth be 11~
16nm, and the depth of pothole is 54nm on the first grid surface that comparative example 1 obtains.As it can be seen that photoetching process in embodiment 1 to 4
The damage caused by first grid is significantly less than photoetching process damage caused by first grid in comparative example 1.
As can be seen from the above embodiments, the above-mentioned example of the application realizes following technical effect: to be etched to being located at
Before second optical resistance glue layer be exposed and perform etching the step of in erosion area, formed on the exposure mask for being located at non-etched area through from
First optical resistance glue layer of son injection processing.Injection ion can shorten the intermolecular distance in the first optical resistance glue layer, so that the first light
The compact structure of resistance glue-line is improved.Therefore, first optical resistance glue layer can prevent the etching during subsequent photoetching from
Son enters non-etched features area, to reduce photoetching process damage caused by device, and then improves semiconductor devices
Performance.
The above is only preferred embodiment of the present application, are not intended to limit this application, for those skilled in the art
For member, various changes and changes are possible in this application.Within the spirit and principles of this application, it is made it is any modification,
Equivalent replacement, improvement etc., should be included within the scope of protection of this application.
Claims (9)
1. a kind of photolithography method of semiconductor devices, the semiconductor devices include area to be etched and non-etched area, feature exists
In the photolithography method includes:
Mask layer is formed on the semiconductor devices；
The first optical resistance glue layer of ion implanted processing is formed on the exposure mask for being located at the non-etched area；And the ion implanting
In the step of processing, injection ion is phosphonium ion or boron ion
The second optical resistance glue layer is formed in first optical resistance glue layer and on the exposure mask in the area to be etched；
The second optical resistance glue layer for being located at the area to be etched is exposed and etches the area to be etched.
2. photolithography method according to claim 1, which is characterized in that formed first optical resistance glue layer the step of include:
The first photoresist glue preparation layers are formed on the mask layer；
Ion implanting processing is carried out to the first photoresist glue preparation layers, forms the first photoresist glue transition zone；
Removal is located at the first photoresist glue transition zone in the area to be etched, forms first optical resistance glue layer.
3. photolithography method according to claim 1 or 2, which is characterized in that in the step of ion implanting is handled, injection
Ion energy is 15keV~50keV, and injection ion concentration is 1E+13atoms/cm3~1E+16atoms/cm3。
4. photolithography method according to claim 1 or 2, which is characterized in that
In the step of forming first optical resistance glue layer, first optical resistance glue layer with a thickness of 0.2~3 μm is formed；
In the step of forming second optical resistance glue layer, second optical resistance glue layer with a thickness of 50~200nm is formed.
5. photolithography method according to claim 1 or 2, which is characterized in that formed second optical resistance glue layer the step of it
Before, first optical resistance glue layer is toasted.
6. photolithography method according to claim 5, which is characterized in that in the step of the baking, the temperature of the baking
It is 100~300 DEG C, the time of the baking is 1~3min.
7. photolithography method according to claim 1 or 2, which is characterized in that the mask layer is for anti-reflection coating or without fixed
Type carbon-coating.
8. a kind of production method of flush memory device, which is characterized in that the production method includes:
Substrate is divided into core memory area and logic circuit area；
First grid is formed in the core memory area, and second grid preparation layers, institute are formed on the logic circuit area
The upper surface for stating first grid is higher than the upper surface of the second grid preparation layers；
Photoetching and etching are carried out to the second grid preparation layers to form second grid, the method for the photoetching is claim
Photolithography method described in any one of 1 to 7.
9. production method according to claim 8, which is characterized in that the first grid includes floating gate and is located at described floating
Control gate on grid, the second grid are logic gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410415519.6A CN105448839B (en) | 2014-08-21 | 2014-08-21 | The photolithography method of semiconductor devices, the production method of flush memory device and flush memory device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410415519.6A CN105448839B (en) | 2014-08-21 | 2014-08-21 | The photolithography method of semiconductor devices, the production method of flush memory device and flush memory device |
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| Publication Number | Publication Date |
|---|---|
| CN105448839A CN105448839A (en) | 2016-03-30 |
| CN105448839B true CN105448839B (en) | 2019-06-04 |
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