CN105448805B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN105448805B CN105448805B CN201410425885.XA CN201410425885A CN105448805B CN 105448805 B CN105448805 B CN 105448805B CN 201410425885 A CN201410425885 A CN 201410425885A CN 105448805 B CN105448805 B CN 105448805B
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Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method of the semiconductor structure comprises the following steps: providing a substrate, wherein a zeroth metal layer is formed in the substrate; forming a first adhesion layer and a first porous medium layer positioned on the surface of the first adhesion layer on the surface of the substrate, wherein the Young modulus of the first adhesion layer is greater than that of the first porous medium layer; carrying out first ultraviolet irradiation on the first porous medium layer to improve the Young modulus of the first porous medium layer; etching the first porous medium layer and the first adhesion layer to form a first opening, wherein the bottom of the first opening is exposed out of the surface of the zeroth metal layer; and forming a first metal layer which is filled in the first opening, wherein the top surface of the first metal layer is flush with the top surface of the first porous medium layer. The invention improves the Young modulus of the semiconductor structure, thereby improving the mechanical strength of the semiconductor structure and improving the reliability of the semiconductor structure.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof.
Background
As the integrated circuit is manufactured into a very large scale integrated circuit, the circuit density of the integrated circuit is increased, the number of semiconductor devices included in the integrated circuit is increased, the number of interconnection lines (interconnects) required for connecting the semiconductor devices is increased, and the silicon area is required to be increased to provide more interconnection line layout space.
In order to meet the demand for an increase in the number of interconnect lines formed on a silicon wafer and to meet the trend of miniaturization of integrated circuits, the prior art proposes a solution for a multilayer interconnect structure technology to provide sufficient interconnection capability for each semiconductor device. A semiconductor structure having a multilayer interconnect structure includes: the semiconductor device comprises a substrate and a zero-level metal layer (M0) positioned in the substrate, wherein the zero-level metal layer is electrically connected with a source drain region or a grid structure region of the semiconductor device; the dielectric layer is positioned on the surface of the substrate and provides an insulating effect between adjacent metal layers; the through hole is positioned in the medium layer, and the bottom of the through hole is exposed out of the surface of the zero layer metal layer; and a first metal layer (M1) located in the through hole and filling the through hole, and the first metal layer is electrically connected with the zero metal layer.
However, the electrical performance and reliability of the semiconductor structures formed by the prior art need to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the mechanical strength of the semiconductor structure, prevent the semiconductor structure from cracking or layering and improve the reliability of the semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein a zeroth metal layer is formed in the substrate; forming a first adhesion layer and a first porous medium layer positioned on the surface of the first adhesion layer on the surface of the substrate, wherein the Young modulus of the first adhesion layer is greater than that of the first porous medium layer; carrying out first ultraviolet irradiation on the first porous medium layer to improve the Young modulus of the first porous medium layer; etching the first porous medium layer and the first adhesion layer to form a first opening, wherein the bottom of the first opening is exposed out of the surface of the zeroth metal layer; and forming a first metal layer which is filled in the first opening, wherein the top surface of the first metal layer is flush with the top surface of the first porous medium layer.
Optionally, the relative dielectric constant of the material of the first porous medium layer is 2.71 to 2.79, and the young modulus of the first porous medium layer is 5.8Gpa to 6.2 Gpa.
Optionally, the first ultraviolet irradiation process parameters are as follows: the irradiation power is 1000W to 6000W, the irradiation time is 2 minutes to 6 minutes, and the ultraviolet wavelength is 200 nanometers to 350 nanometers.
Optionally, after the first ultraviolet irradiation, the relative dielectric constant of the material of the first porous dielectric layer is 2.5 to 2.6, and the young modulus of the first porous dielectric layer is 7.8Gpa to 8.2 Gpa.
Optionally, a chemical vapor deposition process is used to form the first porous medium layer, and the process parameters of the chemical vapor deposition process are as follows: the reaction raw materials comprise silane and oxygen source gas, wherein the silane is one or two of methyldiethoxysilane or octamethylcyclotetrasiloxane, and the oxygen source gas is O2The flow rate of silane is 0.2g/m to 2g/m, the flow rate of oxygen source gas is 50sccm to 1000sccm, the temperature of a deposition chamber is 200 ℃ to 400 ℃, the pressure of the deposition chamber is 1 Torr to 20 Torr, the power of the deposition chamber is 100W to 1000W, a pore-forming agent is introduced into the chamber, and the flow rate of the pore-forming agent is 100sccm to 3000 sccm.
Optionally, the young's modulus of the first adhesive layer is greater than 70 Gpa.
Optionally, the material of the first adhesion layer is silicon oxide, and the thickness of the first adhesion layer is 30 to 300 angstroms.
Optionally, a chemical vapor deposition process is used to form the first adhesion layer, and the process parameters of the chemical vapor deposition process are as follows: the reaction raw materials comprise a silicon source and oxygen source gas, wherein the silicon source is SiH4Or tetraethoxysilane, the flow rate of the silicon source is 100sccm to 2000sccm or 2g/m to 10g/m, the flow rate of the oxygen source gas is increased from zero to 500sccm, the pressure of the deposition chamber is 1 Torr to 10 Torr, the power of the deposition chamber is 100W to 1000W, and the temperature of the deposition chamber is 250 ℃ to 400 ℃.
Optionally, the method further includes: forming an Nth adhesion layer on the surface of the (N-1) (N is more than or equal to 2) th porous medium layer and an Nth porous medium layer positioned on the surface of the Nth adhesion layer; carrying out Nth ultraviolet irradiation on the Nth porous medium layer to improve the Young modulus of the Nth porous medium layer; etching the Nth porous dielectric layer and the Nth adhesion layer to form an Nth opening, wherein the bottom of the Nth opening is exposed out of the surface of the (N-1) th metal layer; and forming an Nth metal layer filled in the Nth opening, wherein the top surface of the Nth metal layer is flush with the top surface of the Nth porous medium layer.
Optionally, the method further comprises the steps of: forming a first stop layer between the substrate and the first adhesion layer; and forming an Nth stop layer between the N-1 th porous medium layer and the Nth adhesion layer.
The present invention also provides a semiconductor structure comprising: the substrate is positioned on the zeroth metal layer in the substrate; the first adhesive layer is positioned on the surface of the substrate, and the first porous medium layer is positioned on the surface of the first adhesive layer, and the Young modulus of the first adhesive layer is greater than that of the first porous medium layer; a first opening positioned in the first porous medium layer and the first adhesion layer, wherein the bottom of the first opening is exposed out of the surface of the zeroth metal layer; and filling the first metal layer of the first opening, wherein the top surface of the first metal layer is flush with the top surface of the first porous medium layer.
Optionally, the relative dielectric constant of the material of the first porous medium layer is 2.5 to 2.6, the young modulus of the first porous medium layer is 7.8Gpa to 8.2Gpa, and the young modulus of the first adhesion layer is greater than 70 Gpa.
Optionally, the method further includes: the Nth adhesion layer is positioned on the surface of the (N-1) (N is more than or equal to 2) th porous medium layer, and the Nth porous medium layer is positioned on the surface of the Nth adhesion layer; the Nth opening is positioned in the Nth porous dielectric layer and the Nth adhesion layer, and the bottom of the Nth opening is exposed out of the surface of the (N-1) th metal layer; and filling the Nth metal layer of the Nth opening, wherein the top surface of the Nth metal layer is flush with the top surface of the Nth porous medium layer.
Optionally, a first stop layer is formed between the substrate and the first adhesion layer, and an nth stop layer is formed between the nth-1 porous medium layer and the nth adhesion layer.
The invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein a zeroth metal layer is formed in the substrate; forming a first porous medium layer on the surface of the substrate; carrying out first ultraviolet irradiation on the first porous medium layer to improve the Young modulus of the first porous medium layer; forming a first mask layer on the surface of the first porous medium layer, wherein the first mask layer is internally provided with a first groove exposing the surface of the first porous medium layer, and the Young modulus of the first mask layer is larger than that of the first porous medium layer; etching the first porous dielectric layer by taking the first mask layer as a mask to form a first opening, wherein the bottom of the first opening is exposed out of the surface of a zeroth metal layer; forming a first metal layer which is filled in the first opening, wherein the first metal layer also covers the surface of the first mask layer; and removing the first metal layer higher than the top surface of the first mask layer and the first mask layer with partial thickness, wherein the first metal layer is flush with the top surface of the remaining first mask layer.
Optionally, the first mask layer is made of silicon oxide, and the young modulus of the first mask layer is greater than 70 Gpa.
Optionally, the method further comprises the steps of: forming an Nth porous medium layer on the surface of the Nth-1 (N is more than or equal to 2) th mask layer; carrying out Nth ultraviolet irradiation on the Nth porous medium layer to improve the Young modulus of the Nth porous medium layer; forming an Nth mask layer on the surface of the Nth porous dielectric layer, wherein an Nth groove exposing the surface of the Nth porous dielectric layer is formed in the Nth mask layer, and the Young modulus of the Nth mask layer is larger than that of the Nth porous dielectric layer; etching the Nth porous dielectric layer by taking the Nth mask layer as a mask to form an Nth opening, wherein the bottom of the Nth opening is exposed out of the surface of the (N-1) th metal layer; forming an Nth metal layer filling the Nth opening, wherein the Nth metal layer is covered on the surface of the Nth mask layer; and removing the Nth metal layer higher than the top surface of the Nth mask layer and the Nth mask layer with partial thickness, wherein the Nth metal layer is flush with the top surface of the residual Nth mask layer.
Optionally, the method further comprises the steps of: forming a first stop layer between the substrate and a first porous medium layer; and forming an Nth stop layer between the N-1 th mask layer and the Nth porous medium layer.
The present invention also provides a semiconductor structure comprising: the substrate is positioned on the zeroth metal layer in the substrate; the first porous medium layer is positioned on the surface of the zeroth metal layer; the first mask layer is positioned on the surface of the first porous medium layer, and the Young modulus of the first mask layer is larger than that of the first porous medium layer; a first opening located in the first mask layer and the first porous medium layer, wherein the bottom of the first opening is exposed out of the surface of the zeroth metal layer; and filling the first metal layer of the first opening, wherein the top surface of the first metal layer is flush with the top surface of the first mask layer.
Optionally, the method further includes: the Nth porous medium layer is positioned on the surface of the Nth-1 (N is more than or equal to 2) th mask layer; the Nth mask layer is positioned on the surface of the Nth porous medium layer, and the Young modulus of the Nth mask layer is larger than that of the Nth porous medium layer; an Nth opening positioned in the Nth mask layer and the Nth porous medium layer, wherein the Nth opening is exposed out of the surface of the (N-1) th metal layer; and filling the Nth metal layer of the Nth opening, wherein the top surface of the Nth metal layer is flush with the top surface of the Nth mask layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the invention provides a method for forming a semiconductor structure, which comprises the steps of forming a first adhesion layer on the surface of a substrate before forming a first porous medium layer, wherein the first adhesion layer plays a role in improving the adhesion between the substrate and the first porous medium layer; in addition, the Young modulus of the first adhesion layer is larger than that of the first porous medium layer, so that the Young modulus of the semiconductor structure is remarkably improved, the mechanical strength of the semiconductor structure is improved, and the reliability of the semiconductor structure is improved. Meanwhile, the embodiment of the invention also carries out first ultraviolet irradiation on the first porous medium layer, thereby improving the Young modulus of the first porous medium layer, improving the mechanical strength of the first porous medium layer, preventing the first porous medium layer from cracking and further improving the reliability of the semiconductor structure.
The embodiment of the invention also provides a method for forming the semiconductor structure, wherein the first mask layer is formed on the surface of the first porous medium layer, the Young modulus of the first mask layer is larger than that of the first porous medium layer, and after the first metal layer is formed, the first mask layer with partial thickness is reserved, so that the Young modulus of the semiconductor structure is improved, the mechanical strength of the semiconductor structure is improved, and the reliability of the semiconductor structure is improved. Meanwhile, the first mask layer can also play a role in improving the adhesion between the first porous medium layer and the second stop layer formed subsequently.
Further, after the first ultraviolet irradiation, the relative dielectric constant of the material of the first porous dielectric layer is 2.5-2.6, and the relative dielectric constant of the material of the first porous dielectric layer is reduced while the Young modulus of the first porous dielectric layer is increased, so that the RC delay effect of the semiconductor structure is reduced, and the electrical property of the semiconductor structure is optimized.
An embodiment of the present invention further provides a semiconductor structure with superior structural performance, including: the semiconductor structure comprises a first adhesion layer and a first porous medium layer, wherein the first adhesion layer is positioned on the surface of a substrate, the first porous medium layer is positioned on the surface of the first adhesion layer, the first adhesion layer plays a role in improving adhesion between the substrate and the first porous medium layer, and the Young modulus of the first adhesion layer is larger than that of the first porous medium layer, so that compared with the prior art, the Young modulus of the semiconductor structure provided by the embodiment of the invention is larger, the mechanical strength of the semiconductor structure is stronger, and the reliability of the semiconductor structure is improved.
The embodiment of the invention also provides a semiconductor structure, which comprises a first mask layer positioned on the surface of the first porous medium layer, wherein the Young modulus of the first mask layer is greater than that of the first porous medium layer, so that the Young modulus of the semiconductor structure is increased, the mechanical strength of the semiconductor structure is improved, and the reliability of the semiconductor structure is improved.
Drawings
Fig. 1 to 11 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment;
fig. 12 to 15 are schematic cross-sectional views illustrating a semiconductor structure forming process according to another embodiment.
Detailed Description
As is known in the art, the electrical performance and reliability of the semiconductor structure formed by the prior art need to be improved.
Research on the formation method of the semiconductor structure has found that one of the main reasons for the poor electrical performance and reliability of the semiconductor structure is: in order to reduce the RC delay effect of the semiconductor structure, the dielectric layer material in the semiconductor structure is a low-k dielectric material. The low-k dielectric material mostly has a porous loose structure, so that the dielectric layer has a low young's modulus, which further results in a low mechanical strength of the semiconductor structure, and when the semiconductor structure is in some severe environments, for example, the semiconductor structure is squeezed in a packaging process, the problem of cracking or even delamination occurs in the semiconductor structure, which results in poor electrical performance and reliability of the semiconductor structure.
Moreover, because the low-k dielectric material has the characteristic of porosity and looseness, the Young modulus of the dielectric layer is low, and when the dielectric layer is placed in a plasma environment, the dielectric layer is easy to deform under the bombardment of plasma, for example, the volume of the dielectric layer shrinks by 5% to 10%; the dielectric layer volume shrinkage can cause significant internal stress effects that can also lead to cracking or delamination problems in the semiconductor structure.
From the above analysis, it is known that if the young's modulus of the dielectric layer and the overall young's modulus of the semiconductor structure can be improved, the problem of cracking or delamination in the semiconductor structure can be effectively avoided, and the electrical performance and reliability of the semiconductor structure can be improved.
Therefore, the invention provides a semiconductor structure and a forming method thereof, wherein the Young modulus of a first porous medium layer is improved by carrying out first ultraviolet irradiation on the first porous medium layer; and a first adhesion layer is formed at the bottom of the first porous medium layer, or a first mask layer is formed at the top of the first porous medium layer, and the Young modulus of the first adhesion layer and the Young modulus of the first mask layer are greater than that of the first porous medium layer, so that the overall Young modulus of the semiconductor structure is improved, the mechanical strength of the semiconductor structure is improved, and the reliability of the semiconductor structure is further improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 11 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the invention.
Referring to fig. 1, a substrate 200 is provided, a zeroth metal layer 201 is formed in the substrate 200, and a surface of the zeroth metal layer 201 is flush with a surface of the substrate 200.
The substrate 200 is made of one of monocrystalline Silicon, polycrystalline Silicon, and amorphous Silicon, the substrate 200 may also be made of Silicon germanium compound or Silicon On Insulator (SOI), and the substrate 200 may also be made of germanium, Silicon germanium, or gallium arsenide. The substrate 200 may have semiconductor devices such as NMOS transistors, PMOS transistors, CMOS transistors, capacitors, or resistors formed therein
In this embodiment, the zeroth metal layer 201 is used to connect with a first metal layer formed later. The material of the zeroth metal layer 201 is Cu, Al or W.
In this embodiment, the substrate 200 is a silicon substrate, and the material of the zeroth metal layer 201 is Cu.
Referring to fig. 2, a first stop layer 202 is formed on the surface of the substrate 200.
The first stop layer 202 functions as: on one hand, after the first porous medium layer is formed, the etching rate of the etching process to the first stop layer 202 is far less than the etching rate to the first porous medium layer, so that the etching stop function is achieved, and the over-etching of the substrate 200 is avoided; on the other hand, since the material of the zeroth metal layer 201 is Cu, the diffusion capability of Cu is strong, and after the first stop layer 202 is formed, the first stop layer 202 has an effect of blocking Cu from diffusing into the first porous medium layer.
The material of the first stop layer 202 is one or more of silicon nitride, carbon-doped silicon nitride, and carbon-doped silicon oxynitride. In order to minimize the relative permittivity of the semiconductor structure and reduce the RC delay of the semiconductor structure, a material having a smaller relative permittivity is used as the material of the first stop layer 202. Compared with silicon Nitride and Carbon-Doped silicon oxynitride, the relative dielectric constant of silicon carbide Nitride (NDC) is small, and therefore, in the embodiment, the material of the first stop layer 202 is silicon carbide Nitride, and the thickness of the first stop layer 202 is 100 to 500 angstroms.
As an embodiment, the first stop layer 202 is formed by a chemical vapor deposition process, and the process parameters of the chemical vapor deposition process are: the reaction gas comprises silane gas, nitrogen source gas and He, the flow rate of the silane gas is 200sccm to 2000sccm, the flow rate of the nitrogen source gas is 200sccm to 1000sccm, the flow rate of the He is 500sccm to 10000sccm, the low-frequency radio frequency power of the deposition chamber is 0 watt to 1000 watts, the high-frequency radio frequency power of the deposition chamber is 500 watt to 1500 watts, the temperature of the deposition chamber is 200 ℃ to 400 ℃, and the pressure of the deposition chamber is 1 Torr to 20 Torr.
Wherein the silane gas is trimethylsilane ((CH)3)3SiH, 3MS) or tetramethylsilane ((CH)3)4Si, 4MS), and NH is used as nitrogen source gas3Or N2One or two of them.
With continued reference to fig. 2, a first adhesive layer 203 and a first porous medium layer 204 on the surface of the first adhesive layer 203 are formed on the surface of the first stop layer 202, and the young's modulus of the first adhesive layer 203 is greater than the young's modulus of the first porous medium layer 204.
Because the material of the first stop layer 202 is silicon carbonitride doped with carbon, the material of the first porous medium layer 204 is porous and loose, and the material of the first porous medium layer 204 contains more silicon, oxygen atoms and carbon atoms; if the first porous medium layer 204 is directly formed on the surface of the first stop layer 202, due to the large difference between the lattice constants of the material of the first porous medium layer 204 and the material of the first stop layer 202, lattice defects may be generated at the interface between the first porous medium layer 204 and the first stop layer 202, so that the adhesion between the first porous medium layer 204 and the first stop layer 202 is poor, and the adhesion between the first porous medium layer 204 and the substrate 200 is poor.
For this reason, the present embodiment forms the first adhesive layer 203 on the surface of the first stopper layer 202 before forming the first porous medium layer 204. The lattice constants of the material of the first adhesion layer 203 and the material of the first stop layer 202 are as close as possible, so that lattice defects at the interface of the first adhesion layer 203 and the first stop layer 202 are reduced, and the adhesion between the first adhesion layer 203 and the first stop layer 202 is improved; similarly, the lattice constants of the materials of the first adhesion layer 203 and the first porous medium layer 204 are as close as possible, so that lattice defects at the interface between the first adhesion layer 203 and the first porous medium layer 204 are reduced, the adhesion between the first adhesion layer 203 and the first porous medium layer 204 is strong, and the bonding capability between the first porous medium layer 204 and the first stop layer 202 is strong.
In addition, in the present embodiment, the young's modulus of the first adhesive layer 203 is larger than the young's modulus of the first porous dielectric layer 204, so that the young's modulus of the whole semiconductor structure is improved to a certain extent, the mechanical strength of the semiconductor structure is improved, and the reliability of the semiconductor structure is further improved.
In consideration of the above factors, the material of the first adhesion layer 203 in this embodiment is silicon oxide, and the young's modulus of the first adhesion layer 203 is greater than 70 Gpa. As a specific embodiment, the thickness of the first adhesion layer 203 is 30 to 300 angstroms.
The first adhesion layer 203 is formed using a chemical vapor deposition or atomic layer deposition process. As a specific embodiment, the process parameters for forming the first adhesion layer 203 by using the chemical vapor deposition process are as follows: the reaction gas comprises a silicon source and an oxygen source gas, the flow rate of the silicon source is 50sccm to 2000sccm or 1g/m to 30g/m, the flow rate of the oxygen source gas is 20 sccm to 1000sccm, the reaction gas further comprises He, the flow rate of the He is 50sccm to 1000sccm, the pressure of the deposition chamber is 0.1 Torr to 10 Torr, the radio frequency power of the deposition chamber is 100 watts to 5000 watts, and the temperature of the deposition chamber is 250 ℃ to 400 ℃.
Wherein the silicon source is methyldiethoxysilane ((CH)3CH2O)2HCH3Si, DEMS), octamethylcyclotetrasiloxane (C)8H24O4Si4) Or tetraethoxysilane (C)8H20O4Si, TEOS); the oxygen source gas is oxygen. When the silicon source is gasIn the state, the unit of the silicon source is sccm, which refers to standard condition milliliter per minute; when the silicon source is in a liquid state, the unit of the silicon source is g/m, which means grams per minute.
The relative dielectric constant of the material of the first porous medium layer 204 is 2.71-2.79, and the Young modulus of the first porous medium layer 204 is 5.8 Gpa-6.2 Gpa; the material of the first porous medium layer 204 is a porous material containing methyl groups. As a specific embodiment, the material of the first porous dielectric layer 204 is porous SiCOH, and the thickness of the first porous dielectric layer 204 is 1000 angstroms to 8000 angstroms.
Because the first adhesion layer 203 is made of silicon oxide and the lattice constant difference between porous SiCOH and silicon oxide is small, lattice defects at the interface between the first porous dielectric layer 204 and the first adhesion layer 203 are few, so that the first porous dielectric layer 204 and the first adhesion layer 203 are tightly bonded, the first porous dielectric layer 204 is difficult to delaminate or even separate from the first stop layer 202, the adhesion between the first porous dielectric layer 204 and the substrate 200 is improved, and the yield of semiconductor production is improved.
In order to improve the production efficiency of the semiconductor, the first dielectric layer 204 and the first adhesive layer 203 are formed in the same reaction chamber, so that the first adhesive layer 203 is prevented from being polluted when being placed in the external environment, and the surface of the first adhesive layer 203 is kept clean.
As an embodiment, the first porous dielectric layer 204 is formed by a chemical vapor deposition process, and the process parameters of the chemical vapor deposition process are as follows: the reaction raw materials comprise silane and oxygen source gas, wherein the silane is one or two of methyldiethoxysilane or octamethylcyclotetrasiloxane, and the oxygen source gas is O2The flow rate of silane is 0.2g/m to 2g/m, the flow rate of oxygen source gas is 50sccm to 1000sccm, the temperature of a deposition chamber is 200 ℃ to 400 ℃, the pressure of the deposition chamber is 1 Torr to 20 Torr, the power of the deposition chamber is 100W to 1000W, a pore-forming agent is introduced into the chamber, and the flow rate of the pore-forming agent is 100sccm to 3000 sccm.
Referring to fig. 3, the first porous medium layer 204 is subjected to a first ultraviolet irradiation 205 to increase the young's modulus of the first porous medium layer 204.
During the first ultraviolet irradiation 205, methyl groups in the first porous dielectric layer 204 escape from the first porous dielectric layer 204, so that the number of methyl groups in the first porous dielectric layer 204 is reduced, Si-Si crosslinking in the first porous dielectric layer 204 is promoted, and more stable Si-Si bonds and Si-H bonds in the first porous dielectric layer 204 are increased, thereby increasing the young modulus of the first porous dielectric layer 204, improving the mechanical strength of the first porous dielectric layer 204, and further improving the mechanical strength of the semiconductor structure.
As a specific embodiment, the process parameters of the first ultraviolet irradiation 205 are: the irradiation power is 1000W to 6000W, the irradiation time is 2 minutes to 6 minutes, and the ultraviolet wavelength is 200 nanometers to 350 nanometers.
After the first ultraviolet irradiation 205 is performed, the relative dielectric constant of the material of the first porous medium layer 204 is 2.5 to 2.6, and the young's modulus of the first porous medium layer 204 is 7.8Gpa to 8.2 Gpa. Not only is the Young's modulus of the first porous dielectric layer 204 increased after the first ultraviolet irradiation 205 as compared to before the first ultraviolet irradiation 205, but the relative dielectric constant of the material of the first porous dielectric layer 204 is also reduced, so that the RC delay effect of the semiconductor structure is reduced.
Referring to fig. 4, a first mask layer 206 is formed on the surface of the first porous dielectric layer 204 after the first ultraviolet irradiation 205.
The first mask layer 206 serves as a partial mask for forming the first opening, and also serves to protect the first porous dielectric layer 204 in a subsequent chemical mechanical polishing process, so that the first porous dielectric layer 204 is prevented from being damaged by the chemical mechanical polishing process.
The first mask layer 206 has a single-layer structure or a stacked-layer structure. The material of the first mask layer 206 is silicon oxide, carbon-containing silicon oxide, silicon oxynitride, or a metal material.
In the embodiment, the first mask layer 206 is exemplarily illustrated as a single-layer structure, the material of the first mask layer 206 is silicon nitride, and the thickness of the first mask layer 206 is 100 angstroms to 1000 angstroms.
Referring to fig. 5, a first groove 207 is formed in the first mask layer 206, and the bottom of the first groove 207 exposes the surface of the first porous dielectric layer 204.
The forming process of the first groove 207 is as follows: forming a first photoresist layer on the surface of the first mask layer 206, and performing a photolithography process (including exposure, development, and the like) on the first photoresist layer to form a patterned first photoresist layer; etching the first mask layer 206 by using the patterned photoresist layer as a mask until the surface of the first porous dielectric layer 204 is exposed, and forming a first groove 207 in the first mask layer 206; and removing the patterned first photoresist layer.
The first recess 207 defines the location and width of the subsequently formed trench.
Referring to fig. 6, a second photoresist layer 209 having a second groove 208 is formed on the surface of the first mask layer 206 and the surface of the first porous dielectric layer 204, wherein the width of the second groove 208 is smaller than the width of the first groove 207 (see fig. 5), and the bottom of the second groove 208 exposes the surface of the first porous dielectric layer 204.
The position and width of the second recess 208 define the position and width of the subsequently formed via.
Referring to fig. 7, the second photoresist layer 209 (see fig. 6) is used as a mask to etch and remove a part of the thickness of the first porous dielectric layer 204, thereby forming a through hole (not labeled); the second photoresist layer 209 is removed.
Specifically, a dry etching process is used to etch and remove a portion of the thickness of the first porous dielectric layer 204 along the second groove 208 (see fig. 6).
In this embodiment, the first porous dielectric layer 204 is subjected to the first ultraviolet irradiation 205, so that the young's modulus of the first porous dielectric layer 204 is improved, and therefore, in the dry etching process, the volume shrinkage of the first porous dielectric layer 204 is significantly reduced.
Referring to fig. 8, the first mask layer 206 is used as a mask to etch and remove a portion of the thickness of the first porous dielectric layer 204 and the first adhesion layer 203 to form a first opening 210, and the bottom of the first opening 210 exposes the surface of the zeroth metal layer 201.
Specifically, a dry etching process is adopted to etch a part of the thickness of the first porous dielectric layer 204, the first adhesion layer 203 and the first stop layer 202 at the bottom of the through hole are removed by etching until the surface of the substrate 200 is exposed, a first opening 210 is formed in the first porous dielectric layer 204, the first adhesion layer 203 and the first stop layer 202, and the surface of the zeroth metal layer 201 is exposed at the bottom of the first opening 210.
The first opening 210 is formed by a trench (not labeled) and a via at the bottom of the trench (not labeled), and in this embodiment, the first opening 210 includes 2 vias.
In the present embodiment, the first opening 210 is exemplified as a dual damascene opening, and the first opening 210 is formed in the order of forming a via hole first and then forming a trench; in other embodiments, the trench may be formed first and then the through holes may be formed, and the number of the through holes may be determined according to the actual process requirement. In other embodiments, the first opening 210 may also be a single damascene opening.
Referring to fig. 9, a first metal layer 211 is formed to fill the first opening 210 (see fig. 8), and the first metal layer 211 covers the surface of the first mask layer 206.
The first metal layer 211 has a single-layer structure or a stacked structure. When the first metal layer 211 is a single-layer structure, the first metal layer 211 includes a first metal layer filling the first opening 210; when the first metal layer 211 is a stacked structure, the first metal layer 211 includes a first seed layer located at the bottom and the sidewall of the first opening 210 and a first metal layer located on the surface of the first seed layer, and the first opening 210 is filled with the first metal layer.
The material of the first metal layer 211 is Cu, Al, or W.
Referring to fig. 10, the first metal layer 211 above the surface of the first mask layer 206 (see fig. 9) is removed; the first mask layer 206 is removed and the top surface of the first metal layer 211 is flush with the top surface of the first porous dielectric layer 204.
In this embodiment, the first metal layer 211 higher than the surface of the first mask layer 206 is removed by using a chemical mechanical polishing process, and the first mask layer 206 is removed by using the chemical mechanical polishing process until the surface of the first porous dielectric layer 204 is exposed.
Referring to fig. 11, a second adhesion layer 303 and a second porous medium layer 304 on the surface of the second adhesion layer 303 are formed on the surface of the first porous medium layer 204; performing second ultraviolet irradiation on the second porous medium layer 304 to improve the Young modulus of the second porous medium layer 304; etching the second porous dielectric layer 304 and the second adhesion layer 303 to form a second opening, wherein the bottom of the second opening is exposed out of the surface of the first metal layer 211; forming a second metal layer 311 filling the second opening, wherein the top surface of the second metal layer 311 is flush with the top surface of the second porous medium layer 304; forming a third adhesion layer 403 on the surface of the second porous medium layer 304 and a third porous medium layer 404 on the surface of the third adhesion layer 403; performing third ultraviolet irradiation on the third porous medium layer 404 to improve the Young modulus of the third porous medium layer 404; etching the third porous dielectric layer 404 and the third adhesion layer 403 to form a third opening, wherein the bottom of the third opening exposes the surface of the second metal layer 311; and forming a third metal layer 411 which is filled in the third opening, wherein the top surface of the third metal layer 411 is flush with the top surface of the third porous medium layer 404.
Further comprising the steps of: forming a first stop layer 202 between the substrate 200 and the first adhesive layer 203; forming a second stop layer 302 between the first porous medium layer 204 and the second adhesive layer 303; a third stop layer 402 is formed between the second porous medium layer 304 and the third adhesion layer 403.
For the descriptions of the second stop layer 302, the third stop layer 402, the second adhesion layer 303, the third adhesion layer 403, the second porous medium layer 304, the third porous medium layer 404, the second ultraviolet radiation, the third ultraviolet radiation, the second opening, the third opening, the second metal layer 311, and the third metal layer 411, reference may be made to the foregoing description, and no further description is given here.
In other embodiments, further comprising the step of: forming an Nth adhesion layer on the surface of the (N-1) (N is more than or equal to 2) th porous medium layer and an Nth porous medium layer positioned on the surface of the Nth adhesion layer; carrying out Nth ultraviolet irradiation on the Nth porous medium layer to improve the Young modulus of the Nth porous medium layer; etching the Nth porous dielectric layer and the Nth adhesion layer to form an Nth opening, wherein the bottom of the Nth opening is exposed out of the surface of the (N-1) th metal layer; and forming an Nth metal layer filled in the Nth opening, wherein the top surface of the Nth metal layer is flush with the top surface of the Nth porous medium layer.
Further comprising the steps of: forming a first stop layer between the substrate and the first adhesion layer; and forming an Nth stop layer between the N-1 th porous medium layer and the Nth adhesion layer.
The present embodiment is exemplified by N ═ 3. In other embodiments, N may be any natural number greater than or equal to 2, such as 2, 5, 6, 8, etc.
The first ultraviolet radiation increases the Young's modulus of the first porous dielectric layer 204, the second ultraviolet radiation increases the Young's modulus of the second porous dielectric layer 304, and the third ultraviolet radiation increases the Young's modulus of the third porous dielectric layer 404, thereby increasing the overall Young's modulus of the semiconductor structure and increasing the mechanical strength of the semiconductor structure. And the Young's moduli of the first adhesion layer 203, the second adhesion layer 303 and the third adhesion layer 403 are larger than the Young's moduli of the first porous medium layer 204, the second porous medium layer 304 and the third porous medium layer 404, so that the overall Young's modulus of the semiconductor structure is further improved, and the mechanical strength of the semiconductor structure is improved.
Meanwhile, the formation of the first adhesion layer 203 improves the adhesion between the first stop layer 202 and the first porous medium layer 204, the formation of the second adhesion layer 303 improves the adhesion between the second stop layer 302 and the second porous medium layer 304, and the formation of the third adhesion layer 403 improves the adhesion between the third stop layer 402 and the third porous medium layer 404, thereby further improving the reliability of the semiconductor structure.
Accordingly, the present embodiment provides a semiconductor structure, referring to fig. 11, the semiconductor structure includes:
a substrate 200, a zeroth metal layer 201 located in the substrate 200;
the first adhesive layer 203 is positioned on the surface of the substrate 200, and the first porous medium layer 204 is positioned on the surface of the first adhesive layer 203, and the Young modulus of the first adhesive layer 203 is larger than that of the first porous medium layer 204;
a first opening located in the first porous medium layer 204 and the first adhesion layer 203, and the bottom of the first opening exposes the surface of the zeroth metal layer 201;
the first metal layer 211 is filled in the first opening, and the top surface of the first metal layer 211 is flush with the top surface of the first porous medium layer 204.
The relative dielectric constant of the material of the first porous medium layer 204 is 2.5-2.6, the Young modulus of the first porous medium layer 204 is 7.8 Gpa-8.2 Gpa, and the Young modulus of the first adhesion layer 203 is more than 70 Gpa.
The present embodiment forms a first stop layer 202 between the substrate 200 and a first adhesive layer 203. The first stop layer 202 is made of silicon nitride, silicon nitride doped with carbon, or silicon oxynitride.
The first adhesion layer 203 is made of silicon oxide, so that the adhesion between the first etching stop layer 202 and the first porous medium layer 204 can be improved; in addition, since the young's modulus of the first adhesive layer 203 is greater than the young's modulus of the first porous medium layer 204, the first adhesive layer 203 can also improve the young's modulus of the semiconductor structure, improve the mechanical strength of the semiconductor structure, and improve the reliability of the semiconductor structure.
Further comprising: the Nth adhesion layer is positioned on the surface of the (N-1) (N is more than or equal to 2) th porous medium layer, and the Nth porous medium layer is positioned on the surface of the Nth adhesion layer; the Nth opening is positioned in the Nth porous dielectric layer and the Nth adhesion layer, and the bottom of the Nth opening is exposed out of the surface of the (N-1) th metal layer; and filling the Nth metal layer of the Nth opening, wherein the top surface of the Nth metal layer is flush with the top surface of the Nth porous medium layer. Further comprising: an Nth stop layer is formed between the Nth-1 porous medium layer and the Nth adhesion layer.
In this embodiment, taking N-3 as an example for illustration, the semiconductor structure further includes: a second adhesive layer 303 positioned on the surface of the first porous medium layer 204, and a second porous medium layer 304 positioned on the surface of the second adhesive layer 303; a second opening located in the second porous dielectric layer 304 and the second adhesion layer 303, and the bottom of the second opening exposes the surface of the first metal layer 211; the second metal layer 311 is filled in the second opening, and the top surface of the second metal layer 311 is flush with the top surface of the second porous medium layer 304; a third adhesion layer 403 positioned on the surface of the second porous medium layer 304, and a third porous medium layer 404 positioned on the surface of the third adhesion layer 403; a third opening located in the third porous dielectric layer 404 and the third adhesion layer 403, and the bottom of the third opening exposes the surface of the second metal layer 311; and the third metal layer 411 is filled in the third opening, and the top surface of the third metal layer 411 is flush with the top surface of the third porous medium layer 404.
Further comprising: a second stop layer 302 is formed between the first porous medium layer 204 and the second adhesion layer 303; a third stop layer 402 is formed between the second porous medium layer 304 and the third adhesive layer 403.
Fig. 12 to 15 are schematic cross-sectional views illustrating a semiconductor structure forming process according to another embodiment of the invention.
Referring to fig. 12, a substrate 200 is provided, wherein a zeroth metal layer 201 is formed in the substrate 200; forming a first porous medium layer 204 on the surface of the substrate 200; performing first ultraviolet irradiation on the first porous medium layer 204 to improve the Young modulus of the first porous medium layer 204; a first mask layer 206 is formed on the surface of the first porous dielectric layer 204, a first groove exposing the surface of the first porous dielectric layer 204 is formed in the first mask layer 206, and the young modulus of the first mask layer 206 is greater than the young modulus of the first porous dielectric layer 204.
Further comprising the steps of: a first stop layer 202 is formed between the substrate 200 and a first porous media layer 204.
For the description of the substrate 200, the zeroth metal layer 201, the first stop layer 202, the first porous medium layer 204 and the first ultraviolet radiation, reference may be made to the foregoing embodiments, and further description is omitted here.
In this embodiment, the first mask layer 206 serves as a mask for forming a first opening later, and the first mask layer 206 with a thickness of a part of the surface of the first porous dielectric layer 204 is remained later, so as to improve the adhesion between the first porous dielectric layer 204 and a second stop layer formed later; in addition, the young's modulus of the first mask layer 206 is greater than that of the first porous medium layer 204, so that the young's modulus of the semiconductor structure is improved, the mechanical strength of the semiconductor structure is improved, and the reliability of the semiconductor structure is improved.
In this embodiment, the first mask layer 206 is made of silicon oxide, the thickness of the first mask layer 206 is 500 to 5000 angstroms, and the young modulus of the first mask layer 206 is greater than 70 Gpa. After the first ultraviolet irradiation, the relative dielectric constant of the material of the first porous medium layer 204 is 2.5 to 2.6, and the young modulus of the first porous medium layer 204 is 7.8Gpa to 8.2 Gpa.
Since the first mask layer 206 is made of silicon oxide, the first mask layer 206 further contains hydrogen atoms, the first porous dielectric layer 204 is made of porous SiCOH, and lattice constants of the first mask layer 206 and the first porous dielectric layer 204 are relatively close to each other, the first mask layer 206 and the first porous dielectric layer 204 have good adhesion.
Referring to fig. 13, the first mask layer 206 is used as a mask to etch and remove a part of the thickness of the first porous dielectric layer 204; forming a second photoresist layer with a second groove on the surface of the first mask layer 206 and the surface of the etched first porous medium layer 204, wherein the width of the second groove is smaller than that of the first groove; continuously etching the first porous dielectric layer 204 by taking the second photoresist layer as a mask to form a first opening, wherein the bottom of the first opening is exposed out of the surface of the zeroth metal layer 201; removing the second photoresist layer; a first metal layer 211 is formed to fill the first opening, and the first metal layer 211 covers the surface of the first mask layer 206.
For the description of the first opening and the first metal layer 211, reference may be made to the foregoing embodiments, and further description is omitted here.
Referring to fig. 14, the first metal layer 211 higher than the top surface of the first mask layer 206 and a portion of the thickness of the first mask layer 206 are removed, and the first metal layer 211 is flush with the top surface of the remaining first mask layer 206.
In this embodiment, a chemical mechanical polishing process is used to grind and remove the first metal layer 211 on the top surface of the first mask layer 206 until the top surface of the first mask layer 206 is exposed; the first mask layer 206 and the first metal layer 211 are removed by polishing, and the first metal layer 211 is flush with the top surface of the remaining first mask layer 206.
As a specific example, the thickness of the remaining first mask layer 206 is 30 a to 300 a.
In the chemical mechanical polishing process, the surface of the first porous dielectric layer 204 is always covered by the first mask layer 206, so that the surface of the first porous dielectric layer 204 is prevented from being ground, thereby preventing the chemical mechanical polishing process from causing adverse effects on the first porous dielectric layer 204 and keeping the first porous dielectric layer 204 with good quality.
Referring to fig. 15, a second porous medium layer 304 is formed on the surface of the remaining first mask layer 206; performing second ultraviolet irradiation on the second porous medium layer 304 to improve the Young modulus of the second porous medium layer 304; forming a second mask layer 306 on the surface of the second porous dielectric layer 304, wherein a second groove exposing the surface of the second porous dielectric layer 304 is formed in the second mask layer 306, and the young modulus of the second mask layer 306 is greater than that of the second porous dielectric layer 304; etching the second porous dielectric layer 304 by using the second mask layer 306 as a mask to form a second opening, wherein the bottom of the second opening is exposed out of the surface of the first metal layer 211; forming a second metal layer 311 filling the second opening, wherein the second metal layer 311 also covers the surface of the second mask layer 306; removing the second metal layer 311 higher than the top surface of the second mask layer 306 and a part of the thickness of the second mask layer 306, wherein the second metal layer 311 is flush with the top surface of the remaining second mask layer 306; forming a third porous medium layer 404 on the surface of the remaining second mask layer 306; performing third ultraviolet irradiation on the third porous medium layer 404 to improve the Young modulus of the third porous medium layer 404; forming a third mask layer 406 on the surface of the third porous dielectric layer 404, wherein the Young modulus of the third mask layer 406 is larger than that of the third porous dielectric layer 404; etching the third porous dielectric layer 404 by using the third mask layer 406 as a mask to form a third opening, wherein the bottom of the third opening is exposed out of the surface of the second metal layer 311; forming a third metal layer 411 filling the third opening; the third metal layer 411 higher than the top surface of the third mask layer 406 and a part of the thickness of the third mask layer 406 are removed, and the third metal layer 411 is flush with the top surface of the remaining third mask layer 406.
In this embodiment, the method further includes the steps of: forming a second stop layer 302 between the first mask layer 206 and a second porous dielectric layer 304; a third stop layer 402 is formed between the second mask layer 306 and a third porous dielectric layer 404.
The material of the first mask layer 206 is silicon oxide, the material of the second stop layer 302 is silicon nitride, silicon carbide or silicon nitride doped with carbon, and the difference between the lattice constants of the second stop layer 302 and the first mask layer 206 is small, so that the adhesion between the second stop layer 302 and the first mask layer 206 is strong, thereby improving the adhesion between the second stop layer 302 and the first porous dielectric layer 204, and similarly, the adhesion between the third stop layer 402 and the second porous dielectric layer 404 is also improved, thereby improving the adhesion between layers in the semiconductor structure and improving the reliability of the semiconductor structure.
In addition, in the embodiment, by the method of retaining the first mask layer 206, the second mask layer 306, and the third mask layer 406 with partial thicknesses, the adhesion between layers of the semiconductor structure is improved, and no process step is added, so that the cost of the semiconductor structure forming process is low.
Because both the second porous dielectric layer 304 and the third porous dielectric layer 404 have undergone ultraviolet irradiation, the young's modulus of the second porous dielectric layer 304 and the third porous dielectric layer 404 is improved; in addition, due to the remaining thickness of the first mask layer 206, the second mask layer 306 and the third mask layer 406, the young's modulus of the formed semiconductor structure is further improved, and the mechanical strength of the semiconductor structure is improved.
Further comprising the steps of: forming an Nth porous medium layer on the surface of the Nth-1 (N is more than or equal to 2) th mask layer; carrying out Nth ultraviolet irradiation on the Nth porous medium layer to improve the Young modulus of the Nth porous medium layer; forming an Nth mask layer on the surface of the Nth porous dielectric layer, wherein the Nth mask layer is internally provided with an Nth through hole exposing the surface of the Nth porous dielectric layer, and the Young modulus of the Nth mask layer is larger than that of the Nth porous dielectric layer; etching the Nth porous dielectric layer by taking the Nth mask layer as a mask to form an Nth opening, wherein the bottom of the Nth opening is exposed out of the surface of the (N-1) th metal layer; forming an Nth metal layer filling the Nth opening, wherein the Nth metal layer is covered on the surface of the Nth mask layer; and removing the Nth metal layer higher than the top surface of the Nth mask layer and the Nth mask layer with partial thickness, wherein the Nth metal layer is flush with the top surface of the residual Nth mask layer.
Further comprising the steps of: and forming an Nth stop layer between the N-1 th mask layer and the Nth porous medium layer.
In the present embodiment, N is 3 as an example. In other embodiments, N may be any natural number greater than or equal to 2, 4, 5, 8, 10, etc.
Accordingly, the present embodiment further provides a semiconductor structure, referring to fig. 15, the semiconductor structure includes:
a substrate 200, a zeroth metal layer 201 located in the substrate 200;
the first porous medium layer 204 is positioned on the surface of the zeroth metal layer 201;
the first mask layer 206 is positioned on the surface of the first porous medium layer 204, and the Young modulus of the first mask layer 206 is larger than that of the first porous medium layer 204;
a first opening located in the first mask layer 206 and the first porous dielectric layer 204, wherein the bottom of the first opening is exposed out of the surface of the zeroth metal layer 201;
the first metal layer 211 filling the first opening is filled, and the top surface of the first metal layer 211 is flush with the top surface of the first mask layer 206.
The first mask layer 206 is made of silicon oxide, the thickness of the first mask layer 206 is 30 to 300 angstroms, and the young modulus of the first mask layer 206 is greater than 70 Gpa. The relative dielectric constant of the material of the first porous medium layer 204 is 2.5 to 2.6, and the Young's modulus of the first porous medium layer 204 is 7.8Gpa to 8.2 Gpa.
Because the young's modulus of the first mask layer 206 is greater than that of the first porous dielectric layer 204, compared with a semiconductor structure without the first mask layer 206, the young's modulus of the semiconductor structure provided by the embodiment is obviously improved, so that the mechanical strength of the semiconductor structure is improved, the problem that the semiconductor structure is cracked or even delaminated is prevented, and the reliability of the semiconductor structure is improved.
Further comprising: a second porous dielectric layer 304 on the surface of the first mask layer 206; the second mask layer 306 is positioned on the surface of the second porous medium layer 304, and the Young modulus of the second mask layer 306 is larger than that of the second porous medium layer 304; a second opening in the second mask layer 306 and the second porous dielectric layer 304, wherein the bottom of the second opening exposes the surface of the first metal layer 211; filling the second metal layer 311 in the second opening, wherein the top surface of the second metal layer 311 is flush with the top surface of the second mask layer 306; a third porous medium layer 404 on the surface of the second mask layer 305; a third mask layer 406 positioned on the surface of the third porous dielectric layer 404, wherein the Young modulus of the third mask layer 406 is larger than that of the third porous dielectric layer 404; a third opening located in the third mask layer 406 and the third porous dielectric layer 404, wherein the bottom of the third opening exposes the surface of the second metal layer 311; the third metal layer 411 is filled in the third opening, and the top surface of the third metal layer 411 is flush with the top surface of the third mask layer 406.
Further comprising: a first stop layer 202 is formed between the substrate 200 and the first porous medium layer 204; a second stop layer 302 is formed between the first mask layer 206 and the second porous medium layer 304; a third stop layer 402 is formed between the second mask layer 306 and a third porous dielectric layer 404.
The difference between the lattice constants of the materials of the first mask layer 206 and the first porous medium layer 204 is small, so that the adhesion between the first mask layer 206 and the first porous medium layer 204 is strong; and the difference between the lattice constants of the materials of the first mask layer 206 and the second stop layer 302 is small, so that the adhesion between the first mask layer 206 and the second stop layer 302 is strong; thereby enabling stronger adhesion between the second stop layer 302 and the first porous medium layer 204. Similarly, the third stop layer 403 has strong adhesion to the second porous medium layer 304, which improves the adhesion between layers in the semiconductor structure, thereby improving the reliability of the semiconductor structure.
Further comprising: the Nth porous medium layer is positioned on the surface of the Nth-1 (N is more than or equal to 2) th mask layer; the Nth mask layer is positioned on the surface of the Nth porous medium layer, and the Young modulus of the Nth mask layer is larger than that of the Nth porous medium layer; an Nth opening positioned in the Nth mask layer and the Nth porous medium layer, wherein the Nth opening is exposed out of the surface of the (N-1) th metal layer; and filling the Nth metal layer of the Nth opening, wherein the top surface of the Nth metal layer is flush with the top surface of the Nth mask layer.
Further comprising: an Nth stop layer is formed between the Nth mask layer and the Nth porous medium layer.
In the present embodiment, N is exemplified as 3, and in other embodiments, N may be any natural number greater than or equal to 2, such as 2, 4, 6, or 8.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a zeroth metal layer is formed in the substrate;
forming a first adhesion layer and a first porous medium layer positioned on the surface of the first adhesion layer on the surface of the substrate, wherein the Young modulus of the first adhesion layer is greater than that of the first porous medium layer;
carrying out first ultraviolet irradiation on the first porous medium layer, improving the Young modulus of the first porous medium layer, and simultaneously reducing the relative dielectric constant of the first porous medium layer;
etching the first porous medium layer and the first adhesion layer to form a first opening, wherein the bottom of the first opening is exposed out of the surface of the zeroth metal layer;
forming a first metal layer which is filled in the first opening, wherein the top surface of the first metal layer is flush with the top surface of the first porous medium layer;
after the first ultraviolet irradiation, the relative dielectric constant of the material of the first porous medium layer is 2.5-2.6, and the Young modulus of the first porous medium layer is 7.8 Gpa-8.2 Gpa.
2. The method of forming a semiconductor structure according to claim 1, wherein the first porous dielectric layer material has a relative dielectric constant of 2.71 to 2.79, and the first porous dielectric layer has a young's modulus of 5.8Gpa to 6.2 Gpa.
3. The method of forming a semiconductor structure of claim 2, wherein the first ultraviolet radiation comprises process parameters of: the irradiation power is 1000W to 6000W, the irradiation time is 2 minutes to 6 minutes, and the ultraviolet wavelength is 200 nanometers to 350 nanometers.
4. The method for forming a semiconductor structure according to claim 2, wherein the first porous dielectric layer is formed by a chemical vapor deposition process, and process parameters of the chemical vapor deposition process are as follows: the reaction raw materials comprise silane and oxygen source gas, wherein the silane is one or two of methyldiethoxysilane or octamethylcyclotetrasiloxane, and the oxygen source gas is O2Silane flow rate of 0.2g/m to 2g/m, oxygen source gasThe flow rate is 50sccm to 1000sccm, the temperature of the deposition chamber is 200 ℃ to 400 ℃, the pressure of the deposition chamber is 1 Torr to 20 Torr, the power of the deposition chamber is 100W to 1000W, and pore-forming agent is introduced into the chamber, wherein the flow rate of the pore-forming agent is 100sccm to 3000 sccm.
5. The method of forming a semiconductor structure of claim 1, wherein the first adhesion layer has a young's modulus greater than 70 Gpa.
6. The method of forming a semiconductor structure of claim 5, wherein the first adhesion layer is silicon oxide and has a thickness of 30 to 300 angstroms.
7. The method of claim 6, wherein the first adhesion layer is formed by a chemical vapor deposition process, and the process parameters of the chemical vapor deposition process are as follows: the reaction raw materials comprise a silicon source and oxygen source gas, wherein the silicon source is SiH4Or tetraethoxysilane, the flow rate of the silicon source is 100sccm to 2000sccm or 2g/m to 10g/m, the flow rate of the oxygen source gas is increased from zero to 500sccm, the pressure of the deposition chamber is 1 Torr to 10 Torr, the power of the deposition chamber is 100W to 1000W, and the temperature of the deposition chamber is 250 ℃ to 400 ℃.
8. The method of forming a semiconductor structure of claim 1, further comprising: forming an Nth adhesion layer on the surface of the (N-1) (N is more than or equal to 2) th porous medium layer and an Nth porous medium layer positioned on the surface of the Nth adhesion layer; carrying out Nth ultraviolet irradiation on the Nth porous medium layer to improve the Young modulus of the Nth porous medium layer; etching the Nth porous dielectric layer and the Nth adhesion layer to form an Nth opening, wherein the bottom of the Nth opening is exposed out of the surface of the (N-1) th metal layer; and forming an Nth metal layer filled in the Nth opening, wherein the top surface of the Nth metal layer is flush with the top surface of the Nth porous medium layer.
9. A method of forming a semiconductor structure as in claim 8 further comprising the steps of: forming a first stop layer between the substrate and the first adhesion layer; and forming an Nth stop layer between the N-1 th porous medium layer and the Nth adhesion layer.
10. A semiconductor structure formed by the method of any of claims 1 to 9, comprising:
the substrate is positioned on the zeroth metal layer in the substrate;
the first adhesive layer is positioned on the surface of the substrate, and the first porous medium layer is positioned on the surface of the first adhesive layer, and the Young modulus of the first adhesive layer is greater than that of the first porous medium layer;
a first opening positioned in the first porous medium layer and the first adhesion layer, wherein the bottom of the first opening is exposed out of the surface of the zeroth metal layer;
filling the first metal layer of the first opening, wherein the top surface of the first metal layer is flush with the top surface of the first porous medium layer;
the relative dielectric constant of the first porous medium layer material is 2.5-2.6, and the Young modulus of the first porous medium layer is 7.8-8.2 Gpa.
11. The semiconductor structure of claim 10, wherein the first adhesion layer has a young's modulus greater than 70 Gpa.
12. The semiconductor structure of claim 10, further comprising: the Nth adhesion layer is positioned on the surface of the (N-1) (N is more than or equal to 2) th porous medium layer, and the Nth porous medium layer is positioned on the surface of the Nth adhesion layer; the Nth opening is positioned in the Nth porous dielectric layer and the Nth adhesion layer, and the bottom of the Nth opening is exposed out of the surface of the (N-1) th metal layer; and filling the Nth metal layer of the Nth opening, wherein the top surface of the Nth metal layer is flush with the top surface of the Nth porous medium layer.
13. The semiconductor structure of claim 12, wherein a first stop layer is formed between the substrate and the first adhesion layer and an nth stop layer is formed between the N-1 porous dielectric layer and the nth adhesion layer.
14. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a zeroth metal layer is formed in the substrate;
forming a first porous medium layer on the surface of the substrate;
carrying out first ultraviolet irradiation on the first porous medium layer, improving the Young modulus of the first porous medium layer, and simultaneously reducing the relative dielectric constant of the first porous medium layer;
forming a first mask layer on the surface of the first porous medium layer, wherein the first mask layer is internally provided with a first groove exposing the surface of the first porous medium layer, and the Young modulus of the first mask layer is larger than that of the first porous medium layer;
etching the first porous dielectric layer by taking the first mask layer as a mask to form a first opening, wherein the bottom of the first opening is exposed out of the surface of a zeroth metal layer;
forming a first metal layer which is filled in the first opening, wherein the first metal layer also covers the surface of the first mask layer;
removing the first metal layer higher than the top surface of the first mask layer and the first mask layer with partial thickness, wherein the first metal layer is flush with the top surface of the remaining first mask layer;
after the first ultraviolet irradiation, the relative dielectric constant of the material of the first porous medium layer is 2.5-2.6, and the Young modulus of the first porous medium layer is 7.8 Gpa-8.2 Gpa.
15. The method of forming a semiconductor structure of claim 14, wherein the first mask layer is formed of silicon oxide, and the young's modulus of the first mask layer is greater than 70 Gpa.
16. The method of forming a semiconductor structure of claim 14, further comprising the steps of: forming an Nth porous medium layer on the surface of the Nth-1 (N is more than or equal to 2) th mask layer; carrying out Nth ultraviolet irradiation on the Nth porous medium layer to improve the Young modulus of the Nth porous medium layer; forming an Nth mask layer on the surface of the Nth porous dielectric layer, wherein an Nth groove exposing the surface of the Nth porous dielectric layer is formed in the Nth mask layer, and the Young modulus of the Nth mask layer is larger than that of the Nth porous dielectric layer; etching the Nth porous dielectric layer by taking the Nth mask layer as a mask to form an Nth opening, wherein the bottom of the Nth opening is exposed out of the surface of the (N-1) th metal layer; forming an Nth metal layer filling the Nth opening, wherein the Nth metal layer is covered on the surface of the Nth mask layer; and removing the Nth metal layer higher than the top surface of the Nth mask layer and the Nth mask layer with partial thickness, wherein the Nth metal layer is flush with the top surface of the residual Nth mask layer.
17. The method of forming a semiconductor structure of claim 16, further comprising the steps of: forming a first stop layer between the substrate and a first porous medium layer; and forming an Nth stop layer between the N-1 th mask layer and the Nth porous medium layer.
18. A semiconductor structure formed using the formation method of any of claims 14-17, comprising:
the substrate is positioned on the zeroth metal layer in the substrate;
the first porous medium layer is positioned on the surface of the zeroth metal layer;
the first mask layer is positioned on the surface of the first porous medium layer, and the Young modulus of the first mask layer is larger than that of the first porous medium layer;
a first opening located in the first mask layer and the first porous medium layer, wherein the bottom of the first opening is exposed out of the surface of the zeroth metal layer;
filling the first metal layer of the first opening, wherein the top surface of the first metal layer is flush with the top surface of the first mask layer;
the relative dielectric constant of the first porous medium layer material is 2.5-2.6, and the Young modulus of the first porous medium layer is 7.8-8.2 Gpa.
19. The semiconductor structure of claim 18, further comprising: the Nth porous medium layer is positioned on the surface of the Nth-1 (N is more than or equal to 2) th mask layer; the Nth mask layer is positioned on the surface of the Nth porous medium layer, and the Young modulus of the Nth mask layer is larger than that of the Nth porous medium layer; an Nth opening positioned in the Nth mask layer and the Nth porous medium layer, wherein the Nth opening is exposed out of the surface of the (N-1) th metal layer; and filling the Nth metal layer of the Nth opening, wherein the top surface of the Nth metal layer is flush with the top surface of the Nth mask layer.
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| JP2012004401A (en) * | 2010-06-18 | 2012-01-05 | Fujitsu Semiconductor Ltd | Method of manufacturing semiconductor device |
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| CN1487581A (en) * | 2002-09-03 | 2004-04-07 | ��ʽ���綫֥ | Semiconductor device |
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