CN105448702A - Semiconductor structure forming method - Google Patents
Semiconductor structure forming method Download PDFInfo
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- CN105448702A CN105448702A CN201410308794.8A CN201410308794A CN105448702A CN 105448702 A CN105448702 A CN 105448702A CN 201410308794 A CN201410308794 A CN 201410308794A CN 105448702 A CN105448702 A CN 105448702A
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Abstract
The invention discloses a semiconductor structure forming method, and the method comprises the steps: forming a substrate, and forming a first material layer, a second material layer and a third material layer on the substrate, wherein the second material layer covers at least a part of the surface of the substrate and the surface of a side wall of the first material layer, and the third material layer is aligned with the surface of the first material layer; forming a mask layer with a first opening which is exposed out of the surface of the first material layer and a part, covering the side wall of the first material layer, of the surface of the second material layer; etching the first and second material layers at certain thickness along the first opening, wherein the etching rate of the second material layer is greater than the etching rate of the first material layer; etching the mask layer, and forming a second opening, wherein the second opening enables the remaining part of the first material layer and the part, located on the surface of the side wall of the first material layer, of the second material layer to be completely exposed; carrying out the etching of the remaining parts of the first and second material layers along the second opening till the surface of the substrate, and forming a groove, wherein the side walls, located at two sides of the groove, of the third and second material layers are aligned with each other. The method can improve the performance of a formed semiconductor structure.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of semiconductor structure.
Background technology
MEMS (micro electro mechanical system) (MEMS, Micro-Electro-MechanicalSystem) is the manufacturing technology platform of a kind of advanced person.It grows up based on semiconductor fabrication.MEMS technology have employed a series of prior art and the material such as photoetching, burn into film in semiconductor technology, and along with the development of semiconductor technology, MEMS (micro electro mechanical system) have also been obtained and develops rapidly.
MEMS oscillator due to its integrated level high, stable performance, obtains and develops widely and apply.
In the process forming MEMS oscillator, semiconductor structure as described in Figure 1 can be formed.
Please refer to Fig. 1, described semiconductor structure comprises: substrate 10, be positioned at the first material layer 21 of cover part substrate 10 in substrate 10, cover the second material layer 22 of substrate 10 and the first material layer 21 sidewall, is positioned at the second material layer 22 surface and the 3rd material layer 23 flushed with described first material layer 21 surface.
The material of described first material layer 21 and the 3rd material layer 23 is SiGe, and the material of described second material layer 22 is Ge.
In the process forming described MEMS oscillator, need part second material layer 22 removed described first material layer 21 and be positioned at described first material layer 21 both sides sidewall surfaces, the second material layer 22 retaining described 3rd material layer 23 and be positioned at below the 3rd material layer 23.
Please refer to Fig. 2, form the mask layer 31 covering described 3rd material layer 23 surface.The method forming described mask layer 31 comprises: after described 3rd material layer 23, second material layer 22 and the first material layer 21 surface form mask layer, graphical photoresist layer 32 is formed on described mask layer surface, with described graphical photoresist layer 32 for mask layer described in mask etching, form mask layer 31, described mask layer 31 exposes the surface of the second material layer 22 of the first material layer 21 and described first material layer 21 sidewall surfaces.
Please refer to Fig. 3, with described mask layer 31 for mask, etch the second material layer 22 (please refer to Fig. 2) of described first material layer 21 (please refer to Fig. 2) and described first material layer 21 sidewall surfaces, form groove 33.Prior art is in etching process, the etch rate of described second material layer 22 is greater than the etch rate of the first material layer 21, so easily cause over etching to the second material layer 22 below the 3rd material layer 23, make part the 3rd material layer 23 unsettled, cause described 3rd material layer 23 easily to collapse.In follow-up cleaning process, also can cause further corrosion to the second material layer 22 below described 3rd material layer 23, make described 3rd material layer 23 that the problems such as stripping can occur, the performance of the final MEMS oscillator formed of impact.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor structure, improves the performance of the semiconductor structure formed.
For solving the problem, the invention provides a kind of formation method of semiconductor structure, comprise: substrate is provided, the 3rd material layer described substrate being formed with the first material layer of cover part substrate, being covered to the second material layer of small part substrate surface and the first material layer sidewall surfaces, being positioned at described second material surface, the surface of described 3rd material layer flushes with the surface of the first material layer; Form the mask layer with the first opening in described first material layer, the second material layer and the 3rd material surface, described first opening exposes the part surface of the second material layer of the first material surface and covering the first material layer sidewall; Along the first material layer and second material layer of described first opening etched portions thickness, the etch rate of described second material layer is greater than the etch rate of the first material layer; Etch described mask layer, the width of the first opening is increased, forms the second opening, described second opening exposes the second material layer of remaining first material layer and described first material layer sidewall surfaces completely; Along described second opening etching remaining first material layer and the second material layer to substrate surface, formed groove, the 3rd material layer of described groove both sides and the sidewall of the second material layer flush.
Optionally, the face width of the second material layer that described first opening exposes is 2/5 ~ 3/5 of the gross thickness of the second material layer of the first material layer sidewall surfaces.
Optionally, the face width of the second material layer that described first opening exposes is
Optionally, the formation method of semiconductor structure according to claim 1, it is characterized in that, after first material layer and the second material layer of the first opening etched portions thickness, the thickness of the first material layer after etching is 1/2 ~ 7/10 of the first layer thickness before etching.
Optionally, after first material layer and the second material layer of the first opening etched portions thickness, the thickness of part second material layer after etching is 3/10 ~ 1/2 of the second layer thickness before etching.
Optionally, the material of described first material layer is different from the material of the second material layer.
Optionally, the material of described first material layer is SiGe, and the material of the second material layer is Ge.
Optionally, dry etch process described first material layer of etching and the second material layer is adopted.
Optionally, described dry etch process adopts HBr and Cl
2mist as etching gas, O
2as buffer gas, wherein the flow of HBr is 135sccm ~ 165sccm, Cl
2flow be 100sccm ~ 140sccm, O
2flow be 5sccm ~ 15sccm, pressure is 5mTorr ~ 15mTorr, and power is 450W ~ 550W, and temperature is 50 DEG C ~ 80 DEG C, and bias voltage is 225V ~ 250V.
Optionally, the material of described mask layer is silica, silicon nitride, silicon oxynitride or amorphous carbon.
Optionally, the method forming described mask layer comprises: form mask layer in described first material layer, the second material layer and the 3rd material surface; The first graphical photoresist layer is formed on described mask layer surface; With the described first graphical photoresist layer for mask, etch described mask layer, form the mask layer with the first opening; Remove the described first graphical photoresist layer.
Optionally, the method forming described second opening comprises: form second graphical photoresist layer on described mask layer surface, described second graphical photoresist layer exposes the part mask layer of the second material surface on the first material layer and described first material layer sidewall; With described second graphical photoresist layer for mask, etch described mask layer, form the second opening.
Optionally, before first material layer and the second material layer of the first opening etched portions thickness, form second graphical photoresist layer on described mask layer surface.
Optionally, after first material layer and the second material layer of the first opening etched portions thickness, form second graphical photoresist layer on described mask layer surface.
Optionally, the material of described 3rd material layer is identical with the material of the first material layer.
Optionally, the material of described 3rd material layer is SiGe.
Compared with prior art, technical scheme of the present invention has the following advantages:
In technical scheme of the present invention, form the mask layer with the first opening in the first material layer of substrate surface, the second material layer and the 3rd material surface, described first opening exposes the first material surface and covers the part surface of the second material layer of the first material layer sidewall; Then along the first material layer and second material layer of described first opening etched portions thickness, the etch rate of described second material layer is greater than the etch rate of the first material layer.Because described mask layer only exposes part second material layer of the first material layer sidewall surfaces, part second material layer on the first material layer sidewall has only been etched in described technical solution of the present invention, the surface of the second material layer on described first material layer sidewall is not flushed, and the height of part second material layer covered by mask layer is greater than the height of the first material layer after etching.And then etching described mask layer, the width of the first opening is increased, forms the second opening, described second opening exposes the second material layer of remaining first material layer and described first material layer sidewall surfaces completely.Height due to part second material layer on the first material layer sidewall is greater than the height along the first material layer after the first opening etching, so in the process along the second opening etching, the thickness of the second material layer of etching is needed to be greater than the thickness of the first material layer of needs etching, described difference in thickness can make up etch rate difference, thus the sidewall of the groove formed finally can be made to flush, over etching can not be caused to the second material layer below the 3rd material layer, described 3rd material layer can be avoided to cave in or peeling phenomenon, thus improve the performance of the final MEMS oscillator formed.
Further, in technical scheme of the present invention, described mask the first opening layer by layer exposes the surface of part second material layer of the first material layer both sides, make follow-uply to etch described first material layer and the second material layer simultaneously, thus can avoid etching in the process of the first material layer separately, the material reaction gas of etching gas and the first material layer is known from experience form many carbon polymers and native oxide layer on the interface of the second material layer and the first material layer, affects the follow-up etching to the second material layer.
Accompanying drawing explanation
Fig. 1 to Fig. 3 is the structural representation of the forming process of the semiconductor structure of prior art of the present invention;
Fig. 4 to Figure 11 is the structural representation of the forming process of the semiconductor structure of embodiments of the invention.
Embodiment
As described in the background art, the semiconductor structure that prior art is formed easily caves in or the problem such as to peel off, the performance of the final MEMS oscillator formed of impact.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Please refer to Fig. 4, substrate 100 is provided, described substrate 100 is formed with the first material layer 201 of cover part substrate 100, be covered to small part substrate 100 surface and the first material layer 201 sidewall surfaces the second material layer 202, be positioned at described second material layer 202 surface and the 3rd material layer 203 flushed with the first material layer 201 surface.
The material of described substrate 100 comprises the semi-conducting materials such as silicon, germanium, SiGe, GaAs, can also be glass or plastic or other material.Described substrate 100 can be body material also can be that composite construction is as silicon-on-insulator.Those skilled in the art can select the type of described Semiconductor substrate 100 according to the semiconductor device that substrate 100 is formed, therefore the type of described Semiconductor substrate should not limit the scope of the invention.In the present embodiment, described substrate 100 is monocrystalline substrate, can be a part for wafer.The semiconductor device such as MOS transistor can also be formed with in described substrate 100.
The material of described first material layer 201 is different from the material of the second material layer 202, thus follow-up in the process etching described first material layer 201 and the second material layer 202, and described first material layer 201 and the second material layer 202 have different etch rates.In the present embodiment, the material of described first material layer 201 is SiGe, and the material of the second material layer is Ge.In other embodiments of the invention, described first material layer 201 and the second material layer 202 can also be other semi-conducting materials.
In the present embodiment, the material of described 3rd material layer 203 is identical with the material of the first material layer 201, is SiGe.In other embodiments of the invention, described 3rd material layer 203 also can be other semi-conducting materials different from the material of the second material layer 202.
In the present embodiment, the method that described substrate 100 is formed described first material layer 201, second material layer 202 and the 3rd material layer 203 comprises: adopt chemical vapor deposition method, after forming the first material on the substrate, described first material is graphically formed to the first material layer 201 of cover part substrate 100; Form the second material layer 202 successively on described substrate 100 surface and the first material layer 201 surface and cover the 3rd material layer 203 of described second material layer 202, and planarization is carried out to described 3rd material layer 203, second material layer 202, expose the surface of the first material layer 201, described 3rd material layer 203 is flushed with the surface of the first material layer 201.Described 3rd material layer 203 is for the formation of the cantilever design of MEMS oscillator.
Please refer to Fig. 5, form mask layer 300 at described first material layer 201, second material layer 202 and the 3rd material layer 203 surface.
The material of described mask layer 300 can be the mask materials such as silica, silicon nitride, silicon oxynitride or amorphous carbon.In the present embodiment, the material of described mask layer 300 is silica, and chemical vapor deposition method can be adopted to form described mask layer 300.The thickness of described mask layer 300 is
Please refer to Fig. 6, form the first graphical photoresist layer 401 on described mask layer 300 surface.
Adopt spin coating proceeding after described mask layer 300 surface forms photoresist layer, exposure imaging is carried out to described photoresist layer, forms the first graphical photoresist layer 401.
The figure of the described first graphical photoresist layer 401 exposes the mask layer 300 on part second material layer 202 surface of the first material layer 201 and described first material layer 201 sidewall surfaces.
Please refer to Fig. 7, with the described first graphical photoresist layer 401 for mask, etch described mask layer 300 (please refer to Fig. 6), form the mask layer 300a with the first opening 301, described first opening 301 exposes the part surface of the second material layer 202 of the first material layer 201 surface and covering the first material layer 201 sidewall.
Adopt dry etch process to etch described mask layer 300, in the present embodiment, the material of described mask layer 300 is silica, so can adopt CF
4, CHF
3, C
2f
6deng fluoro-gas as etching gas, described etching technics, using the first material layer 201 as etching stop layer, forms the mask layer 300a with the first opening 301.
The width of described first opening 301 is greater than the width of the first material layer 201, so the face width of the second material layer 202 that described first opening 301 exposes is 2/5 ~ 3/5 of total thickness of the second material layer 202 of the first material layer 201 sidewall surfaces.In the present embodiment, the gross thickness of the second material layer 202 of described first material layer 201 sidewall surfaces is
the face width of the second material layer 202 that described first opening 301 exposes can be
Described first opening 301 exposes the surface of part second material layer 202 of the first material layer 201 both sides, make follow-up in the process etching described first material layer 201 and the second material layer 202, only can etch part second material layer 202 of the first material layer 201 sidewall surfaces, and, etch described first material layer 201 and the second material layer 202 can be avoided etching in the process of the first material layer 201 separately simultaneously, the interface of the second material layer 202 and the first material layer 201 forms many carbon polymers and native oxide layer, affect the follow-up etching to the second material layer 202.
Please refer to Fig. 8, remove the described first graphical photoresist layer 401 (please refer to Fig. 7), form second graphical photoresist layer 402 on described mask layer 300a surface, described second graphical photoresist layer 402 exposes the part mask layer 300a on the second material layer 202 surface on the first material layer 201 and described first material layer 201 sidewall.
In the present embodiment, cineration technics is adopted to remove the described first graphical photoresist layer 401.In other embodiments of the invention, wet etching can also be adopted to remove the described first graphical photoresist layer 401.
After removing the described first graphical photoresist layer 401, adopt spin coating proceeding, photoresist layer is formed at described mask layer 300a and the first material layer 201, second material layer 202 surface, then exposure imaging is carried out to described photoresist layer, form second graphical photoresist layer 402, described second graphical photoresist layer 402 exposes the part mask layer 300a of the first opening 301 and described first opening 301 both sides.Described second graphical mask layer 402 defines position and the size of follow-up the second opening formed in mask layer 300a.
In the present embodiment, before described first material layer 201 of etching and the second material layer 202, form described second graphical photoresist layer 402, described second graphical photoresist layer 402 can protect the material layer in other regions on described substrate 100 surface.
In other embodiments of the present invention, also after the first material layer 201 of subsequent etching segment thickness and the second material layer 202, then second graphical photoresist layer 402 can be formed on described mask layer 300a surface.
Please refer to Fig. 9, along the first material layer 201 (please refer to Fig. 8) and second material layer 202 (please refer to Fig. 8) of described first opening 301 etched portions thickness, the etch rate of described second material layer 202 is greater than the etch rate of the first material layer 201, makes the surface of the first material layer 201a after etching higher than the surface of part second material layer 202 on described first material layer 201a sidewall.
Dry etch process can be adopted to etch described first material layer 201 and the second material layer 202.In the present embodiment, described dry etch process adopts HBr and Cl
2mist as etching gas, O
2as buffer gas, wherein the flow of HBr is 135sccm ~ 165sccm, Cl
2flow be 100sccm ~ 140sccm, O
2flow be 5sccm ~ 15sccm, pressure is 5mTorr ~ 15mTorr, and power is 450W ~ 550W, and temperature is 50 DEG C ~ 80 DEG C, and bias voltage is 225V ~ 250V.Described etching technics has lower etch rate for mask layer 300a; thus larger damage can not be caused to the pattern of described 300a in etching process; described mask layer 300a can play enough protective effects to part second material layer 202 of below, makes described anisotropic etch process only can etch described first material layer 201 and is positioned at part second material layer 202 on described first material layer 201 surface.
In above-mentioned etching technics, the etch rate ratio of described second material layer 202 and the first material layer 201 is 1.5 ~ 1.8, after first material layer 201 and the second material layer 202 of the first opening 301 etched portions thickness, the thickness of the first material layer 201a after etching is 1/2 ~ 7/10 of the first material layer 201 thickness before etching, and the thickness of part second material layer 202 after etching is 3/10 ~ 1/2 of the second material layer 202 thickness before etching.The thickness of part first material layer 201 that etching is removed can adjust according to the etch rate difference of described first material layer 201 and the second material layer 202.
Compared with prior art, embodiments of the invention have only etched part second material layer 202 on the first material layer 201 sidewall, the surface of the second material layer 202 on described first material layer 201 sidewall is not flushed, and the height of part second material layer 202 contacted with the first material layer 201a is lower than by the height of the second material layer 202 of mask layer 300a cover part.
Please refer to Figure 10, with described second graphical photoresist layer 402 for mask, etch described first opening 301 (please refer to Fig. 9) both sides not by mask layer 300a that second graphical photoresist layer 402 covers, form the second opening 302, described second opening 302 exposes the second material layer 202 of the first material layer 201a and the first material layer 201a sidewall surfaces completely.
The etching technics identical with forming the first opening 301 can being adopted to etch described mask layer 300a, forming described second opening 302, with CF
4, CHF
3, C
2f
6deng fluoro-gas as etching gas.The sidewall of described second opening 302 flushes with the sidewall of the 3rd material layer 203, thus expose the second material layer 202 of the first material layer 201a and the first material layer 201a sidewall surfaces completely, be convenient to follow-up the second material layer 202 removed completely on described first material layer 201a and both sides sidewall thereof.
Please refer to Figure 11, remaining first material layer 201a (please refer to Figure 10) and the second material layer 202 to substrate 100 surface is etched along described second opening 302, form groove 210, the 3rd material layer 203 of described groove 210 both sides and the sidewall of the second material layer 202 flush.
Adopt dry etch process, etch the first material layer 201a and the second material layer 202 to substrate 100 surface along described second opening 302.Described dry etch process HBr and Cl
2mist as etching gas, O
2as buffer gas, wherein the flow of HBr is 135sccm ~ 165sccm, Cl
2flow be 100sccm ~ 140sccm, O
2flow be 5sccm ~ 15sccm, pressure is 5mTorr ~ 15mTorr, and power is 450W ~ 550W, and temperature is 50 DEG C ~ 80 DEG C, and bias voltage is 225V ~ 250V.
Although in etching process, the etch rate of the second material layer 202 is greater than the etch rate of the first material layer 201a, but the height due to part second material layer 202 on described first material layer 201a sidewall is greater than the height of the first material layer 201a, so need the thickness of the second material layer 202 of etching to be greater than the thickness of the first material layer 201a of needs etching, described difference in thickness can make up etch rate difference, thus the sidewall of the groove 210 formed finally can be made to flush.Compared with prior art, damage can not be caused to the second material layer 202 below the 3rd material layer 203, thus avoid described 3rd material layer 203 to occur collapsing or spallation problems.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (16)
1. a formation method for semiconductor structure, is characterized in that, comprising:
Substrate is provided, the 3rd material layer described substrate being formed with the first material layer of cover part substrate, being covered to the second material layer of small part substrate surface and the first material layer sidewall surfaces, being positioned at described second material surface, the surface of described 3rd material layer flushes with the first material surface;
Form the mask layer with the first opening in described first material layer, the second material layer and the 3rd material surface, described first opening exposes the part surface of the second material layer of the first material surface and covering the first material layer sidewall;
Along the first material layer and second material layer of described first opening etched portions thickness, the etch rate of described second material layer is greater than the etch rate of the first material layer;
Etch described mask layer, the width of the first opening is increased, forms the second opening, described second opening exposes the second material layer of remaining first material layer and described first material layer sidewall surfaces completely;
Along described second opening etching remaining first material layer and the second material layer to substrate surface, formed groove, the 3rd material layer of described groove both sides and the sidewall of the second material layer flush.
2. the formation method of semiconductor structure according to claim 1, is characterized in that, the face width of the second material layer that described first opening exposes is 2/5 ~ 3/5 of the gross thickness of the second material layer of the first material layer sidewall surfaces.
3. the formation method of semiconductor structure according to claim 2, is characterized in that, the face width of the second material layer that described first opening exposes is
4. the formation method of semiconductor structure according to claim 1, it is characterized in that, after first material layer and the second material layer of the first opening etched portions thickness, the thickness of the first material layer after etching is 1/2 ~ 7/10 of the first layer thickness before etching.
5. the formation method of semiconductor structure according to claim 4, it is characterized in that, after first material layer and the second material layer of the first opening etched portions thickness, the thickness of part second material layer after etching is 3/10 ~ 1/2 of the second layer thickness before etching.
6. the formation method of semiconductor structure according to claim 1, is characterized in that, the material of described first material layer is different from the material of the second material layer.
7. the formation method of semiconductor structure according to claim 6, is characterized in that, the material of described first material layer is SiGe, and the material of the second material layer is Ge.
8. the formation method of semiconductor structure according to claim 1, is characterized in that, adopts dry etch process described first material layer of etching and the second material layer.
9. the formation method of semiconductor structure according to claim 8, is characterized in that, described dry etch process adopts HBr and Cl
2mist as etching gas, O
2as buffer gas, wherein the flow of HBr is 135sccm ~ 165sccm, Cl
2flow be 100sccm ~ 140sccm, O
2flow be 5sccm ~ 15sccm, pressure is 5mTorr ~ 15mTorr, and power is 450W ~ 550W, and temperature is 50 DEG C ~ 80 DEG C, and bias voltage is 225V ~ 250V.
10. the formation method of semiconductor structure according to claim 1, is characterized in that, the material of described mask layer is silica, silicon nitride, silicon oxynitride or amorphous carbon.
The formation method of 11. semiconductor structures according to claim 1, is characterized in that, the method forming described mask layer comprises: form mask layer in described first material layer, the second material layer and the 3rd material surface; The first graphical photoresist layer is formed on described mask layer surface; With the described first graphical photoresist layer for mask, etch described mask layer, form the mask layer with the first opening; Remove the described first graphical photoresist layer.
The formation method of 12. semiconductor structures according to claim 1, it is characterized in that, the method forming described second opening comprises: form second graphical photoresist layer on described mask layer surface, described second graphical photoresist layer exposes the part mask layer of the second material surface on the first material layer and described first material layer sidewall; With described second graphical photoresist layer for mask, etch described mask layer, form the second opening.
The formation method of 13. semiconductor structures according to claim 12, is characterized in that, before first material layer and the second material layer of the first opening etched portions thickness, forms second graphical photoresist layer on described mask layer surface.
The formation method of 14. semiconductor structures according to claim 12, is characterized in that, after first material layer and the second material layer of the first opening etched portions thickness, forms second graphical photoresist layer on described mask layer surface.
The formation method of 15. semiconductor structures according to claim 1, is characterized in that, the material of described 3rd material layer is identical with the material of the first material layer.
The formation method of 16. semiconductor structures according to claim 15, is characterized in that, the material of described 3rd material layer is SiGe.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030003759A1 (en) * | 2001-06-27 | 2003-01-02 | Infineon Technologies North America Corp | Etch selectivity inversion for etching along crystallographic directions in silicon |
| CN102543698A (en) * | 2010-12-22 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of metal gate electrode |
| CN102956536A (en) * | 2011-08-24 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for quasi SOI (silicon on insulator) structure |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030003759A1 (en) * | 2001-06-27 | 2003-01-02 | Infineon Technologies North America Corp | Etch selectivity inversion for etching along crystallographic directions in silicon |
| CN102543698A (en) * | 2010-12-22 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of metal gate electrode |
| CN102956536A (en) * | 2011-08-24 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for quasi SOI (silicon on insulator) structure |
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