CN105447217B - Four based on FPGA select the process mapping method of a selector - Google Patents
Four based on FPGA select the process mapping method of a selector Download PDFInfo
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- CN105447217B CN105447217B CN201410513650.6A CN201410513650A CN105447217B CN 105447217 B CN105447217 B CN 105447217B CN 201410513650 A CN201410513650 A CN 201410513650A CN 105447217 B CN105447217 B CN 105447217B
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Abstract
The present invention relates to the process mapping methods that a kind of four based on FPGA select a selector, select a selector for realizing one four in LP；LP includes two LUT4, LUT4C and two register；The described method includes: the input terminal in first LUT4 is respectively connected to the first input signal, the second input signal, the first input signal or the second input signal are exported by the output end that the first gating signal gates first LUT4；And it is respectively connected to third input signal, the 4th input signal in the input terminal of second LUT4, third input signal or the 4th input signal are exported by the output end that the first gating signal gates second LUT4；The output end of two LUT4 is separately connected two input terminals of an alternative selector in LP；The first input signal or the second input signal, or gating output third input signal or the 4th input signal are exported to gate alternative selector according to the second gating signal.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to four based on FPGA select a selector Technology Mapping side
Method.
Background technique
Field programmable gate array (Field-Programmable Gate Array, FPGA) is a kind of with abundant hard
The logical device of part resource, powerful parallel processing capability and flexible reconfigurable ability.These features make FPGA at data
Many fields such as reason, communication, network have obtained more and more extensive uses.
In the application design of FPGA, multiple selector (MUX) is a kind of general-purpose device being widely used.Traditional
In process mapping method, select the logical mappings schematic diagram of a selector can be as based on four inputs look-up table (LUT4) are realized four
Shown in Fig. 1.First LUT4 gates input signal i2 and i3 by gating signal S0, or is gated and exported by S1
S0, and the output signal after gating is connected to the input all the way of second LUT4；Other three input terminals of second LUT4
Also input signal i0 and i1 gates the i2 or i3 of output of the output from first LUT4 by gating signal S1, or when the
When one LUT4 gating output S0, output i0 or i1 is gated by S0, realizes that four select one output with this.
In the framework of CME FPGA, include inside fpga chip multiple logic units (Logic Element, LE), often
A LE includes multiple logic areas (Logic Parcel, LP), includes two LUT4,1 LUT4C in each LP (with carry chain
) and two registers LUT4.It, can be such as Fig. 2 institute using the logical mappings figure of above-mentioned process mapping method based on CME-HR3 framework
Show.Because the output signal of first LUT4 requires connect to the input of second LUT4, in CME framework, the output of LUT4
The input terminal of LUT4C is connected to after winding structure, therefore four select a selector to need to occupy a LUT4 above in Fig. 2
It is realized with LUT4C.LUT4C is the LUT4 of carry chain, may be used as adder, therefore when LUT4C resource anxiety, can be generated
Competition.And the output of LUT4 is the input terminal that LUT4C is just connected to after winding structure, also results in multiple selector
Delay than directly use LP interconnector it is long.
Summary of the invention
The work of a selector is selected the purpose of the present invention is in view of the drawbacks of the prior art, providing a kind of four based on FPGA
Skill mapping method effectively prevents the occupancy to LUT4C resource in the case where resource consumption is constant, while also effective drop
Low logic time delay, realizes the optimization to chip efficiency.
The embodiment of the invention provides the process mapping method that a kind of four based on FPGA select a selector, the technique is reflected
Shooting method is used to select one selector in the logic area LP realization one four of FPGA, includes that two four inputs are looked into the LP
Look for table LUT4, a four input look-up table LUT4C and two registers with carry chain；The process mapping method includes:
It is respectively connected to the first input signal, the second input signal and the first gating signal in the input terminal of first LUT4,
The first input signal or the second input letter are exported by the output end that first gating signal gates first LUT4
Number；And
Third input signal, the 4th input signal and the first gating letter are respectively connected in the input terminal of second LUT4
Number, third input signal or the 4th input are exported by the output end that first gating signal gates second LUT4
Signal；
Wherein, the output end of first LUT4 connects the first input of an alternative selector in the LP
End, the output end of second LUT4 connect the second input terminal of the alternative selector；
The alternative selector exports the first input of the first input end input according to the second gating signal gating
Perhaps the second input signal or gating export the third input signal or the 4th input that second input terminal inputs to signal
Signal.
Preferably, the process mapping method further include:
It will believe in the input terminal of first LUT4 except the first input signal of access, the second input signal and first gate
Number three input terminals except another input terminal it is hanging.
Preferably, the process mapping method includes:
It will believe in the input terminal of second LUT4 except access third input signal, the 4th input signal and first gate
Number three input terminals except another input terminal it is hanging.
Preferably, the FPGA is specially CME-HR3FPGA device.
Four based on FPGA provided in an embodiment of the present invention select the process mapping method of a selector, based on CME-HR3's
LP structure realizes two alternative selectors using two LUT4 in LP respectively, the output end of the two LUT4 is recycled to connect
LP in the same MUX, the output signal of two LUT4 is gated, four is achieved in and the logic of a selector is selected to reflect
It penetrates.In the case where resource consumption is constant, the occupancy to LUT4C resource is effectively prevented, while also effectively reducing logic
Time delay realizes the optimization to chip efficiency.
Detailed description of the invention
The logical mappings schematic diagram that Fig. 1 selects a selector for the prior art provides four；
Fig. 2 is the logical mappings figure that four based on CME-HR3FPGA device that the prior art provides select a selector；
Fig. 3 is the provided in an embodiment of the present invention four logical mappings schematic diagrames for selecting a selector；
Fig. 4 is the logical mappings figure that four based on CME-HR3FPGA device provided in an embodiment of the present invention select a selector.
Specific embodiment
Below by drawings and examples, technical scheme of the present invention will be described in further detail.
Method in the following embodiments of the present invention is realized based on CME-HR3FPGA device, to better understand this hair
The technical solution that bright embodiment provides, is first briefly described the logical construction of CME-HR3FPGA device.
In the framework of CME-HR3FPGA, include inside fpga chip multiple logic units (LogicElement, LE),
Each LE includes multiple logic areas (Logic Parcel, LP), includes two four input look-up table LUT4,1 in each LP
LUT4C (LUT4 with carry chain) and two registers.
Fig. 3 is the provided in an embodiment of the present invention four logical mappings schematic diagrames for selecting a selector；Fig. 4 is provides based on Fig. 3
Logical mappings, four realized in CME-HR3FPGA device select the logical mappings figure of a selector.
Process mapping method of the present invention is described in further detail below with reference to Fig. 3, Fig. 4.
As shown in figure 3, provided in an embodiment of the present invention four select the logic of a selector realizes it is by three alternative MUX
Built-up.
Wherein, the input terminal of first MUX accesses the first input signal I0 and the second input signal I1, passes through gating signal
S0 selection output, the input terminal of second MUX access third input signal I2 and the 4th input signal I3, pass through gating signal S0
Selection output.The output end of above-mentioned two MUX is coupled with the input terminal of third MUX, selects to export by gating signal S1,
Four logics for selecting a selector are realized with this.
In process mapping method provided in this embodiment, it is based on CME-HR3FPGA framework, two MUX of prime can be with
It is respectively mapped to realize in the LUT4 of a LP, specific as follows:
The first input signal I0, the second input signal I1 and the first gating letter are respectively connected in the input terminal of first LUT4
Number S0 exports the first input signal I0 or the by the output end that the first gating signal S0 gates first LUT4
Two input signal I1；
Also, access the first input signal I0, the second input signal I1 and first will be removed in the input terminal of first LUT4
Another input terminal except three input terminals of gating signal S0 is hanging.
Third input signal I2, the 4th input signal I3 and first choosing are respectively connected in the input terminal of second LUT4
Messenger S0, by the first gating signal S0 gate second LUT4 output end export third input signal I2 or
The 4th input signal I3 of person；
Also, access third input signal I2, the 4th input signal I3 and first will be removed in the input terminal of second LUT4
Another input terminal except three input terminals of gating signal S0 is hanging.
Wherein, the first input end of the output end connection alternative selector MUXF5 of first LUT4, second LUT4's
Output end connects the second input terminal of alternative selector MUXF5；
Alternative selector MUXF5 gates the first input for exporting the input of its first input end according to the second gating signal S1
Perhaps the second input signal I1 or gating export the third input signal I2 or the 4th that its second input terminal inputs to signal I0
Input signal I3.
As a result, by two LUT4 and alternative MUX, four logic functions for selecting a selector are realized.
Specific implementation of the above-mentioned Technology Mapping in LP is as shown in Figure 4.Above-mentioned first LUT4 is the LUT4 4_1 in LP,
Above-mentioned second LUT4 is the LUT4 0 in LP.Their output is by being connected to an alternative MUX shown in thick line in figure.
Because after logical mappings, logical resource usage amount that the dosage of LUT as needs to pay close attention to.Accordingly, with respect to existing
Have in technology occupy LUT4 and LUT4C for, present invention process mapping method be occupy two LUT4, i.e., with it is existing
Logical resource usage amount in technology is identical.But avoid may be used as the resource occupation of the LUT4C of adder, so as to avoid
The competition that may be generated when LUT4C resource anxiety.Again because LUT4 4_1 and LUT4 0 is to the line between alternative MUX
The line that 2 modules are connected directly on LP internal hardware, referred to as cascade cable release, compared to the prior art LUT4 need by around
Output is connected to for the input of LUT4C by cable architecture, can be effectively reduced logic time delay, to realize the excellent of chip efficiency
Change.
It should be noted that, although specific embodiments of the present invention be realized based on CME-HR3FPGA device, but
Be, it will be apparent to those skilled in the art that provided by the present invention four select a selector process mapping method can it is same or
Person's slightly change application is in the FPGA device of other frameworks.
Professional should further appreciate that, described in conjunction with the examples disclosed in the embodiments of the present disclosure
Unit and algorithm steps, can be realized with electronic hardware, computer software, or a combination of the two, hard in order to clearly demonstrate
The interchangeability of part and software generally describes each exemplary composition and step according to function in the above description.
These functions are implemented in hardware or software actually, the specific application and design constraint depending on technical solution.
Professional technician can use different methods to achieve the described function each specific application, but this realization
It should not be considered as beyond the scope of the present invention.
The step of method described in conjunction with the examples disclosed in this document or algorithm, can be executed with hardware, processor
The combination of software module or the two is implemented.Software module can be placed in random access memory (RAM), memory, read-only memory
(ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field
In any other form of storage medium well known to interior.
Above-described specific embodiment has carried out further the purpose of the present invention, technical scheme and beneficial effects
It is described in detail, it should be understood that being not intended to limit the present invention the foregoing is merely a specific embodiment of the invention
Protection scope, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (4)
1. the process mapping method that a kind of four based on FPGA select a selector, which is characterized in that the process mapping method is used
One selector is selected in the logic area LP realization one four in FPGA, includes two four input look-up tables in the LP
LUT4, a four input look-up table LUT4C and two registers with carry chain；The process mapping method includes:
It is respectively connected to the first input signal, the second input signal and the first gating signal in the input terminal of first LUT4, is passed through
The output end that first gating signal gates first LUT4 exports the first input signal or the second input signal；And
And
It is respectively connected to third input signal, the 4th input signal and first gating signal in the input terminal of second LUT4,
Third input signal or the 4th input letter are exported by the output end that first gating signal gates second LUT4
Number；
Wherein, the output end of first LUT4 connects the first input end of an alternative selector in the LP, institute
The output end for stating second LUT4 connects the second input terminal of the alternative selector；
The alternative selector exports the first input signal of the first input end input according to the second gating signal gating
Perhaps the second input signal or gating export the third input signal or the 4th input letter of the second input terminal input
Number.
2. process mapping method according to claim 1, which is characterized in that the process mapping method further include:
The first input signal of access, the second input signal and the first gating signal will be removed in the input terminal of first LUT4
Another input terminal except three input terminals is hanging.
3. process mapping method according to claim 1, which is characterized in that the process mapping method includes:
Access third input signal, the 4th input signal and the first gating signal will be removed in the input terminal of second LUT4
Another input terminal except three input terminals is hanging.
4. the method according to claim 1, wherein the FPGA is specially CME-HR3 FPGA device.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101446996A (en) * | 2008-12-17 | 2009-06-03 | 复旦大学 | Virtual FPGA structural modeling and mapping method thereof |
| CN101969306A (en) * | 2010-09-07 | 2011-02-09 | 复旦大学 | FPGA (Field Programmable Gate Array) configurable five-input lookup table structure |
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| US6864714B2 (en) * | 2002-06-10 | 2005-03-08 | Stmicroelectronics Pvt. Ltd. | PLDs providing reduced delays in cascade chain circuits |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101446996A (en) * | 2008-12-17 | 2009-06-03 | 复旦大学 | Virtual FPGA structural modeling and mapping method thereof |
| CN101969306A (en) * | 2010-09-07 | 2011-02-09 | 复旦大学 | FPGA (Field Programmable Gate Array) configurable five-input lookup table structure |
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