CN105446935B - It is shared to store concurrent access processing method and device - Google Patents
It is shared to store concurrent access processing method and device Download PDFInfo
- Publication number
- CN105446935B CN105446935B CN201410526653.3A CN201410526653A CN105446935B CN 105446935 B CN105446935 B CN 105446935B CN 201410526653 A CN201410526653 A CN 201410526653A CN 105446935 B CN105446935 B CN 105446935B
- Authority
- CN
- China
- Prior art keywords
- access
- interface
- storage
- shared
- feedback data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Multi Processors (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Abstract
The invention discloses the shared concurrent access processing methods of storage of one kind, the described method includes: for the access queue on each access interface, unfinished storage is arbitrarily selected to access from any one or more access queues, there is no Bank to conflict between selected storage access；Parallel decoding is accessed to selected storage, and is transferred to corresponding Bank.Correspondingly, significantly more efficient can evade access conflict the invention also discloses the shared concurrent access process device of storage of one kind and make full use of interface bandwidth, and not influenced substantially by access mode.
Description
Technical field
The present invention relates to digit chip fields, more particularly to a kind of concurrent access processing method of shared storage and device.
Background technique
At present all there is more than one processor and coprocessor in majority system on chip (SOC, System on Chip), and
And the key data interaction between these processors is realized by shared storage.It is shared to deposit with the extensive use of multicore SOC
The access conflict of storage and bandwidth deficiency increasingly become the bottleneck of system for restricting performance.
The method that existing shared memory interface improves mainly solves reduction access delay, optimizes cross-border access, disappears
Except non-alignment access expense, simple access conflict are evaded, optimizes bandwidth and delay that continuation address accesses etc., it is substantially pair
The optimization of special scenes.
As shown in Figure 1, for a kind of common concurrent access mode of shared storage.Wherein, only one is logically independent
Memory, when 4 interfaces have storage access to occur, only one accesses available response (as shown by the solid line in the drawings).
Even if in this way, having 4 stand-alone interfaces, the but effective bandwidth of only one interface.
As shown in Fig. 2, be a kind of concurrent access mode of shared storage with common conflict evading, have 4 in logic solely
Vertical logical block (Block), but the access of queue heads can only be taken on interface, when 4 interfaces have storage access to occur, only
There is no the access of Block conflict can be responded (as shown by the solid line in the drawings).Even if in this way, have 4 stand-alone interfaces, but
Since the probability of Block conflict is very big, actually active bandwidth only has 2.7 times of individual interface.
As shown in figure 3, access is then counted from which interface for common shared storage concurrent access interface echo plex mode
Which returned according to from interface.Obviously when there is multiple access to enter from the same interface, although these access all will be by interface institute
Receive, but synchronization, because each interface can only return to a data, only those do not have the access of interface conflict
Real response is obtained.As shown in figure 3, access0 and access1 from interface 0 (Interface0) enter, access2 and
Access3 enters from interface 1 (Interface1), although these access will all be received by the corresponding interface, synchronization
Because each interface can only return to a data, only access0 and access2 have obtained real response (solid line expression
Received by interface and obtained real response), access1 and access3 do not obtain real response (dotted line are indicated by interface
Receive without but obtain real response).Even if in this way, have 4 stand-alone interfaces, but because interface conflict probability very
Greatly, actually active bandwidth only has 2.7 times of individual interface.
It is, therefore, desirable to provide a kind of new scheme, evades access conflict with significantly more efficient and makes full use of interface bandwidth,
It solves the problems, such as that access conflict and the bandwidth of shared storage are insufficient, and guarantees not influenced by access mode substantially.
Summary of the invention
In view of this, the main purpose of the present invention is to provide the concurrent access processing method of the shared storage of one kind and device,
It significantly more efficient can evade access conflict and using interface bandwidth, solve the problems, such as the access conflict and bandwidth deficiency of shared storage.
In order to achieve the above objectives, the technical scheme of the present invention is realized as follows:
A kind of shared concurrent access processing method of storage is provided in the embodiment of the present invention, comprising:
For the access queue on each access interface, arbitrarily selected from any one or more access queues not complete
At storage access, there is no heap Bank conflicts between selected storage access；
Parallel decoding is accessed to selected storage, and is transferred to corresponding Bank.
In above scheme, the method also includes:
According to the ID of selected storage access, its transmission state is updated at any time；
By it is processed at the ID of storage access inform corresponding access interface so that access interface will store accordingly
Access is removed from access queue.
In above scheme, each corresponding access queue containing multiple unfinished transmission of the access interface is selected
Storage access no more than access interface sum.
A kind of shared concurrent access process device of storage is additionally provided in the embodiment of the present invention, comprising: shared bus, multiple
Access interface, shared storage access exchange administrative unit and shared memory, wherein
Shared bus is supported not completing transmission, be supported disorderly for providing read/write channel for the storage access from access originator
Sequence transmission；
Access interface, the storage access for receiving to send by the shared bus, and the storage of receiving access is put
Enter access queue；
Shared storage access exchange administrative unit includes: access selecting module and parallel decoding module, wherein
Selecting module is accessed, the access queue for being directed on each access interface, from any one or more institutes
Stating access queue arbitrarily selects unfinished storage to access, and there is no Bank to conflict between selected storage access；
Parallel decoding module for accessing parallel decoding to the storage of the access selecting module selection, and is transferred to each
Self-corresponding heap Bank；
Shared memory, including multiple logical blocks, the logical block and access interface do not have apparent corresponding relationship, each
Logical block includes multiple Bank, and the logical block, which refers to, provides the logic storage unit of continuation address, and Bank is for carrying out ground
The smaller physical memory cell that location ranks interweave.
In above scheme, the shared storage access exchange administrative unit further includes transmission state update module；
The access selecting module is also used to after selection storage access, and the ID of selected storage access is sent to
The transmission state update module；
The transmission state update module updates its transmission state for the ID according to the storage access at any time；And
By it is processed at the ID of storage access inform corresponding access interface；
The access interface, be also used to according to it is processed at storage access ID, access will be stored accordingly from visit
It asks in queue and removes.
In above scheme, each corresponding access queue containing multiple unfinished transmission of the access interface is selected
Storage access no more than access interface sum.
A kind of shared concurrent access processing method of storage is additionally provided in the embodiment of the present invention, comprising:
For each feedback data for needing to return, any one access interface is selected as it and passes through interface；
Access interface is given by feedback data and its with information, and adjoint the information includes to access ID and described by connecing
The mark of mouth.
In above scheme, any one access interface is selected as it and passes through interface, comprising:
The corresponding access interface of the feedback data is preferentially selected as it and passes through interface；
If the corresponding access interface of the feedback data selects any one not need currently to return there are access conflict
The access interface for returning data passes through interface as it.
In above scheme, the method also includes:
Access interface receives the feedback data and its with information, and according to the adjoint information by the feedback data
Access originator is returned to by shared bus.
A kind of shared concurrent access process device of storage is additionally provided in the embodiment of the present invention, comprising: shared bus, multiple
Access interface, shared storage access exchange administrative unit and shared memory, wherein
Shared bus is supported not completing transmission, be supported disorderly for providing read/write channel for the storage access from access originator
Sequence transmission；
Access interface, the storage access for receiving to send by the shared bus, and the storage of receiving access is put
Enter access queue；And for the adjoint information according to feedback data, the feedback data for needing to return is passed through described shared total
Line returns to access originator；
Shared storage access exchange administrative unit includes: interface selecting module, for being directed to the feedback data of storage access,
It selects any one of access interface as it by interface, and the feedback data and its adjoint information is given access and connect
Mouthful, the adjoint information includes the ID and the mark by interface that the corresponding storage of the feedback data accesses；
Shared memory, including multiple logical blocks, each logical block include multiple Bank, and the logical block, which refers to, provides company
The logic storage unit of continuous address, Bank is the smaller physical memory cell for carrying out address file intertexture.
In above scheme, the interface selecting module is used to select any one for each feedback data for needing to return
A access interface passes through interface as it, comprising:
For each feedback data for needing to return, preferentially select the corresponding access interface of feedback data as it by connecing
Mouthful；If the corresponding access interface of the feedback data there are access conflict, selects any one not need currently to return to number
According to access interface pass through interface as it.
In the present invention, the receiving storage access and selection storage access, when returned data for ignoring sequence select any one
Interface is used as through interface, in this way, multiple interfaces share the memory in the same chip, improves storage access bandwidth, can
It is significantly more efficient to evade access conflict and make full use of interface bandwidth, and do not influenced substantially by access mode.
Detailed description of the invention
Fig. 1 is a kind of common concurrent access mode schematic diagram of shared storage；
Fig. 2 is a kind of concurrent access mode schematic diagram of shared storage with common conflict evading；
Fig. 3 is a kind of common concurrent access interface echo plex mode schematic diagram of shared storage；
Fig. 4 is the concurrent access mode schematic diagram of shared storage according to the embodiment of the present invention；
Fig. 5 is the concurrent access interface echo plex mode schematic diagram of shared storage according to the embodiment of the present invention；
Fig. 6 is the composed structure schematic diagram according to the concurrent access process device of shared storage of the embodiment of the present invention；
Fig. 7 a-7b is the concurrent access process device shared memory address code of shared storage according to the embodiment of the present invention
Schematic diagram；
Fig. 8 is the concurrent access processing method flow chart of shared storage according to the embodiment of the present invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, by the following examples and referring to attached drawing, right
The present invention is further described.
The concurrent access processing method of shared storage provided in an embodiment of the present invention and device, are shared same by multiple interfaces
Memory in a chip significantly more efficient can evade access conflict and make full use of interface to improve storage access bandwidth
Bandwidth, and do not influenced substantially by access mode.
Come so that 4 access interfaces, memory include 4 logical blocks (block), 16 independent heaps (Bank) as an example below
Illustrate the specific implementation process of the embodiment of the present invention.It should be noted that the embodiment of the present invention is equally applicable and is not limited to 8 and connects
The similar structures of mouth, 8 Block, 32 Bank etc., this similar structures are mainly characterized by having multiple access interfaces, Block
With the shared storage of Bank two-stage tissue.
As shown in figure 4, having 4 block and 16 independent Bank being logically independent in memory, when 4 interfaces
When having storage access to occur, the corresponding access queue containing multiple unfinished transmission of each access interface, the present invention is implemented
Example using out-of-order function can from 4 from four access queue access01~access04, access11 of equipment~
In access14, access21~access24, access31~access34, storage is arbitrarily taken to visit from random access queue
It asks, selected storage access stores selected access and carry out parallel processing, as long as not depositing no more than access interface sum
It will all be responded in the access of Bank conflict, and not need to take a visit according to the order or each access queue of access queue
The rule asked accesses to handle storage, and in this case, close to 0, actually active bandwidth about has single the probability of Bank conflict
4 times of interface.For example, as shown in figure 4, access01, access03, access21, access34 can be taken to carry out simultaneously simultaneously
Row processing.
The interface concurrently accessed is returned, feedback data can pass through any one access interface in the embodiment of the present invention
It returns, does not need according to " from where coming just from the rule where returned " returned data, as long as not needing to return on current interface
Data, so that it may with this interface return feedback data.There is no data that the interface returned is needed to solve interface using those
On access conflict, all access of any moment can obtain real response, and in this case, actually active bandwidth is individually to connect
4 times of mouth.As shown in figure 5, access0 and access1 is there are access conflict, when returned data, for the feedback coefficient of access1
According to not having to original interface Interface0, and the interface Interface1 returned is needed to return to its feedback with without data
Data.In access2 and access3 there are when access conflict, access2 and access3 have data to need to return, for
The feedback data of access1 is returned with interface Interface2, and the feedback data of access3 is returned with interface Interface3
It returns.
As shown in fig. 6, the concurrent access process apparatus structure of the shared storage of 4 interfaces, specifically includes that shared bus, 4
Access interface Slave0~Slave3, shared storage access exchange management (Shared memory access switch) unit,
Shared memory.
Shared bus provides read/write channel for the storage access from access originator, can be arbitrary topology but meet with
Under several main features (such as Fig. 6 is the signal of read/write channel separation, the same bus for supporting read/write channel unification):
Master is routed to from equipment (Slave) according to address；Slave to Master is routed according to ID；It supports not completing transmission
(outstanding)；It supports out-of-order transfer (out of order).
Four access interface Slave0~Slave3 are managed collectively, the access of each access interface in Slave0~Slave3
Queue has 4 positions (WID0&RID0~WID3&RID3), the storage access for receiving to send by the shared bus,
And the storage of receiving access is put into access queue；In addition, access interface can be also used for according to it is processed at storage visit
The ID asked will store access accordingly and remove from access queue.In addition to this it is possible to for according to the adjoint of feedback data
Information will need the feedback data returned to return to access originator by the shared bus.
Shared storage access exchange administrative unit includes access selection (access select) module, parallel decoding
(parallel decoding) module, transmission state update (transaction state update) module, access selection mould
Block, for arbitrarily being selected from any one or more access queues not complete for the access queue on each access interface
At storage access, there is no Bank conflicts between selected storage access；Parallel decoding module, for the visit
It asks the storage access parallel decoding of selecting module selection, and is transferred to corresponding Bank；The access selecting module, is also used
In after selection storage access, the ID of selected storage access is sent to the transmission state update module；The transmission
State update module updates its transmission state for the ID according to the storage access at any time；And by it is processed at deposit
The ID of storage access informs corresponding access interface.In addition to this it is possible to select (date feedback& comprising interface
Interface select) module, for selecting any one of access interface to pass through as it for each feedback data
Interface, and access interface is given by the feedback data and its with information, the adjoint information includes the feedback data institute
The ID of corresponding storage access and the mark by interface.
As shown in fig. 6, shared memory includes 4 logical block Block0~Block3, each logical block includes four
Bank (Bank0~Bank3), the logical block, which refers to, provides the logic storage unit of continuation address, and Bank is for carrying out ground
The smaller physical memory cell that location ranks interweave.Each Bank is responsible for multiple addresses, that is to say, that the address bit of multiple access
In the same Bank, when being accessed next, access is put by corresponding Bank according to the address of access.It is shared to deposit in practical application
Reservoir comprising four logical blocks (Block) encoded according to continuation address, can be convenient for as shown in Figure 7a using two-stage tissue
The conflict between concurrently accessing is avoided according to function storing data；As shown in Figure 7b, each Block includes according to lateral address
Four Bank of coding, convenient for avoiding the conflict between concurrently accessing according to statistical property storing data.In above-mentioned apparatus, word
A length of 128bit；First character in Bank0, second word in Bank1, third word in Bank2, the 4th word in Bank3, with
This analogizes.Sequential addressing in namely Block laterally addresses between Bank, discontinuous (the equal differences of tolerance 4 in address in Bank
Column), ranks intertexture is done in address between Bank.
Wherein, the interface selecting module is used to select any one access for each feedback data for needing to return
Interface passes through interface as it, comprising: preferential to select the corresponding access of feedback data for each feedback data for needing to return
Interface passes through interface as it；If there are access conflicts for the corresponding access interface of the feedback data, any one is selected
The access interface for not needing returned data currently passes through interface as it.
As shown in figure 8, the concurrent access process of shared storage of the embodiment of the present invention may be implemented by device shown in fig. 6
Method, the method can specifically include following steps:
Step 801: storage access is sent on each access interface Slave0~Slave3 by access originator by shared bus,
Judge whether receive new multiple storage access according to the total depth of 4 access queues in Slave0~Slave3, it will
The storage access of receiving is put into access queue；
Wherein, each access interface preferentially receives corresponding storage access.The gross space of 4 access queues is insufficient
When, it can be chosen according to application characteristic according to any strategy arbitration and receive or do not receive new storage access.
Step 802: the access selecting module of shared storage access exchange administrative unit from respectively correspond Slave0~
Receive in still unfinished storage access on 32 positions of 4 access queues of Slave3, selection 4 for ignoring sequence
The storage access for not having Bank to conflict, and give the ID of selected storage access to shared storage access switch management module
Transmission state update module；
Wherein, it can be arbitrated according to any strategy when selection storage access, it is preferred that emphasis is from 32 of four access queues
The arbitrarily one or more storage access of selection carry out parallel processing on position, but the storage access number that simultaneous selection comes out is not
Greater than the logic number of blocks of shared memory.In the embodiment of the present invention, selected storage access number be no more than 4 it is (total
Number of ports).
Step 803: the parallel decoding module of shared storage access exchange administrative unit, which stores selected Lothrus apterus, visits
It asks parallel decoding, and gives corresponding Bank；
Step 804: ID of the transmission state update module based on each storage access, update its transmission state (transmit into
Degree), notify access interface to remove storage access from access queue if just completing transmission.
Step 805: the interface selecting module of shared storage access exchange administrative unit is each feedback coefficient for needing to return
The access interface passed through according to selection.
Here, for each feedback data for needing to return, any one access interface is selected as it and passes through interface.It is excellent
First select the corresponding access interface of feedback data as by interface, it, can be with for there are other feedback data of interface conflict
Any one is selected not need the access interface of returned data as passing through interface.Interface selection strategy can be with flexible setting, this
Inventive embodiments are with no restrictions.
Step 806: the interface selecting module of shared storage access exchange administrative unit is by feedback data and its with information
Give access interface；
It wherein, mainly include that the ID of storage access and feedback data corresponding to feedback data to be walked with information
Access interface be to pass through the mark of interface.
Step 807: access interface receive feedback data and its with information, feedback data is passed through according to information
Shared bus returns to access originator.
Wherein, it according to the adjoint information of feedback data each of in Slave0~Slave3, chooses whether to receive described anti-
Data are presented, if received with identical as self identification by the mark of interface in information, and are stored according in adjoint information
The feedback data is returned to corresponding access originator by shared bus by the ID of access；Otherwise do not receive feedback data, also not
Carry out subsequent data return processing.
For not needing the access of returned data, such as read access, process can be terminated to step 804；To needing to return
The access of feedback data, such as write access, process to 807 terminate.
In above step, step 802 and step 805 are the main reason for shared storage access bandwidth are improved；Step
Rapid 801 and step 807 be reformed AHP and flexible Application to existing interior data bus protocol, be that this method can be effective
The subsidiary conditions used.
Compared with the ameliorative way and device of existing various shared memory interface bandwidth, using method of the present invention
And device, it has a characteristic that
1) it in the storage access arbitration to each interface, in conjunction with outstanding function, dispatches and responds out of sequence,
Bank conflict when multiport storage access is reduced to greatest extent, improves Static RAM (SRAM, Static
RAM entrance and exit bandwidth).
2) in multiple concurrently access generations, each access interface does not work independently, and is managed collectively queue resource,
It eliminates and the access interface queue full come is accessed and other access interfaces cannot receive new access when having vacant and be brought
Bandwidth loss.
3) when multiple data return, the mode wherefrom where gone back and forth originally is abandoned, returned data can be walked any
One interface returns, and the return time delay that each interface is walked in control is consistent, and bus to returned data is routed according to ID, in this way will not
There is any adverse effect, to take full advantage of the outlet bandwidth of interface offer.
Assuming that only one Block and access interface of SRAM, it is clear that address patter when this mode and access
It is unrelated, it is assumed that the bus bandwidth of individual interface is 1 (normalizated unit), then the access bandwidth that storage is shared under the program is just
1。
1) four independent bus line interfaces and four independent Block, if using commonsense method, 4 concurrent access originators
It will appear following several situations:
4 addresses concurrently accessed just fall in four different Block, bandwidth 4*1=4.
4 addresses concurrently accessed have fallen in three different Block, bandwidth 3*1=3.
4 addresses concurrently accessed have fallen in two different Block, bandwidth 2*1=2.
4 addresses concurrently accessed have fallen in the same Block, bandwidth 1.
Assuming that the access address of each access originator is mutually indepedent and access address is evenly distributed, and of total access situation
Number are as follows:
N=44=256=N1+N2+N3+N4
4 addresses concurrently accessed just fall in the probability of four different Block are as follows: N4/N=9.38%.
4 addresses concurrently accessed have fallen in the probability of three different Block are as follows: N3/N=56.25%.
4 addresses concurrently accessed have fallen in the probability of two different Block are as follows: N2/N=32.81%.
4 addresses concurrently accessed have fallen in the probability of the same Block are as follows: N1/N=1.56%.
Average bandwidth in this way under the program are as follows: B=B1*P1+B2*P2+B2*P2+B2*P2=4*9.38%+3*
56.25%+2*32.81%+1*1.56%=2.73.
2) device and method provided in an embodiment of the present invention are used, it is assumed that shared bus can support most 16
The unordered function of outstanding, that is, each access originator averagely support the unordered function of 4 outstanding；Memory
It is divided into 4 logically independent Block, each Block points of 4 Bank for interleave address.Under this scheme, the institute from 16 ID
4 concurrent access originators of selection will appear following several situations:
4 addresses concurrently accessed just fall in four different Bank, bandwidth 4*1G=4.
4 addresses concurrently accessed have fallen in three different Bank, bandwidth 3*1=3.
4 addresses concurrently accessed have fallen in two different Bank, bandwidth 2*1=2.
4 addresses concurrently accessed have fallen in the same Bank, bandwidth 1.
Assuming that the access address of each access originator is mutually indepedent and access address is evenly distributed, and of total access situation
Number are as follows:
N=N1+N2+N3+N4=1616=18446744073709551616
N4=N-N1-N2-N3=18446744049705622576
4 addresses concurrently accessed just fall in the probability of four different block are as follows: N4/N=99.99%.
4 addresses concurrently accessed have fallen in the probability of three different block are as follows: N3/N=0.001%.
4 addresses concurrently accessed have fallen in the probability of two different block are as follows: N2/N=0.00%.
4 addresses concurrently accessed have fallen in the probability of the same block are as follows: N1/N=0.00.
Average bandwidth in this way under the program are as follows: B=B1*P1+B2*P2+B2*P2+B2*P2=4*99.99%+3*
0.01%+2*0.00%+1*0.00%=4.
Therefore, it compares with common four independent bus line Interference fits, four independent Block, embodiment of the present invention side
Income brought by method and device promotes 46.5% compared to common method bandwidth.
Obviously, those skilled in the art should be understood that each module of the above invention or each step can be with general
Computing device realize that they can be concentrated on a single computing device, or be distributed in multiple computing devices and formed
Network on, optionally, they can be realized with the program code that computing device can perform, it is thus possible to which they are stored
It is performed by computing device in the storage device, and in some cases, it can be to be different from shown in sequence execution herein
Out or description the step of, perhaps they are fabricated to each integrated circuit modules or by them multiple modules or
Step is fabricated to single integrated circuit module to realize.In this way, the present invention is not limited to any specific hardware and softwares to combine.
The foregoing is only a preferred embodiment of the present invention, is not intended to limit the scope of the present invention.
Claims (11)
1. the shared concurrent access processing method of storage of one kind, which is characterized in that the described method includes:
For the access queue on each access interface, from any one or more access queues arbitrarily select do not complete
Storage accesses, and there is no heap Bank to conflict between selected storage access；
Parallel decoding is accessed to selected storage, and is transferred to corresponding Bank.
2. the method according to claim 1, wherein the method also includes:
According to the ID of selected storage access, its transmission state is updated at any time；
By it is processed at the ID of storage access inform corresponding access interface so that access interface will store access accordingly
It is removed from access queue.
3. according to claim 1 to 2 described in any item methods, which is characterized in that corresponding one of each access interface contains
The access queue of multiple unfinished transmission, selected storage access is no more than access interface sum.
4. the shared concurrent access process device of storage of one kind, which is characterized in that described device includes: shared bus, multiple access
Interface, shared storage access exchange administrative unit and shared memory, wherein
Shared bus is supported not completing transmission, supports out-of-order pass for providing read/write channel for the storage access from access originator
It is defeated；
Access interface, the storage access for receiving to send by the shared bus, and the storage of receiving access is put into visit
Ask queue；
Shared storage access exchange administrative unit includes: access selecting module and parallel decoding module, wherein
Selecting module is accessed, the access queue for being directed on each access interface, from any one or more visits
Ask that queue arbitrarily selects unfinished storage to access, there is no Bank to conflict between selected storage access；
Parallel decoding module, for it is described access selecting module selection storage access parallel decoding, and be transferred to respectively it is right
The heap Bank answered；
Shared memory, including multiple logical blocks, the logical block and access interface do not have apparent corresponding relationship, each logic
Block includes multiple Bank, and the logical block, which refers to, provides the logic storage unit of continuation address, and Bank is for carrying out address line
The smaller physical memory cell of column interleaving.
5. the shared concurrent access process device of storage according to claim 4, which is characterized in that the shared storage access
Exchanging administrative unit further includes transmission state update module；
The access selecting module is also used to after selection storage access, the ID of selected storage access is sent to described
Transmission state update module；
The transmission state update module updates its transmission state for the ID according to the storage access at any time；And it will
The ID for the storage access that processing is completed informs corresponding access interface；
The access interface, be also used to according to it is processed at storage access ID, will store accordingly access from access team
It is removed in column.
6. according to the described in any item shared concurrent access process devices of storage of claim 4 to 5, which is characterized in that Mei Gesuo
The corresponding access queue containing multiple unfinished transmission of access interface is stated, selected storage access is total no more than access interface
Number.
7. the shared concurrent access processing method of storage of one kind, which is characterized in that the described method includes:
For each feedback data for needing to return, any one access interface is selected as it and passes through interface；
Access interface is given by feedback data and its with information, and adjoint the information includes to access ID and described by interface
Mark.
8. the method according to the description of claim 7 is characterized in that select any one access interface as it by interface,
Include:
The corresponding access interface of the feedback data is preferentially selected as it and passes through interface；
If the corresponding access interface of the feedback data there are access conflict, selects any one not need currently to return to number
According to access interface pass through interface as it.
9. the method according to the description of claim 7 is characterized in that the method also includes:
Access interface receives the feedback data and its with information, and is passed through the feedback data according to the adjoint information
Shared bus returns to access originator.
10. the shared concurrent access process device of storage of one kind, which is characterized in that described device includes: shared bus, multiple access
Interface, shared storage access exchange administrative unit and shared memory, wherein
Shared bus is supported not completing transmission, supports out-of-order pass for providing read/write channel for the storage access from access originator
It is defeated；
Access interface, the storage access for receiving to send by the shared bus, and the storage of receiving access is put into visit
Ask queue；And for the adjoint information according to feedback data, the feedback data returned will be needed to return by the shared bus
Back to access originator；
Shared storage access exchange administrative unit includes: interface selecting module, for the feedback data for storage access, selection
Any one of access interface gives access interface by interface, and by the feedback data and its with information as it,
The adjoint information includes the ID and the mark by interface that the corresponding storage of the feedback data accesses；
Shared memory, including multiple logical blocks, each logical block include multiple Bank, and the logical block refers to offer continuously
The logic storage unit of location, Bank are the smaller physical memory cells for carrying out address file intertexture.
11. the shared concurrent access process device of storage according to claim 10, which is characterized in that the interface selects mould
Block is used to select any one access interface for each feedback data for needing to return as it and pass through interface, comprising:
For each feedback data for needing to return, preferentially selecting the corresponding access interface of feedback data as it passes through interface；
If there are access conflicts for the corresponding access interface of the feedback data, any one is selected not need returned data currently
Access interface passes through interface as it.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410526653.3A CN105446935B (en) | 2014-09-30 | 2014-09-30 | It is shared to store concurrent access processing method and device |
| PCT/CN2015/077552 WO2016050059A1 (en) | 2014-09-30 | 2015-04-27 | Shared storage concurrent access processing method and device, and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410526653.3A CN105446935B (en) | 2014-09-30 | 2014-09-30 | It is shared to store concurrent access processing method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105446935A CN105446935A (en) | 2016-03-30 |
| CN105446935B true CN105446935B (en) | 2019-07-19 |
Family
ID=55557153
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410526653.3A Active CN105446935B (en) | 2014-09-30 | 2014-09-30 | It is shared to store concurrent access processing method and device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN105446935B (en) |
| WO (1) | WO2016050059A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109902041A (en) * | 2019-03-11 | 2019-06-18 | 中国核动力研究设计院 | A kind of SDRAM driver design method based on FPGA |
| CN109960664B (en) * | 2019-03-19 | 2023-05-02 | 西安微电子技术研究所 | FIFO control device for unified allocation and independent use of capacity shared by multiple modules |
| CN113435153B (en) * | 2021-06-04 | 2022-07-22 | 上海天数智芯半导体有限公司 | Method for designing digital circuit interconnected by GPU (graphics processing Unit) cache subsystems |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1613060A (en) * | 2001-11-06 | 2005-05-04 | 因芬尼昂技术股份公司 | Improved architecture with shared memory |
| CN1703685A (en) * | 2002-09-30 | 2005-11-30 | 艾利森电话股份有限公司 | Method and memory controller for scalable multi-channel memory access |
| CN101236741A (en) * | 2008-01-24 | 2008-08-06 | 华为技术有限公司 | Data reading and writing method and device |
| CN102622192A (en) * | 2012-02-27 | 2012-08-01 | 北京理工大学 | Weak correlation multiport parallel store controller |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080320016A1 (en) * | 2007-06-19 | 2008-12-25 | Raza Microelectronics, Inc. | Age matrix for queue dispatch order |
| US20110296078A1 (en) * | 2010-06-01 | 2011-12-01 | Qualcomm Incorporated | Memory pool interface methods and apparatuses |
-
2014
- 2014-09-30 CN CN201410526653.3A patent/CN105446935B/en active Active
-
2015
- 2015-04-27 WO PCT/CN2015/077552 patent/WO2016050059A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1613060A (en) * | 2001-11-06 | 2005-05-04 | 因芬尼昂技术股份公司 | Improved architecture with shared memory |
| CN1703685A (en) * | 2002-09-30 | 2005-11-30 | 艾利森电话股份有限公司 | Method and memory controller for scalable multi-channel memory access |
| CN101236741A (en) * | 2008-01-24 | 2008-08-06 | 华为技术有限公司 | Data reading and writing method and device |
| CN102622192A (en) * | 2012-02-27 | 2012-08-01 | 北京理工大学 | Weak correlation multiport parallel store controller |
Non-Patent Citations (1)
| Title |
|---|
| 一种基于共享存储器的通信同步机制的实现方式;罗康义等;《舰船电子工程》;20041231;第24卷(第3期);第89-92页 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105446935A (en) | 2016-03-30 |
| WO2016050059A1 (en) | 2016-04-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100585414B1 (en) | Data storage system | |
| KR0150072B1 (en) | Device for controlling memory data path in parallel processing computer system | |
| US7660951B2 (en) | Atomic read/write support in a multi-module memory configuration | |
| CN104471555B (en) | Multi-hierarchy interconnect system and method | |
| CN108139882B (en) | Implement the system and method for stratum's distribution lists of links for network equipment | |
| CN108701081A (en) | Device and method for the multiple subregions for accessing nonvolatile memory simultaneously | |
| KR100590387B1 (en) | Apparatus and method for efficiently sharing memory bandwidth in a network processor | |
| US9841913B2 (en) | System and method for enabling high read rates to data element lists | |
| JP2002510079A (en) | Method and apparatus for forcing ordered execution of reads and writes between memory interfaces | |
| EP3758318A1 (en) | Shared memory mesh for switching | |
| US7366854B2 (en) | Systems and methods for scheduling memory requests utilizing multi-level arbitration | |
| US7512729B2 (en) | Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency | |
| CN105446935B (en) | It is shared to store concurrent access processing method and device | |
| CN108139867B (en) | For realizing the system and method for the high read rate to data element list | |
| US20230185736A1 (en) | Packet processing system, method and device utilizing a port client chain | |
| WO2006071714A1 (en) | Multiple cell computer systems and methods | |
| CN106326143B (en) | A kind of caching distribution, data access, data transmission method for uplink, processor and system | |
| US9195622B1 (en) | Multi-port memory that supports multiple simultaneous write operations | |
| JPH0635874A (en) | Parallel processor | |
| US20230111351A1 (en) | Topology of accelerators | |
| CN107835134B (en) | Port access arbitration method and device applied to Ethernet switching chip | |
| CN110214437A (en) | The system and method redistributed for memory access token | |
| CN108139767A (en) | Implement the system and method for distributed lists of links for network equipment | |
| CN100422978C (en) | Integrated circuit with a plurality of communicating digital signal processors | |
| CN106057226B (en) | The access control method of dual-port storage system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |