CN105446213A - Intelligent digital strain ammeter control system for resonant signal identification circuit - Google Patents
Intelligent digital strain ammeter control system for resonant signal identification circuit Download PDFInfo
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- CN105446213A CN105446213A CN201510848915.2A CN201510848915A CN105446213A CN 105446213 A CN105446213 A CN 105446213A CN 201510848915 A CN201510848915 A CN 201510848915A CN 105446213 A CN105446213 A CN 105446213A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24215—Scada supervisory control and data acquisition
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Abstract
The invention discloses an intelligent digital strain ammeter control system for a resonant signal identification circuit. The intelligent digital strain ammeter control system comprises a signal acquisition unit, a processor, an analysis unit, a signal classification unit, a signal confirmation unit, a protection unit, a selection unit and a display unit, wherein both the analysis unit and the signal classification unit are connected with the processor; the signal confirmation unit is connected with the signal classification unit; both the protection unit and the selection unit are connected with the signal confirmation unit; and the display unit is connected with the selection unit. The intelligent digital strain ammeter control system is characterized in that a resonant signal identification circuit is also connected in series between the processor and the signal classification unit; and a digital strain circuit is also connected in series between the signal acquisition unit and the processor. The intelligent digital strain ammeter control system utilizes the resonant signal identification circuit; and under the resonant state of the resonant signal identification circuit, the current total impedance of the system can achieve the extreme value so that the circuit can effectively identify the different information transmitted from the processor and leakage of the privacy of a user terminal can be effectively prevented.
Description
Technical field
The present invention relates to electrical equipment technical field, specifically refer to a kind of intelligent digital strain ammeter control system of resonant mode signal recognition circuit.
Background technology
At present, the development built along with China's intelligent grid, people are also increasing substantially to the demand of intelligent electric meter.But existing intelligent electric meter, because of the imperfection of its control system, easily cause the details of user to be revealed to Utilities Electric Co. inadvertently, and the leakage of these information may bring serious consequence to consumer.Therefore, provide a kind of and can guarantee that the privacy of user is not then seemed excellent in important by the control system of the intelligent electric meter revealed.
Summary of the invention
The object of the invention is to overcome ammeter in prior art and easily reveal the defect of privacy of user, the invention provides a kind of intelligent digital strain ammeter control system of resonant mode signal recognition circuit.
The present invention is achieved through the following technical solutions: a kind of intelligent digital strain ammeter control system of resonant mode signal recognition circuit, primarily of processor, information acquisition unit, the analytic unit be all connected with processor and signal sort out unit, the signal confirmation unit that unit is connected is sorted out with signal, the protected location be all connected with signal confirmation unit and selection unit, the display unit be connected with selection unit, be serially connected in the digital strain unit between information acquisition unit and processor, and be serially connected in the resonant mode signal recognition circuit that processor and signal sort out between unit and form.
Described resonant mode signal recognition circuit is by identification chip U1, not gate IC1, Sheffer stroke gate IC2, Sheffer stroke gate IC3, Sheffer stroke gate IC4, triode VT3, triode VT4, triode VT5, P pole is connected with the base stage of triode VT3 after diode D9 through resistance R14 in turn, the diode D7 that N pole is connected with the base stage of triode VT5, P pole is connected with the base stage of triode VT5 after resistance R15, the diode D8 that N pole is connected as the input end of resonant mode signal recognition circuit and with processor after resistance R13, positive pole is connected with the base stage of triode VT5, the polar capacitor C7 that negative pole is connected with the N pole of diode D8, positive pole is connected with the collector of triode VT5 after resistance R17, the polar capacitor C9 that negative pole is connected with the collector of triode VT3 after resistance R18, one end is connected with the negative pole of polar capacitor C9, the resistance R21 that the other end is connected with the positive pole of Sheffer stroke gate IC4, negative pole is connected with the negative pole of Sheffer stroke gate IC4, positive pole is in turn through polar capacitor C10 that resistance R20 is connected with the emitter of triode VT3 after resistance R19, negative pole is connected with the VDD pin of identification chip U1, the polar capacitor C8 that positive pole is connected with the emitter of triode VT5 after resistance R16, positive pole is connected with the VDD pin of identification chip U1 after resistance R22, the polar capacitor C11 that negative pole is connected with triode VT4 base stage after resistance R25, P pole is connected with the FB pin of identification chip U1, the diode D10 that N pole is connected with the positive pole of Sheffer stroke gate IC2 after resistance R24, P pole is connected with the output terminal of Sheffer stroke gate IC2, the diode D11 that N pole is connected with the negative pole of Sheffer stroke gate IC3, positive pole is connected with the collector of triode VT4, the polar capacitor C12 that negative pole is connected with the output terminal of Sheffer stroke gate IC4 after resistance R23, and positive pole is connected with the output terminal of Sheffer stroke gate IC3, negative pole as resonant mode signal recognition circuit output terminal and sort out with signal the polar capacitor C13 that unit is connected and form, the BD pin of described identification chip U1 is connected with the positive pole of polar capacitor C9, the forward end of its CS pin Sheffer stroke gate IC1 is connected, its GND pin ground connection, the base stage of described triode VT3 is connected with the P pole of diode D8, the reverse end of described not gate IC1 is connected with the negative pole of Sheffer stroke gate IC2, the positive pole of described Sheffer stroke gate IC3 is connected with the emitter of triode VT4, the minus earth of institute polar capacitor C9.
Described digital strain circuit is by process chip U2, amplifier P1, triode VT1, triode VT2, negative pole is connected with the base stage of triode VT2, positive pole is in turn through polar capacitor C5 that resistance R2 is connected with the VDD pin of process chip U2 after diode D1 and resistance R8, one end is connected with the base stage of triode VT2, the resistance R5 that the other end is connected with the EOC pin of process chip U2, be connected with information acquisition unit as the input end of digital strain unit while one end is connected with the positive pole of polar capacitor C5, the resistance R3 that the other end is connected with the REF pin of process chip U2, minus earth, the polar capacitor C1 that positive pole is connected with the VDD pin of process chip U2 after resistance R4, N pole is connected with the emitter of triode VT2 after resistance R6, P pole is in turn through diode D3 that resistance R7 is connected with the OUT pin of process chip U2 after diode D4 and resistance R10, positive pole is connected with the collector of triode VT2, the polar capacitor C2 that negative pole is connected with the P pole of diode D3 after resistance R1, positive pole is connected with the IN pin of process chip U2, the polar capacitor C6 of minus earth, N pole is connected with the VDD pin of process chip U2 after inductance L, the diode D2 that P pole is connected with the DIN pin of process chip U2, positive pole is connected with the N pole of diode D2 after resistance R9, the polar capacitor C3 that negative pole is connected with the base stage of triode VT1, positive pole is connected with the emitter of triode VT1, the polar capacitor C4 that negative pole is connected with the CS pin of process chip U2 after diode D5, and P pole is connected with the collector of triode VT1 after resistance R11, the diode D6 that N pole is connected with the output terminal of amplifier P1 after resistance R12 forms, the negative pole of described amplifier P1 is connected with the OUT pin of process chip U2, its positive pole is connected with the negative pole of polar capacitor C4, its output terminal as digital strain circuit output terminal and be connected with processor, the IN pin of described process chip U2 is connected with the N pole of diode D3, its GND pin ground connection.
Further, described signal confirmation unit is also connected with SIM unit; Described selection unit is also connected with encrypted tunnel; For guaranteeing best result of use of the present invention, described process chip U2 is MAX1494 integrated chip; Described identification chip U1 is SOT-23-5 integrated chip.
The present invention compared with prior art has the following advantages and beneficial effect:
(1) under the resonant condition of resonant mode signal recognition circuit of the present invention, the electric current resulting impedance that this intelligent electric meter controls system can reach extreme value, therefore, the different information that processor transmits can be carried out identifying and being separated by this resonant mode signal recognition circuit, can prevent the privacy of user side from being revealed.
(2) the different load data message of current through meter can be converted to different signal codes by digital strain unit of the present invention, thus effectively ensure that the privacy information of user side is not revealed.
(3) signal of the present invention sorts out the signal wave information decomposition generated after processor can be changed by unit is privacy information and general information, thus improve intelligent electric meter control system of the present invention to the accuracy of user profile Classification Management, ensure that the privacy information of user side is not revealed simultaneously.
Accompanying drawing explanation
Fig. 1 is one-piece construction block diagram of the present invention.
Fig. 2 is the electrical block diagram of digital strain circuit of the present invention.
Fig. 3 is the electrical block diagram of resonant mode signal recognition circuit of the present invention.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited thereto.
As shown in Figure 1, the present invention is primarily of information acquisition unit, processor, the analytic unit be all connected with processor and signal sort out unit, the signal confirmation unit that unit is connected is sorted out with signal, the protected location be all connected with signal confirmation unit and SIM unit and selection unit, the display unit be all connected with selection unit and encrypted tunnel, input end is connected with information acquisition unit, the digital strain unit that its output terminal is connected with processor, and input end is connected with processor, its output terminal and signal are sorted out the resonant mode signal recognition circuit that unit is connected and are formed.
During enforcement, the different load data message of the current through meter that information acquisition unit gathers by digital strain circuit of the present invention is converted to different signal codes, described analytic unit measures load parameter by analyzing this signal code, to draw the information such as electrical equipment kind and electricity of electricity consumption.Simultaneously, system thresholds is provided with in this analytic unit, private data and general data is drawn by comparing with threshold data, this analytic unit analysis is transferred to two groups that draw different information datas after processor carries out information processing simultaneously to be transmitted through resonant mode signal recognition circuit, under the resonant condition of this resonant mode signal recognition circuit, the electric current resulting impedance of native system can reach extreme value, thus this resonant mode signal recognition circuit can effectively identify the different information of processor transmission and be separated and be transferred to signal classification unit accurately.This signal is sorted out unit and is then reaffirmed being sent to information confirmation unit after the privacy information in this information and general information classification packing, and is left in protected location by privacy information.
Due to, being separated privacy signal is very important systems engineering, so be also provided with selection unit in the present invention, information can be carried out classification and be exported by described selection unit, electric quantity data information is sent to display unit by this selection unit, and this display unit is for showing the electricity of ammeter.Described selection unit transfers out after then sending to encrypted tunnel to be encrypted other electric charge parameter information, and this just effectively avoids the private data sent in data and is revealed.
In order to better implement the present invention, described SIM unit is arranged in confirmation unit, is also provided with signal receiver and signal projector in this SIM unit.When user allows, user can send and allow code to SIM unit, and this SIM unit just can send and allow access instruction and confirm that password is to signal confirmation unit, and the data in described protected location can send through encrypted tunnel.Arranging of SIM unit can also facilitate the metering situation of user's real-time query ammeter and arrange payment reminding service simultaneously.
As shown in Figure 2, described digital strain circuit by process chip U2, amplifier P1, triode VT1, triode VT2, resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R10, resistance R11, resistance R12, polar capacitor C1, polar capacitor C2, polar capacitor C3, polar capacitor C4, polar capacitor C5, polar capacitor C6, diode D1, diode D2, diode D3, diode D4, diode D5, and diode D6 forms.
During connection, the negative pole of polar capacitor C5 is connected with the base stage of triode VT2, its positive pole is connected with the P pole of diode D1 after resistance R2, and the N pole of described diode D1 is connected with the VDD pin of process chip U2 after resistance R8.One end of resistance R5 is connected with the base stage of triode VT2, the other end is connected with the EOC pin of process chip U2.While one end of resistance R3 is connected with the positive pole of polar capacitor C5 as the input end of digital strain unit and be connected with information acquisition unit, the other end is connected with the REF pin of process chip U2.
Wherein, the minus earth of polar capacitor C1, positive pole are connected with the VDD pin of process chip U2 after resistance R4.The N pole of diode D3 is connected with the emitter of triode VT2 after resistance R6, its P pole is connected with the P pole of diode D4 after resistance R7, and the N pole of described diode D4 is connected with the OUT pin of process chip U2 after resistance R10.The positive pole of polar capacitor C2 is connected with the collector of triode VT2, negative pole is connected with the P pole of diode D3 after resistance R1.The positive pole of polar capacitor C6 is connected with the IN pin of process chip U2, minus earth.
Meanwhile, the N pole of diode D2 is connected with the VDD pin of process chip U2 after inductance L, P pole is connected with the DIN pin of process chip U2.The positive pole of polar capacitor C3 is connected with the N pole of diode D2 after resistance R9, negative pole is connected with the base stage of triode VT1.The positive pole of polar capacitor C4 is connected with the emitter of triode VT1, its negative pole is connected with the N pole of diode D5, and the P pole of described diode D5 is then connected with the CS pin of process chip U2.The P pole of diode D6 is connected with the collector of triode VT1 after resistance R11, N pole is connected with the output terminal of amplifier P1 after resistance R12.
The negative pole of described amplifier P1 is connected with the OUT pin of process chip U2, its positive pole is connected with the negative pole of polar capacitor C4, its output terminal as digital strain circuit output terminal and be connected with processor; The IN pin of described process chip U2 is connected with the N pole of diode D3, its GND pin ground connection.
Different load data message is converted to different signal codes to better realize by digital strain circuit of the present invention, and the process chip U2 in the present invention have employed the MAX1494 integrated chip of 8.Resistance R3 and diode D1 and inductance L are wherein connected in series between the REF pin of MAX1494 integrated chip and DIN pin to realize the gain of different pieces of information signal, EOC pin and resistance R5 and the element such as triode VT2 and diode D3 form input bridge, and this input bridge is used for the difference of detection signal.The different signal code generated after the conversion of MAX1494 integrated chip amplifies output channel by the signal formed by amplifier P1 and the element such as diode D5 and polar capacitor C4 after CS pin and OUT pin and exports.
As shown in Figure 3, described resonant mode signal recognition circuit is by identification chip U1, not gate IC1, Sheffer stroke gate IC2, Sheffer stroke gate IC3, Sheffer stroke gate IC4, triode VT3, triode VT4, triode VT5, resistance R13, resistance R14, resistance R15, resistance R16, resistance R17, resistance R18, resistance R19, resistance R20, resistance R21, resistance R22, resistance R23, resistance R24, resistance R25, polar capacitor C7, polar capacitor C8, polar capacitor C9, polar capacitor C10, polar capacitor C11, polar capacitor C12, polar capacitor C13, diode D7, diode D8, diode D9, diode D10, and diode D11 forms.
During connection, the N pole of diode D7 is connected with the base stage of triode VT5, its P pole is connected with the P pole of diode D9 after resistance R14, and the N pole of described diode D9 is connected with the base stage of triode VT3.The P pole of diode D8 is connected with the base stage of triode VT5 after resistance R15, N pole is connected with processor as the input end of resonant mode signal recognition circuit after resistance R13.The positive pole of polar capacitor C7 is connected with the base stage of triode VT5, negative pole is connected with the N pole of diode D8.The positive pole of polar capacitor C9 is connected with the collector of triode VT5 after resistance R17, negative pole is connected with the collector of triode VT3 after resistance R18.One end of resistance R21 is connected with the negative pole of polar capacitor C9, the other end is connected with the positive pole of Sheffer stroke gate IC4.
Wherein, the negative pole of polar capacitor C10 is connected with the negative pole of Sheffer stroke gate IC4, positive pole is connected with the emitter of triode VT3 after resistance R19 through resistance R20 in turn.The negative pole of polar capacitor C8 is connected with the VDD pin of identification chip U1, positive pole is connected with the emitter of triode VT5 after resistance R16.The positive pole of polar capacitor C11 is connected with the VDD pin of identification chip U1 after resistance R22, negative pole is connected with triode VT4 base stage after resistance R25.The P pole of diode D10 is connected with the FB pin of identification chip U1, N pole is connected with the positive pole of Sheffer stroke gate IC2 after resistance R24.
Meanwhile, the P pole of diode D11 is connected with the output terminal of Sheffer stroke gate IC2, N pole is connected with the negative pole of Sheffer stroke gate IC3.The positive pole of polar capacitor C12 is connected with the collector of triode VT4, negative pole is connected with the output terminal of Sheffer stroke gate IC4 after resistance R23.The positive pole of polar capacitor C13 is connected with the output terminal of Sheffer stroke gate IC3, negative pole as resonant mode signal recognition circuit output terminal and sort out unit with signal and be connected.
The BD pin of described identification chip U1 is connected with the positive pole of polar capacitor C9, the forward end of its CS pin Sheffer stroke gate IC1 is connected, its GND pin ground connection; The base stage of described triode VT3 is connected with the P pole of diode D8; The reverse end of described not gate IC1 is connected with the negative pole of Sheffer stroke gate IC2; The positive pole of described Sheffer stroke gate IC3 is connected with the emitter of triode VT4; The minus earth of institute polar capacitor C9.
For better implementing the present invention, described identification chip U1 have employed SOT-23-5 integrated chip, and this chip has extremely strong resonant capacity, effectively raises the information identification accuracy of this unit.
As mentioned above, just the present invention can well be realized.
Claims (6)
1. the intelligent digital strain ammeter control system of a resonant mode signal recognition circuit, primarily of processor, information acquisition unit, the analytic unit be all connected with processor and signal sort out unit, the signal confirmation unit that unit is connected is sorted out with signal, the protected location be all connected with signal confirmation unit and selection unit, and the display unit be connected with selection unit forms; It is characterized in that: sort out between unit at processor and signal and be also serially connected with resonant mode signal recognition circuit, between signal gathering unit and processor, be also serially connected with digital strain circuit.
2. the intelligent digital strain ammeter control system of a kind of resonant mode signal recognition circuit according to claim 1, it is characterized in that, described resonant mode signal recognition circuit is by identification chip U1, not gate IC1, Sheffer stroke gate IC2, Sheffer stroke gate IC3, Sheffer stroke gate IC4, triode VT3, triode VT4, triode VT5, P pole is connected with the base stage of triode VT3 after diode D9 through resistance R14 in turn, the diode D7 that N pole is connected with the base stage of triode VT5, P pole is connected with the base stage of triode VT5 after resistance R15, the diode D8 that N pole is connected as the input end of resonant mode signal recognition circuit and with processor after resistance R13, positive pole is connected with the base stage of triode VT5, the polar capacitor C7 that negative pole is connected with the N pole of diode D8, positive pole is connected with the collector of triode VT5 after resistance R17, the polar capacitor C9 that negative pole is connected with the collector of triode VT3 after resistance R18, one end is connected with the negative pole of polar capacitor C9, the resistance R21 that the other end is connected with the positive pole of Sheffer stroke gate IC4, negative pole is connected with the negative pole of Sheffer stroke gate IC4, positive pole is in turn through polar capacitor C10 that resistance R20 is connected with the emitter of triode VT3 after resistance R19, negative pole is connected with the VDD pin of identification chip U1, the polar capacitor C8 that positive pole is connected with the emitter of triode VT5 after resistance R16, positive pole is connected with the VDD pin of identification chip U1 after resistance R22, the polar capacitor C11 that negative pole is connected with triode VT4 base stage after resistance R25, P pole is connected with the FB pin of identification chip U1, the diode D10 that N pole is connected with the positive pole of Sheffer stroke gate IC2 after resistance R24, P pole is connected with the output terminal of Sheffer stroke gate IC2, the diode D11 that N pole is connected with the negative pole of Sheffer stroke gate IC3, positive pole is connected with the collector of triode VT4, the polar capacitor C12 that negative pole is connected with the output terminal of Sheffer stroke gate IC4 after resistance R23, and positive pole is connected with the output terminal of Sheffer stroke gate IC3, negative pole as resonant mode signal recognition circuit output terminal and sort out with signal the polar capacitor C13 that unit is connected and form, the BD pin of described identification chip U1 is connected with the positive pole of polar capacitor C9, the forward end of its CS pin Sheffer stroke gate IC1 is connected, its GND pin ground connection, the base stage of described triode VT3 is connected with the P pole of diode D8, the reverse end of described not gate IC1 is connected with the negative pole of Sheffer stroke gate IC2, the positive pole of described Sheffer stroke gate IC3 is connected with the emitter of triode VT4, the minus earth of institute polar capacitor C9.
3. the intelligent digital strain ammeter control system of a kind of resonant mode signal recognition circuit according to claim 2, it is characterized in that, described digital strain circuit is by process chip U2, amplifier P1, triode VT1, triode VT2, negative pole is connected with the base stage of triode VT2, positive pole is in turn through polar capacitor C5 that resistance R2 is connected with the VDD pin of process chip U2 after diode D1 and resistance R8, one end is connected with the base stage of triode VT2, the resistance R5 that the other end is connected with the EOC pin of process chip U2, be connected with information acquisition unit as the input end of digital strain unit while one end is connected with the positive pole of polar capacitor C5, the resistance R3 that the other end is connected with the REF pin of process chip U2, minus earth, the polar capacitor C1 that positive pole is connected with the VDD pin of process chip U2 after resistance R4, N pole is connected with the emitter of triode VT2 after resistance R6, P pole is in turn through diode D3 that resistance R7 is connected with the OUT pin of process chip U2 after diode D4 and resistance R10, positive pole is connected with the collector of triode VT2, the polar capacitor C2 that negative pole is connected with the P pole of diode D3 after resistance R1, positive pole is connected with the IN pin of process chip U2, the polar capacitor C6 of minus earth, N pole is connected with the VDD pin of process chip U2 after inductance L, the diode D2 that P pole is connected with the DIN pin of process chip U2, positive pole is connected with the N pole of diode D2 after resistance R9, the polar capacitor C3 that negative pole is connected with the base stage of triode VT1, positive pole is connected with the emitter of triode VT1, the polar capacitor C4 that negative pole is connected with the CS pin of process chip U2 after diode D5, and P pole is connected with the collector of triode VT1 after resistance R11, the diode D6 that N pole is connected with the output terminal of amplifier P1 after resistance R12 forms, the negative pole of described amplifier P1 is connected with the OUT pin of process chip U2, its positive pole is connected with the negative pole of polar capacitor C4, its output terminal as digital strain circuit output terminal and be connected with processor, the IN pin of described process chip U2 is connected with the N pole of diode D3, its GND pin ground connection.
4. the intelligent digital strain ammeter control system of a kind of resonant mode signal recognition circuit according to claim 3, is characterized in that, described selection unit is also connected with encrypted tunnel.
5. the intelligent digital strain ammeter control system of a kind of resonant mode signal recognition circuit according to claim 4, it is characterized in that, described signal confirmation unit is also connected with SIM unit.
6. the intelligent digital strain ammeter control system of a kind of resonant mode signal recognition circuit according to claim 5, it is characterized in that, described process chip U2 is MAX1494 integrated chip; Described identification chip U1 is SOT-23-5 integrated chip.
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| CN201510848915.2A CN105446213A (en) | 2015-11-27 | 2015-11-27 | Intelligent digital strain ammeter control system for resonant signal identification circuit |
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| CN201510848915.2A CN105446213A (en) | 2015-11-27 | 2015-11-27 | Intelligent digital strain ammeter control system for resonant signal identification circuit |
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