CN105427575B

CN105427575B - Receiver

Info

Publication number: CN105427575B
Application number: CN201511019165.4A
Authority: CN
Inventors: 胡剑飞; 季科夫
Original assignee: Shanghai Anlogic Information Science & Technology Co Ltd
Current assignee: Shanghai Anlu Information Technology Co.,Ltd.
Priority date: 2015-12-29
Filing date: 2015-12-29
Publication date: 2019-01-25
Anticipated expiration: 2035-12-29
Also published as: CN105427575A

Abstract

The present invention relates to data transmission technologies, disclose a kind of receiver.In the present invention, receiver receives differential input signal using dual-stage amplifier, first order amplifier sacrifices gain, improves bandwidth, second level amplifier is in the case where bandwidth is not less than first order amplifier, it can achieve higher gain, to realize high-gain high bandwidth simultaneously, and differential-to-single-ended conversion is realized in first order amplifier, can save power consumption and area.

Description

Receiver

Technical field

The present invention relates to data transmission technologies, in particular to receiver.

Background technique

Since the 1990s is released, LVDS (Low Voltage Differential Signaling, low voltage difference Sub-signal) it is used as a kind of data transmission interface technology, with its low amplitude of oscillation, using electric current output and the advantages that strong antijamming capability, It is widely used in high-rate digital transmission field.Due to needing to take into account various application environments, so opposite TX (transmitting Device) for RX (receiver) be more difficult to design.And the performance of RXIO has been largely fixed the performance of entire LVDS RX.Generally By ESD (Electro-Static discharge, Electro-static Driven Comb), input terminal 100ohm resistance and RX front-end circuit, such as put Big device etc. is referred to as RXIO.

As the transmission rate of LVDS is getting faster, especially in some FPGA (Field Programmable Gate Array, field programmable gate array) application in, LVDS interface also needs to receive DDR (Double Date Rate, double data Rate) signal, therefore not only the output data eye figure of LVDS is required, and the duty ratio of output clock also proposed and want It asks.This just proposes increasingly higher demands to the bandwidth of LVDS RXIO.Along with integrated circuit supply voltage increasingly Low, the design of high-performance LVDS RXIO increasingly becomes a kind of challenge.

Summary of the invention

The purpose of the present invention is to provide a kind of receivers, while realizing high-gain high bandwidth, and save power consumption and face Product.

In order to solve the above technical problems, embodiments of the present invention disclose a kind of receiver, including first order amplifier With second level amplifier；

First order amplifier includes:

Input stage circuit, the input stage circuit receive differential input signal and output difference output signal；And

Conversion circuit, the conversion circuit receive differential output signal, differential output signal are converted to single-end output signal, And export the single-end output signal；

Second level amplifier receives single-end output signal, and by output after single-end output signal amplification to driving circuit；

Wherein, the gain of first order amplifier is less than the gain of second level amplifier, and the bandwidth of second level amplifier is not small In the bandwidth of first order amplifier.

Compared with prior art, the main distinction and its effect are embodiment of the present invention:

In the present invention, receiver receives differential input signal using dual-stage amplifier, and first order amplifier sacrifice increases Benefit improves bandwidth, and second level amplifier can achieve higher gain in the case where bandwidth is not less than first order amplifier, To realize high-gain high bandwidth simultaneously, and differential-to-single-ended conversion is realized in first order amplifier, can save power consumption And area.

Further, conversion circuit does not use folded cascode configuration, so as to adapt to low supply voltage work shape Condition.

Further, by introducing the push-pull circuit structure of automatic biasing in the amplifier of the second level, first can be eliminated Grade amplifier hanging output so that circuit performance substantially not with PVT (Process, Voltage and Temperature, i.e., Technique, supply voltage and temperature) variation, so that circuit performance be substantially improved, and by introducing second level amplifier, can make The input of driving circuit is obtained close to full width, so that the output eye figure of receiver and clock duty cycle be made to be greatly improved.

Detailed description of the invention

Fig. 1 is a kind of structural schematic diagram of existing receiver.

Fig. 2 is a kind of circuit diagram of existing receiver.

Fig. 3 is a kind of circuit diagram of existing receiver.

Fig. 4 is a kind of structural schematic diagram of receiver in first embodiment of the invention；

Fig. 5 is a kind of circuit diagram of first order amplifier in receiver in second embodiment of the invention.

Fig. 6 is the circuit diagram of second level amplifier and driving circuit in a kind of receiver in second embodiment of the invention.

Fig. 7 is a kind of circuit diagram of first order amplifier in receiver in second embodiment of the invention.

Fig. 8 is a kind of circuit diagram of second level amplifier in receiver in second embodiment of the invention.

Specific embodiment

In the following description, in order to make the reader understand this application better, many technical details are proposed.But this The those of ordinary skill in field is appreciated that even if without these technical details and many variations based on the following respective embodiments And modification, each claim of the application technical solution claimed can also be realized.

Due to that need to adapt to various application environments, the reception range of signal of LVDS RX is 0~2.4V, wherein common-mode voltage model It encloses for 0.05~2.235V, it is 50mV that minimum single-termination, which receives signal amplitude,.Due to needing support such large-scale incoming level, Need for input stage to be made into rail-to-rail (rail-to-rail).A kind of LVDS RXIO structure of classics is as shown in Figure 1.The first order Rail-to-rail amplifier completes the amplification to input signal amplitude, and the second level is generally digital circuit (phase inverter or buffer), For providing enough drivings to subsequent conditioning circuit.

It is exactly the circuit realization of Fig. 1 structure shown in Fig. 2.Since LVDS is dc-couple (DC-couple), and it is defeated Entering signal level can achieve 2.4V, so the rail-to-rail input pipe of first order amplifier uses I/O device (IO device).Separately Outside, LVDS is transmitted with differential signal, and RXIO just needs the differential signal that will be received to switch to Single-end output.It is total to fold common source Grid (folded-cascode) structure is to complete this function.In order to improve the bandwidth of input stage circuit, in addition to input pipe (Fig. 2 Middle M1 '~M6 '), remaining device can all select kernel (core) device (M7 '~M14 ' is kernel device in Fig. 2).In Fig. 2 INV1 ' and INV2 ' forms a latch (latch), to reduce the up and down time of LVDS output, and gives subsequent electricity Road provides driving enough.

Circuit shown in Fig. 3 is an improvement to Fig. 2 circuit.By introducing cross-coupling (cross- in output stage Couple phase inverter (INV5 ' and INV6 ')) improves the performance of output data eye figure and the duty ratio of clock.

It was found by the inventors of the present invention that LVDS RXIO structure shown in FIG. 1 and Fig. 2, circuit exists centainly shown in 3 Problem:

1. the gain bandwidth product of amplifier has certain upper limit for special process.Therefore high-gain in order to obtain, Low level signal amplification will be inputted, bandwidth will make sacrifices, but this and the LVDS signal transmission rate phase lance that is getting faster now Shield (needs higher circuit bandwidth).Opposite, if bandwidth done greatly, gain will become smaller, cause amplifier output (Fig. 2, Amp_out ' in 3) amplitude is too small, reception failure

2. while realizing high-gain, input is changed from difference using folded cascode configuration for Fig. 2 and Fig. 3 circuit It is single-ended.For the amplifier when VDD supply voltage is higher, what can be worked is preferable, but under deep-submicron, when VDD power supply Voltage drop to 1.2V it is even lower when, the problem of capacity space (headroom) will occur

3. in addition, other two problem can be brought using the amplifier of folded cascode configuration:

A) due to the limitation in capacity space, the output voltage swing (voltage of amp-out ' point) of amplifier will be smaller, thus Cause the duty ratio for exporting clock very poor；

B) when the amplitude of input signal is larger, in addition the gain of folded common source and common grid amplifier is larger, output will appear It is distorted (distortion), to deteriorate output eye figure and clock duty cycle

4. in circuit shown in Fig. 2 and Fig. 3, the output of first order amplifier is all hanging (floating), and they Output be not full width again.Cause subsequent inverter circuit not only to provide certain driving capability in this way, and needs The output of first order amplifier is amplified to full width CMOS (Complementary Metal-Oxide- by certain amplifying power Semiconductor Transistor, complementary metal oxide semiconductor) signal.But it is understood that a phase inverter wants work Make to be to need certain bias voltage, and the output dc point of previous stage is indefinite in amplifier status (floating), this will lead to the eye figure of output signal and clock duty cycle is very poor.

5. for Fig. 3 circuit, a kind of improvement project is to introduce common mode feedback circuit in first order amplifier circuit (CMFB, Common Mode FeedBack), in this way its output amp_outp ' and amp_outn ' can be clamped down on solid to one In constant voltage.The harm done so is:

A) circuit design can become complicated.Due to the introducing of CMFB circuit, there is loop in circuit, steady so as to cause circuit Qualitative can be a problem；

Even if it is no longer hanging b) to introduce CMFB, amp_outp ' and amp_outn ', but they can also be fixed on it is a certain In fixed reference potential.Since the threshold voltage (threshold voltage) of phase inverter can be with PVT (process, voltage Andtemperature, i.e. technique, supply voltage and temperature) do not stop to change, therefore do not ensure that the circuit at all PVT Performance.

To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to implementation of the invention Mode is described in further detail.

First embodiment of the invention is related to a kind of receiver.Fig. 4 is the structural schematic diagram of the receiver.As shown in figure 4, The receiver includes first order amplifier and second level amplifier.

First order amplifier includes:

Input stage circuit, the input stage circuit receive differential input signal inp and inm (such as low-voltage differential input signal) And output difference output signal.And

Conversion circuit, the conversion circuit receive differential output signal, differential output signal are converted to single-end output signal, And export single-end output signal preamp_out.

Second level amplifier receives single-end output signal preamp_out, and will export after single-end output signal amplification Amp_out is to driving circuit.Then, driving circuit output drive signal lvdsrxio_out.

It can be seen that the key of foregoing circuit structure is that the rail-to-rail amplifier of input in Fig. 1 is split into two-stage circuit: First order amplifier and second level amplifier.Since input reference signal is 0~2.4V, input pipe still uses I/O device (relative to kernel device, cutoff frequency can be much lower).So believing for first order amplifier in order to receive high speed Number (> 1Gbps), the difficult point of design is bandwidth.And high bandwidth in order to obtain, it is necessary to which circuit gain is done to small, such as the first order The gain of amplifier can be pressed less than 10dB, preferably in 3~6dB or so, particularly preferably 6dB.In addition, in order to save function Consumption and area, first order amplifier circuit just realize differential-to-single-ended conversion.

It is appreciated that difference can not also be realized to list in first order amplifier in other embodiments of the invention The conversion at end carries out differential-to-single-ended conversion again, is equally able to achieve this hair after amplifier amplifies differential signal in the second level Bright technical solution.

As optional embodiment, the input stage circuit of first order amplifier uses input and output device (I/O device), the The conversion circuit of first stage amplifier uses kernel device.All devices of second level amplifier use kernel device (core device Part).Formula ft=gm/2*pi*cgs, the cutoff frequency ft ratio core of I/O device itself is roughly calculated according to device cutoff frequency The cutoff frequency of device is small, easier than being designed with I/O device with the amplifier of core device design high gain-bandwidth product.Gm is device Part mutual conductance, pi 3.1415926, cgs are the parasitic capacitance of grid and source.

It is appreciated that first order amplifier section is using I/O device, partially using kernel device, the increasing of first order amplifier The upper limit of beneficial bandwidth product is smaller, and for example, 12, bandwidth 3, gain 4.I O power supply voltage domain is completed in first order amplifier to arrive After the conversion in core voltage domain, second level amplifier can use kernel device completely, so that the gain of second level amplifier The upper limit of bandwidth product is larger, and for example, 24, bandwidth 3, gain 8, to realize high-gain simultaneously by dual-stage amplifier High bandwidth.

Furthermore, it is to be understood that second level amplifier can also be not exclusively using interior in other embodiments of the invention Core device, as long as higher gain can be reached in the case where bandwidth is not less than first order amplifier.

Preferably, above-mentioned input stage circuit is current amplification circuit to realize low gain high bandwidth, and above-mentioned conversion circuit is Voltage amplifier circuit or voltage and current Hybrid amplifier circuit are to realize that the gain of follow-up signal is amplified and differential-to-single-ended conversion. Above-mentioned receiver can be applied to interface circuit (especially FPGA circuitry) or be related to the circuit of voltage domain conversion.

In the present embodiment, receiver receives differential input signal using dual-stage amplifier, and first order amplifier is sacrificial Domestic animal gain improves bandwidth, and second level amplifier can achieve higher increasing in the case where bandwidth is not less than first order amplifier Benefit to realize high-gain high bandwidth simultaneously, and realizes differential-to-single-ended conversion in first order amplifier, can save function Consumption and area.

In a preferred embodiment, input stage circuit is rail-to-rail circuit.It is appreciated that the input of " rail-to-rail " finger device part is defeated Voltage range can achieve supply voltage out.

As shown in figure 5, above-mentioned input stage circuit includes the first MOS (Metal Oxide Semiconductor, metal oxygen Compound semiconductor) transistor M1, the second to the tenth MOS transistor M2 to M10, first resistor and second resistance.

The grid of first MOS transistor M1 and the second MOS transistor M2 receive differential input signal inm and inp, first The second pole of MOS transistor M1 and the second MOS transistor M2 link together and connect with the first pole of third MOS transistor M3 It connects, the grid of third MOS transistor M3 connects the first bias voltage signal nbias, the second pole of third MOS transistor M3 and second source VSS connection.

4th MOS transistor M4, the 5th MOS transistor M5, the 6th MOS transistor M6 and the 7th MOS transistor M7 One pole is connect with the first power vd D, and the grid of the 5th MOS transistor M5 and grid, the 4th MOS of the 4th MOS transistor M4 are brilliant The second pole of body pipe M4 is connected with the first pole of the first MOS transistor M1, and the grid of the 7th MOS transistor M7 and the 6th MOS are brilliant The grid of body pipe M6, the second pole of the 6th MOS transistor M6 are connected with the first pole of the second MOS transistor M2.

The grid of 8th MOS transistor M8 and the 9th MOS transistor M9 receives differential input signal inp and inm, and the 8th The first pole of MOS transistor M8 and the 9th MOS transistor M9 link together and connect with the second pole of the tenth MOS transistor M10 It connects, the grid of the tenth MOS transistor M10 connects the second bias voltage signal pbias, the first pole of the tenth MOS transistor M10 and the first electricity Source VDD connection.

First resistor is equal with the impedance value of second resistance, a pole of first resistor and the second of the 8th MOS transistor M8 Pole is connected with the second pole of the 5th MOS transistor M5, a pole of second resistance and the second pole and the 7th of the 9th MOS transistor M9 The second pole of MOS transistor M7 connects, another pole output difference output signal of first resistor and second resistance.

Wherein, first is NMOS transistor to third MOS transistor M1 to M3, and the first of NMOS transistor extremely drains, The extremely source electrode of the second of NMOS transistor, the 4th to the tenth MOS transistor M4 to M10 are PMOS transistor, PMOS transistor First extremely source electrode, the second of PMOS transistor extremely drains.Or

First is PMOS transistor, the extremely source electrode of the first of PMOS transistor, PMOS crystalline substance to third MOS transistor M1 to M3 The second of body pipe extremely drains, and the 4th to the tenth MOS transistor M4 to M10 is NMOS transistor, the first pole of NMOS transistor For drain electrode, the extremely source electrode of the second of NMOS transistor.

As optional embodiment, above-mentioned input stage circuit can be as shown in fig. 7, comprises the first to the tenth MOS crystal Pipe M1 to M10 eliminates first resistor and second resistance compared to Fig. 5, and makes the 11st MOS transistor M11 and the 12nd First resistor, second resistance resistance value in the inverse and Fig. 5 of the mutual conductance of MOS transistor M12 is similar, while nbias voltage is not Higher than VDD, the function of input stage circuit in Fig. 5 equally may be implemented.

Furthermore, it is to be understood that the input stage circuit in first order amplifier can also use other input stage circuit structures, As long as being able to achieve Current amplifier, however it is not limited to the input stage circuit structure in Fig. 5 and Fig. 7.

Second embodiment of the invention is related to a kind of receiver.Second embodiment on the basis of first embodiment into Following improvement is gone.

First is improved to conversion circuit and does not use folded cascode configuration, to adapt to low supply voltage working condition. Specifically:

As shown in figure 5, conversion circuit includes the 11st to the 16th MOS transistor M11 to M16.

The grid reception differential output signal of 11st MOS transistor M11 and the 12nd MOS transistor M12, the 11st MOS transistor M11, the 12nd MOS transistor M12, the 13rd MOS transistor M13 and the 14th MOS transistor M14 second Pole is connect with second source VSS, the grid of the 13rd MOS transistor M13 and the grid and the tenth of the 12nd MOS transistor M12 The first pole of two MOS transistor M12 connects, the grid of the 14th MOS transistor M14 and the grid of the 11st MOS transistor M11 It is connected with the first pole of the 11st MOS transistor M11；

The first pole of 15th MOS transistor M15 and the 16th MOS transistor M16 link together and with the first power supply VDD connection, the grid of the 15th MOS transistor M15 and the second pole, the 13rd MOS transistor of the 15th MOS transistor M15 The first pole of M13 is connected with the grid of the 16th MOS transistor M16, the second pole and the 14th of the 16th MOS transistor M16 The first pole of MOS transistor M14 connects and exports single-end output signal preamp_out.

Wherein, the 11st to the 14th MOS transistor M11 to M14 is NMOS transistor, and the first of NMOS transistor is extremely Drain electrode, the extremely source electrode of the second of NMOS transistor, the 15th MOS transistor M15 and the 16th MOS transistor M16 are PMOS brilliant Body pipe, the extremely source electrode of the first of PMOS transistor, the second of PMOS transistor extremely drain.Or

11st to the 14th MOS transistor M11 to M14 be PMOS transistor, the extremely source electrode of the first of PMOS transistor, The second of PMOS transistor extremely drains, and the 15th MOS transistor M15 and the 16th MOS transistor M16 are NMOS transistor, The first of NMOS transistor extremely drains, the extremely source electrode of the second of NMOS transistor.

It can be seen that one embodiment of the first order amplifier in Fig. 5 is symmetrical amplifier (symmetrical Amplifier) an improvement of circuit, input stage is rail-to-rail circuit, and realizes differential-to-single-ended conversion.The amplifier Input stage still uses I/O device (M1~M9 in Fig. 5).For spread bandwidth, in remaining metal-oxide-semiconductor (M11~M16 in Fig. 5) is selected Core device, wherein M13~M16 work is completed Differential Input in core power voltage domain to single-ended conversion, and completes IO electricity Conversion of the source voltage domain to core power voltage domain.After first order amplifier completes these conversions, second level amplifier is just Kernel device can be used completely, to accomplish high-gain high bandwidth simultaneously.In order to enable circuit to work in 2.5V I O power supply electricity Pressure, all current sources (such as nbias, pbias etc.) do not use cascode structure.

As optional embodiment, above-mentioned conversion circuit can also be as shown in fig. 7, comprises the 11st to the 16th MOS be brilliant Body pipe M11 to M16, it is different from Fig. 5 to be, the first of the grid of the 12nd MOS transistor M12, the 11st MOS transistor M11 Pole and grid connect the first bias voltage signal nbias, the 12nd MOS transistor M12 the first pole and the 13rd MOS transistor M13 and The grid of the M14 of 14th MOS transistor connects.Furthermore, it is to be understood that in other embodiments of the invention, conversion electricity Road can also use folded cascode configuration, as long as the bandwidth of first order amplifier can be improved, equally be able to achieve of the invention Technical solution.

Second is improved to the push-pull circuit structure by introducing automatic biasing in the amplifier of the second level, can eliminate the The hanging output of first stage amplifier so that circuit performance be substantially improved, and is led to so that circuit performance does not change substantially with PVT Cross introducing second level amplifier, the input of driving circuit can be made close to full width, thus make receiver output eye figure and when Clock duty ratio is greatly improved.Specifically:

In order to eliminate the hanging of first order amplifier output point, second level amplifier uses the push-pull circuit knot of automatic biasing Structure.

As shown in fig. 6, second level amplifier includes the 17th MOS transistor M17, the 18th MOS transistor M18 and the Three resistance Rbias.

A pole of 3rd resistor Rbias is connect with the grid of the 17th MOS transistor M17 and the 18th MOS transistor M18 And single-end output signal preamp_out is received, another pole of 3rd resistor Rbias and the first of the 17th MOS transistor M17 Pole connects and outputs signal to driving circuit with the second pole of the 18th MOS transistor M18, and 3rd resistor Rbias is greater than 100k Ω。

The first pole of 18th MOS transistor M18 is connect with the first power vd D, and the second of the 17th MOS transistor M17 Pole is connect with second source VSS.

Wherein, the 17th MOS transistor M17 is NMOS transistor, and the first of NMOS transistor extremely drains, NMOS crystal The extremely source electrode of the second of pipe, the 18th MOS transistor M18 are PMOS transistor, the extremely source electrode of the first of PMOS transistor, PMOS The second of transistor extremely drains.Or

17th MOS transistor M17 be PMOS transistor, the extremely source electrode of the first of PMOS transistor, PMOS transistor Second extremely drains, and the 18th MOS transistor M18 is NMOS transistor, and the first of NMOS transistor extremely drains, NMOS crystal The extremely source electrode of the second of pipe.

As optional embodiment, above-mentioned second level amplifier can be as shown in figure 8, include the 17th to the 23rd MOS transistor M17 to M23.

The grid of 17th MOS transistor M17 connect with the grid of the 22nd MOS transistor M22 and receives single-ended defeated Signal preamp_out out, the 17th MOS transistor M17, the 18th MOS transistor M18, the 20th MOS transistor M20 and The first pole of 22 MOS transistor M22 is connect with the first power vd D, the second pole and the tenth of the 17th MOS transistor M17 The second pole of eight MOS transistor M18, the 18th MOS transistor M18 and the 20th MOS transistor M20 grid and the 19th The first pole of MOS transistor M19 connects；

The grid of 19th MOS transistor M19 and the grid of the 13rd MOS transistor M13 and the 14th MOS transistor M14 Pole connection, the second pole of the 19th MOS transistor M19, the 21st MOS transistor M21 and the 23rd MOS transistor M23 It is connect with second source VSS；

The second pole of 20th MOS transistor M20 and the first pole, the 21st MOS of the 21st MOS transistor M21 The connection of the grid of the grid of transistor M21 and the 23rd MOS transistor M23；

The second pole of 22nd MOS transistor M22 connect and exports with the first pole of the 23rd MOS transistor M23 Signal is to driving circuit.

Wherein, the 19th MOS transistor M19, the 21st MOS transistor M21 and the 23rd MOS transistor M23 are NMOS transistor, the first of NMOS transistor extremely drain, the extremely source electrode of the second of NMOS transistor, the 17th MOS transistor M17, the 18th MOS transistor M18, the 20th MOS transistor M20 and the 22nd MOS transistor M22 are PMOS transistor, The extremely source electrode of the first of PMOS transistor, the second of PMOS transistor extremely drain.Or

19th MOS transistor M19, the 21st MOS transistor M21 and the 23rd MOS transistor M23 are PMOS brilliant Body pipe, the extremely source electrode of the first of PMOS transistor, the second of PMOS transistor extremely drain, the 17th MOS transistor M17, 18 MOS transistor M18, the 20th MOS transistor M20 and the 22nd MOS transistor M22 are NMOS transistor, and NMOS is brilliant The first of body pipe extremely drains, the extremely source electrode of the second of NMOS transistor.

It is equally able to achieve in Fig. 6 in Fig. 8 by the push-pull amplifier that M17, M18, M19, M20, M21, M22 and M23 are formed The push-pull amplifier function of M17, M18 composition.

Furthermore, it is to be understood that in other embodiments of the invention, it can also be using the push-pull type electricity of other automatic biasings Line structure or other amplifier circuit configurations with higher gain, are equally able to achieve technical solution of the present invention.

In one example, as shown in fig. 6, above-mentioned driving circuit includes the 24th MOS transistor M24 and the 25th MOS transistor M25.

The grid of 24th MOS transistor M24 and the 25th MOS transistor M25 receives the defeated of second level amplifier Out, the first pole with the second pole of the 25th MOS transistor M25 of the 24th MOS transistor M24 is connect and output driving is believed Number lvdsrxio_out

The first pole of 25th MOS transistor M25 is connect with the first power vd D, the 24th MOS transistor M24's Second pole is connect with second source VSS.

Wherein, the 24th MOS transistor M24 is NMOS transistor, and the first of NMOS transistor extremely drains, and NMOS is brilliant The extremely source electrode of the second of body pipe, the 25th MOS transistor M25 be PMOS transistor, the extremely source electrode of the first of PMOS transistor, The second of PMOS transistor extremely drains.Or

24th MOS transistor M24 is PMOS transistor, the extremely source electrode of the first of PMOS transistor, PMOS transistor Second extremely drain, the 25th MOS transistor M25 is NMOS transistor, and the first of NMOS transistor extremely drains, NMOS The extremely source electrode of the second of transistor.

Furthermore, it is to be understood that in other embodiments of the invention, it can be using the driving electricity of other circuit structures Road, the circuit structure being not limited in Fig. 6.

It can see by upper, (M17, M18 and Rbias) shown in the left side Fig. 6 is one embodiment of second level amplifier. M24 and M25 is output phase inverter in Fig. 6, provides certain driving capability.

The single-ended amplifier of automatic biasing is by the way that by resistance Rbias one big, (> 100k is reduced under off state with this Leakage current) phase inverter input/output terminal is connected across to realize.The dc point of the circuit is exactly the threshold voltage of phase inverter, So circuit gain can be made big.In addition because using kernel device, circuit bandwidth is also cinch higher.In this way, through Second level amplifying circuit is crossed, exports (amp_out in Fig. 6) substantially close to full width, at this time again through output phase inverter (in Fig. 6 Output stage), signal integrity will improve very big.

Compared to the structure that the circuit in Fig. 3 adds CMFB, since the circuit uses automatic biasing, the direct current of second level amplifier It operating point can be with PVT adjust automatically, so that circuit performance does not change substantially with PVT.

It should be noted that in claims hereof and specification, such as first and second or the like relationship Term is only used to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying There are any actual relationship or orders between these entities or operation.Moreover, the terms "include", "comprise" or its Any other variant is intended to non-exclusive inclusion so that include the process, methods of a series of elements, article or Equipment not only includes those elements, but also including other elements that are not explicitly listed, or further include for this process, Method, article or the intrinsic element of equipment.In the absence of more restrictions, being wanted by what sentence " including one " limited Element, it is not excluded that there is also other identical elements in the process, method, article or apparatus that includes the element.

To sum up, in order to adapt to the transmission rate being getting faster, in lower and lower on-chip power supply voltage and FPGA application Certain special requirements (for example needing to receive DDR signal, and thus requirement of the bring to output clock duty cycle), to figure Circuit shown in structure and Fig. 2/3 shown in 1 is improved, a kind of completely new to meet high-speed high-performance LVDS receiver LVDS RXIO is as shown in Figures 4 to 6.Compared to circuit shown in structure shown in Fig. 1 and Fig. 2/3, the advantages of entire circuit, is:

1. since the bottleneck of circuit bandwidth is the first order (need using I/O device), but because the in structure shown in Fig. 4 The presence of two-stage amplifier, second level amplifier use kernel device to realize completely, and first order amplifier is not necessarily to very high increasing Benefit, thus the circuit bandwidth of entire RXIO can be improved it is very much, thus support the signal of higher speed transmit (> 1Gbps) with Realize high-gain high bandwidth；

2. introducing new differential-to-single-ended circuit to adapt to low supply voltage working condition (2.5V I O power supply voltage with this And it is less than 1.2V core power voltage)；

3. the push-pull type structure of automatic biasing is introduced in the circuit of the second level, to eliminate the hanging of first order amplifier output Point (that is, input of second level circuit) so that circuit performance be substantially improved, and can make the performance of circuit substantially not with PVT Variation；

4. by introducing second level amplifier, so that the close full width of the input of phase inverter, to make the output eye figure of RXIO It is greatly improved with clock duty cycle.

Although being shown and described to the present invention by referring to some of the preferred embodiment of the invention, It will be understood by those skilled in the art that can to it, various changes can be made in the form and details, without departing from this hair Bright spirit and scope.

Claims

1. a kind of receiver, which is characterized in that including first order amplifier and second level amplifier；

The first order amplifier includes:

Conversion circuit, the conversion circuit receive the differential output signal, the differential output signal are converted to Single-end output Signal, and export the single-end output signal；

The second level amplifier receives the single-end output signal, and gives output after single-end output signal amplification to driving electricity Road；

Wherein, the gain of the first order amplifier is less than the gain of the second level amplifier, the second level amplifier Bandwidth is not less than the bandwidth of the first order amplifier；

The input stage circuit includes the first metal-oxide semiconductor (MOS) MOS transistor, the second to the tenth MOS transistor, first Resistance and second resistance；

The grid of first MOS transistor and the second MOS transistor receives the differential input signal, first MOS transistor It links together and is connect with the first pole of third MOS transistor, the third with the second pole of second MOS transistor The grid of MOS transistor connects the first bias voltage signal, and the second pole of the third MOS transistor is connect with second source；

4th MOS transistor, the 5th MOS transistor, the 6th MOS transistor and the 7th MOS transistor the first pole and the first electricity Source connection, the of the grid of the grid of the 5th MOS transistor and the 4th MOS transistor, the 4th MOS transistor Two poles are connected with the first pole of first MOS transistor, the grid and the 6th MOS crystal of the 7th MOS transistor The grid of pipe, the 6th MOS transistor the second pole connected with the first pole of second MOS transistor；

The grid of 8th MOS transistor and the 9th MOS transistor receives the differential input signal, the 8th MOS transistor It links together with the first pole of the 9th MOS transistor and is connect with the second pole of the tenth MOS transistor, the described tenth The grid of MOS transistor connects the second bias voltage signal, and the first pole of the tenth MOS transistor is connect with first power supply；

The first resistor is equal with the impedance value of the second resistance, and a pole of the first resistor and the 8th MOS are brilliant Second pole of body pipe is connected with the second pole of the 5th MOS transistor, and a pole of the second resistance and the 9th MOS are brilliant Second pole of body pipe is connected with the second pole of the 7th MOS transistor, the first resistor and the second resistance it is another Pole exports the differential output signal；

Wherein, first is NMOS transistor to third MOS transistor, and the first of NMOS transistor extremely drains, NMOS transistor The second extremely source electrode, the 4th to the tenth MOS transistor is PMOS transistor, the extremely source electrode of the first of PMOS transistor, PMOS The second of transistor extremely drains；Or

First to third MOS transistor be PMOS transistor, the extremely source electrode of the first of PMOS transistor, the second of PMOS transistor It extremely drains, the 4th to the tenth MOS transistor is NMOS transistor, and the first of NMOS transistor extremely drains, NMOS transistor The second extremely source electrode.

2. receiver according to claim 1, which is characterized in that the input stage circuit of the first order amplifier is using defeated Enter output device, the conversion circuit of the first order amplifier uses kernel device；

All devices of the second level amplifier use kernel device.

3. receiver according to claim 1, which is characterized in that the conversion circuit includes the 11st to the 16th MOS Transistor；

The grid of 11st MOS transistor and the 12nd MOS transistor receives the differential output signal, the 11st MOS crystal Second pole of pipe, the 12nd MOS transistor, the 13rd MOS transistor and the 14th MOS transistor is connect with second source, institute State the first of the grid of the 13rd MOS transistor and the grid of the 12nd MOS transistor and the 12nd MOS transistor Pole connection, the grid of the 14th MOS transistor and the grid of the 11st MOS transistor and the 11st MOS are brilliant First pole of body pipe connects；

First pole of the 15th MOS transistor and the 16th MOS transistor links together and connects with the first power supply It connects, the grid of the 15th MOS transistor and the second pole, the 13rd MOS transistor of the 15th MOS transistor The first pole connected with the grid of the 16th MOS transistor, the second pole and the described tenth of the 16th MOS transistor First pole of four MOS transistors connects and exports the single-end output signal；

Wherein, the 11st to the 14th MOS transistor is NMOS transistor, and the first of NMOS transistor extremely drains, and NMOS is brilliant The extremely source electrode of the second of body pipe, the 15th MOS transistor and the 16th MOS transistor are PMOS transistor, PMOS The extremely source electrode of the first of transistor, the second of PMOS transistor extremely drain；Or

11st to the 14th MOS transistor be PMOS transistor, the extremely source electrode of the first of PMOS transistor, PMOS transistor Second extremely drains, and the 15th MOS transistor and the 16th MOS transistor are NMOS transistor, NMOS transistor First extremely drain, the extremely source electrode of the second of NMOS transistor.

4. receiver according to claim 1, which is characterized in that the second level amplifier uses the push-pull type of automatic biasing Circuit structure.

5. receiver according to claim 4, which is characterized in that the second level amplifier includes the 17th MOS crystal Pipe, the 18th MOS transistor and 3rd resistor；

One pole of the 3rd resistor is connect simultaneously with the grid of the 17th MOS transistor and the 18th MOS transistor Receive the single-end output signal, the first pole of another pole of the 3rd resistor and the 17th MOS transistor and described Second pole of the 18th MOS transistor connects and outputs signal to the driving circuit, and the 3rd resistor is greater than 100k Ω；

First pole of the 18th MOS transistor is connect with the first power supply, the second pole of the 17th MOS transistor with Second source connection；

Wherein, the 17th MOS transistor is NMOS transistor, and the first of NMOS transistor extremely drains, NMOS transistor The second extremely source electrode, the 18th MOS transistor is PMOS transistor, the extremely source electrode of the first of PMOS transistor, PMOS The second of transistor extremely drains；Or

17th MOS transistor be PMOS transistor, the extremely source electrode of the first of PMOS transistor, the second of PMOS transistor It extremely drains, the 18th MOS transistor is NMOS transistor, and the first of NMOS transistor extremely drains, NMOS transistor The second extremely source electrode.

6. receiver according to any one of claim 1 to 5, which is characterized in that the gain of the first order amplifier Less than 10dB.

7. receiver according to any one of claim 1 to 5, which is characterized in that the differential input signal is low pressure Differential input signal, the input stage circuit are rail-to-rail circuit.

8. receiver according to any one of claim 1 to 5, which is characterized in that the input stage circuit is put for electric current Big circuit, the conversion circuit are voltage amplifier circuit or voltage and current Hybrid amplifier circuit.

9. receiver according to any one of claim 1 to 5, which is characterized in that the driving circuit includes the 20th Four MOS transistors and the 25th MOS transistor；

The grid of 24th MOS transistor and the 25th MOS transistor receives the second level amplifier Output, the first pole of the 24th MOS transistor connect with the second pole of the 25th MOS transistor and exports drive Dynamic signal；

First pole of the 25th MOS transistor is connect with the first power supply, the second pole of the 24th MOS transistor It is connect with second source；

Wherein, the 24th MOS transistor is NMOS transistor, and the first of NMOS transistor extremely drains, NMOS crystal The extremely source electrode of the second of pipe, the 25th MOS transistor be PMOS transistor, the extremely source electrode of the first of PMOS transistor, The second of PMOS transistor extremely drains；Or

24th MOS transistor is PMOS transistor, the extremely source electrode of the first of PMOS transistor, the of PMOS transistor Two extremely drain, and the 25th MOS transistor is NMOS transistor, and the first of NMOS transistor extremely drains, and NMOS is brilliant The extremely source electrode of the second of body pipe.