CN105409003A - Method for improving the electrical conductivity of metal oxide semiconductor layers - Google Patents
Method for improving the electrical conductivity of metal oxide semiconductor layers Download PDFInfo
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- CN105409003A CN105409003A CN201480041709.4A CN201480041709A CN105409003A CN 105409003 A CN105409003 A CN 105409003A CN 201480041709 A CN201480041709 A CN 201480041709A CN 105409003 A CN105409003 A CN 105409003A
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- metal oxide
- oxide semiconductor
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Links
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 138
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 138
- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 238000000034 method Methods 0.000 title claims abstract description 81
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000010409 thin film Substances 0.000 claims abstract description 14
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 239000012212 insulator Substances 0.000 claims description 7
- 238000000059 patterning Methods 0.000 claims description 7
- 238000006722 reduction reaction Methods 0.000 claims description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 claims description 6
- 239000011112 polyethylene naphthalate Substances 0.000 claims description 6
- -1 polyethylene terephthalate Polymers 0.000 claims description 6
- 229920000139 polyethylene terephthalate Polymers 0.000 claims description 6
- 239000005020 polyethylene terephthalate Substances 0.000 claims description 6
- NJWNEWQMQCGRDO-UHFFFAOYSA-N indium zinc Chemical compound [Zn].[In] NJWNEWQMQCGRDO-UHFFFAOYSA-N 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052783 alkali metal Inorganic materials 0.000 claims description 3
- 150000001340 alkali metals Chemical class 0.000 claims description 3
- 229910052784 alkaline earth metal Inorganic materials 0.000 claims description 3
- 150000001342 alkaline earth metals Chemical class 0.000 claims description 3
- 239000006227 byproduct Substances 0.000 claims description 3
- 239000003638 chemical reducing agent Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 239000000376 reactant Substances 0.000 claims 1
- 230000008569 process Effects 0.000 abstract description 10
- 238000000231 atomic layer deposition Methods 0.000 abstract 1
- 239000002243 precursor Substances 0.000 description 14
- 230000008901 benefit Effects 0.000 description 13
- 239000010408 film Substances 0.000 description 12
- 238000000137 annealing Methods 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- KBIWNQVZKHSHTI-UHFFFAOYSA-N 4-n,4-n-dimethylbenzene-1,4-diamine;oxalic acid Chemical compound OC(=O)C(O)=O.CN(C)C1=CC=C(N)C=C1 KBIWNQVZKHSHTI-UHFFFAOYSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Natural products OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 description 2
- 239000004696 Poly ether ether ketone Substances 0.000 description 2
- 239000004695 Polyether sulfone Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910007717 ZnSnO Inorganic materials 0.000 description 2
- 229910052788 barium Inorganic materials 0.000 description 2
- 229910052790 beryllium Inorganic materials 0.000 description 2
- 229910052792 caesium Inorganic materials 0.000 description 2
- 229910052791 calcium Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052730 francium Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052744 lithium Inorganic materials 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229920006393 polyether sulfone Polymers 0.000 description 2
- 229920002530 polyetherether ketone Polymers 0.000 description 2
- 229910052700 potassium Inorganic materials 0.000 description 2
- 229910052701 rubidium Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052708 sodium Inorganic materials 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910052712 strontium Inorganic materials 0.000 description 2
- VOITXYVAKOUIBA-UHFFFAOYSA-N triethylaluminium Chemical compound CC[Al](CC)CC VOITXYVAKOUIBA-UHFFFAOYSA-N 0.000 description 2
- MCULRUJILOGHCJ-UHFFFAOYSA-N triisobutylaluminium Chemical compound CC(C)C[Al](CC(C)C)CC(C)C MCULRUJILOGHCJ-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000005300 metallic glass Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000004549 pulsed laser deposition Methods 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Abstract
The present disclosure provides a method for improving the electrical conductivity of a metal oxide semiconductor layer at predetermined locations. The method comprises: providing on a substrate a metal oxide semiconductor layer; providing by means of Atomic Layer Deposition a metal oxide layer on top of the metal oxide semiconductor layer, wherein the metal oxide layer is in physical contact with the metal oxide semiconductor layer at the predetermined locations. It was surprisingly found that this method results in an increased electrical conductivity of the metal oxide semiconductor layer at the predetermined locations. The method of the present disclosure can advantageously be used in a fabrication process for self-aligned top- gate metal oxide semiconductor thin film transistors, for improving the electrical conductivity in the source and drain regions.
Description
Technical field
The disclosure relates to the method for the conductance for improving metal oxide semiconductor layer partly.
The disclosure also relates to the method for the manufacture of the thin-film transistor based on metal-oxide semiconductor (MOS).
Background technology
Amorphous metal oxide semiconductor thin-film transistor (TFT) (such as such as amorphous oxide gallium indium zinc (a-IGZO) thin-film transistor) is due to its higher mobility and larger area uniformity, and being verified as is potential replacement based on the TFT of silicon in plane display application.
The non-crystalline silicon tft of the conventional switching device be used as in active matrix liquid crystal display has the advantage of large regions uniformity.But, its field-effect mobility (<1cm
2/ V.s) too low so that Organic Light Emitting Diode (OLED) cannot be driven.
On the other hand, high mobility (>50cm
2/ V.s) crystal phosphorus silicon TFT (it is used as the switching device in displayer at present) when the heterogeneity for meeting with its field-effect mobility and threshold voltage during large scale displayer.
Known bottom gate and top grid TFT structure are unsuitable for using in high-clear display due to the high and scalability difference (area occupied (footprint) is large) of its parasitic capacitance.High parasitic capacitance in such TFT structure is relevant with there is overlap between source electrode and grid and/or between drain and gate.This overlap is owing to using the transistor gate length that is greater than channel length to avoid or to limit grid and between source electrode and drain electrode, out-of-alignment negative results causes.
Therefore, developing the method for the manufacture of autoregistration top gate oxide TFT, wherein source electrode and drain electrode and gate alignment, and wherein these TFT have good electrical property and high stability.Reported some autoregistration top gate structures with oxide semiconductor active layer, wherein the conductance of metal-oxide semiconductor (MOS) local in source electrode and drain region increases.
Some methods increasing the conductance of metal oxide semiconductor material for (partly) are proposed.A method comprises is adulterated by the ion implantation of impurity (such as, boron, phosphorus or arsenic).But it may be difficult for carrying out ion implantation on flexible substrate, because need usually to perform annealing steps to realize electrode dopant activation higher than the temperature of 450 DEG C.
Other method comprises the process of execution argon plasma, hydrogen gas plasma process or NH
3plasma treatment.But should observe, be not fine through the source electrode of these plasma treatment and the stability of drain region, and as OLED integration needed for the result of further treatment step, the effect of plasma treatment can disappear.
In US2012/0001167, describing a kind of method for the manufacture of autoregistration metal oxide semiconductor films transistor, which using a kind of replacement method of the conductance for increasing metal oxide semiconductor layer partly.After deposited metal oxide semiconductor layer, gate insulator and gate electrode, be provided by the metal metallic film of such as Ti, Al or In and so on, this metallic film has 10nm or less thickness.Then, such as in oxygen-containing atmosphere, heat treatment is performed with the temperature of 300 DEG C.As this heat treated result, this metallic film is oxidized.In the oxidation reaction of metal film, part oxygen included in the source area of metal oxide semiconductor layer and drain region is migrated to metal film.As a result, the oxygen concentration in source region and drain region reduces, thus causes forming low resistance region on the top of metal oxide semiconductor layer.Preferably, the thickness of metallic film is 10nm or less, and the Heat Treatment of metallic film in oxygen-containing atmosphere can be fully oxidized.In this way, can avoid execution etching step to remove the demand of non-oxidising metal.
The method described in US2012/0001167 needs the temperature of at least 200 DEG C, such as, need the temperature in the magnitude of 300 DEG C.Therefore, this method the flexible substrate being not suitable for some low costs are (such as example, PET (polyethylene terephthalate), PEN (Polyethylene Naphthalate) and PC (Merlon)), and may need to have the plastic foil (such as, PI (polyimides), PES (polyether sulfone) or PEEK (polyether-ether-ketone)) that the price of the thermal stability of increase and/or chemical stability is higher.The method also needs well and accurately controlling to avoid execution etching step to remove the demand of non-oxidising metal the thickness of metal level.
General introduction of the present disclosure
Target of the present disclosure is a kind of method providing conductance for increasing metal oxide semiconductor layer partly, and the conductance wherein increased has good thermal stability, and wherein the method can perform with the temperature lower than 200 DEG C.
Target of the present disclosure is also to provide a kind of for the manufacture of having good source electrode and drain contact, good field-effect mobility (such as, higher than 10cm
2/ Vs), the method for the autoregistration top gate metal oxide semiconductor thin-film transistor of good thermal stability and good bias stability, wherein this transistor can with lower than the temperature manufacture of 200 DEG C.
The disclosure relates to a kind of for improving the method for metal oxide semiconductor layer in the conductance of pre-position.The method comprises: on substrate, provide metal oxide semiconductor layer; And provide metal oxide layer by ald (ALD) at the top of metal oxide semiconductor layer, wherein this metal oxide layer is at precalculated position and metal oxide semiconductor layer physical contact, namely docks with metal oxide semiconductor layer by direct physical interface in precalculated position.
Be surprised to find and deposit such metal oxide layer by ALD and cause metal oxide semiconductor layer to have the conductance of increase in the position that metal oxide layer contacts with metal oxide semiconductor layer direct physical.
In each embodiment of the present disclosure, metal oxide layer such as can have the thickness in the scope between 10nm and 100nm or between 11nm and 99nm, and the disclosure is not limited to this.
In each embodiment of the present disclosure, provide (such as depositing) metal oxide layer can come with the temperature be in the scope between 150 DEG C and 200 DEG C by ald.
In each embodiment of the present disclosure, before the method also can be included in and provide metal oxide layer on the top of metal oxide semiconductor layer: the reducing zone being provided in pre-position and metal oxide semiconductor layer physical contact, this reducing zone comprises alkali metal (such as, any one or its combination in any in Li, Na, K, Rb, Cs or Fr) or alkaline-earth metal (such as, in Be, Mg, Ca, Sr, Ba or a any one or its combination in any); Such as by causing the chemical reduction reaction between reducing zone and metal oxide semiconductor layer with the temperature execution annealing steps in the scope be between 20 DEG C and 200 DEG C; And, such as by rinsing in water or alcohol, reducing zone and byproduct of reaction are removed from reduction reaction.
In each embodiment of the present disclosure, metal oxide semiconductor layer such as can comprise oxidation gallium indium zinc (GIZO or IGZO), and metal oxide layer such as can comprise Al
2o
3.But the disclosure is not limited to this.Other metal-oxide semiconductor (MOS)s can be used, such as such as ZnO, ZnSnO, InO, InZnO, InZnSnO, LaInZnO, GaInO, HfInZnO, MgZnO, LaInZnO, TiO, TiInSnO, ScInZnO, SiInZnO and ZrInZnO or ZrZnSnO.Other metal oxide layers can be used, such as such as HfO
2, Ta
2o
5, ZrO
2or Ga
2o
3.
Be Al at wherein metal oxide layer of the present disclosure
2o
3in each embodiment of layer, this metal oxide layer can deposit as precursor as precursor or with such as triethyl aluminum and water or with triisobutyl aluminium and water with trimethyl aluminium and water (H2O).
In each embodiment of the present disclosure, when forming metal oxide layer, different precursors can be mixed, or alternatively use different precursors.
The disclosure relates to a kind of method of pushing up grid (grid is provided at the top of metal oxide semiconductor layer) metal oxide semiconductor films transistor for the manufacture of autoregistration (mean source electrode and drain and grid autoregistration) further.The method comprises: on substrate, provide metal oxide semiconductor layer; At the deposited atop gate dielectric of this metal oxide semiconductor layer; Gate electrode layer on this gate dielectric; Patterning grid electrode layer and gate insulator, to form gate electrode and gate insulator, limit channel region by this in metal oxide semiconductor layer; Patterning metal oxide semiconductor layer, limits source region and drain region by this in metal oxide semiconductor layer; And, at least deposit metal oxide layers in source electrode and drain region is carried out such as by ald, increase the conductance of metal oxide semiconductor layer in source region and in drain region by this, wherein metal oxide layer contacts with metal oxide semiconductor layer direct physical, namely docks with metal oxide semiconductor layer by direct physical interface.
The method can comprise further: at the deposited atop dielectric layer of metal oxide semiconductor layer; Form the through hole through dielectric layer and metal oxide layer; And, fill this through hole to form source contact and drain contact with metal.
In each embodiment of the present disclosure, the method can be included in before the top of metal oxide semiconductor layer provides metal oxide layer further: the reducing zone being provided in pre-position and metal oxide semiconductor layer physical contact, this reducing zone comprises alkali metal (such as, any one or its combination in any in Li, Na, K, Rb, Cs or Fr) or alkaline-earth metal (such as, in Be, Mg, Ca, Sr, Ba or a any one or its combination in any); Such as by causing the chemical reduction reaction between reducing zone and metal oxide semiconductor layer with the temperature execution annealing steps in the scope be between 20 DEG C and 200 DEG C; And, such as by rinsing in water or alcohol, reducing zone and byproduct of reaction are removed from reduction reaction.
An advantage of each method of the present disclosure is that these methods can with lower than 200 DEG C or lower than 199 DEG C or lower than 190 DEG C or lower than 180 DEG C or lower than 170 DEG C or perform lower than the temperature of 160 DEG C.Therefore, the flexible substrate of these methods and low cost is compatible, and the flexible substrate of low cost is such as such as PET (polyethylene terephthalate), PEN (Polyethylene Naphthalate) and PC (Merlon).
An advantage of each method of the present disclosure is that key-course thickness is exactly existed to less demand or there is not demand, is then this situation in some art methods.
An advantage of each method of the present disclosure is that deposit metal oxide layers not only causes the conductance of the improvement of metal oxide semiconductor layer below, and deposit metal oxide layers also causes the passivation of metal oxide semiconductor layer below and encapsulation (such as in addition, metal oxide semiconductor layer is completely covered or encapsulates, and namely no longer exposes in the environment).
An advantage of each method of the present disclosure is its good stability causing the conductance of the increase of metal oxide semiconductor layer; Namely the conductance increased is maintained in time.
An advantage of each method of the present disclosure is that it allows manufacture to have good bias stability and has the autoregistration top gate metal oxide semiconductor thin-film transistor of good thermal stability.
Some object of each creative aspect and advantage describe more than herein.It should be understood, of course, that not necessarily this type of objects all or advantage all can realize according to any specific embodiment of the present disclosure.Therefore, such as, person of skill in the art will appreciate that the present invention can specialize by the mode realized or optimize an advantage teaching herein or one group of advantage or perform, and not necessarily will realize other objects that this paper may instruct or propose or advantage simultaneously.In addition, should be appreciated that this general introduction to be only an example and be not intended to limit the scope of the present disclosure.About tissue and the disclosure of method of operation, together with its feature and advantage, in conjunction with the drawings and reading can be understood best with reference to following detailed description.
Accompanying drawing is sketched
Fig. 1 (a) to Fig. 1 (f) explains orally the method for the manufacture of metal oxide semiconductor films transistor according to method of the present disclosure.
Fig. 2 illustrates the transfer characteristic (I of the a-IGZO thin-film transistor manufactured according to method of the present disclosure
dS-V
gS).
Fig. 3 illustrates the output characteristic (I of the a-IGZO thin-film transistor manufactured according to method of the present disclosure
dS-V
dS).
Fig. 4 illustrates the transfer characteristic (I of the a-IGZOTFT (W/L=30/10 μm/μm) manufactured according to method of the present disclosure
dS-V
gS), the deviated stress time for different: Fig. 4 (a) is for the back bias voltage stress (V for-1MV/cm
gS=-12V and V
dS=0V) situation; Fig. 4 (b) is for the positive bias stress (V for+1MV/cm
gS=+12V and V
dS=+12V) situation.
Fig. 5 illustrates the V of the a-IGZOTFT manufactured according to method of the present disclosure
tHskew, this V
tHoffset in positive and negative direction both according to stress time.
Fig. 6 illustrates the initial transfer characteristic (open circles) of a-IGZOTFT (W/L=30/10 μm/μm) and the transfer characteristic (closed square) after annealing 2 hours in nitrogen with 150 DEG C.
Any reference marker in claims should not be interpreted as limiting the scope of the present disclosure.
In different figures, same reference numbers indicates same or similar element.
Detailed description of preferred embodiment
In the following detailed description, numerous specific detail is set forth to provide the disclosure and its thorough understanding that can how implement in certain embodiments.But will understand, the disclosure also can be implemented when not having these specific detail.In other situation, well-known method, program and technology are not described in detail in order to avoid obscure the disclosure.
Although also will describe the disclosure with reference to certain figures for particular implementation, the disclosure will be not limited thereto.To comprise and the accompanying drawing described therewith is schematic, do not limit the scope of the present disclosure.It shall yet further be noted that in the accompanying drawings, for purpose of explanation, the size of some elements may be exaggerated, therefore not drawn on scale.
In addition, term first, second, and third grade in specification for distinguishing similar element, and not necessarily for describing the sequencing of time, space, arrangement or any other mode.Should be understood that the term so used is interchangeable in the appropriate case, and embodiment of the present disclosure described herein can be different from other operation in tandem that is described herein or that illustrate.
In addition, the term top in specification, bottom, on, under etc. for descriptive object, and not necessarily for describing relative position.Should be understood that the term so used is interchangeable in the appropriate case, and embodiment of the present disclosure described herein can be different from other orientation that is described herein or that illustrate operation.
Present disclose provides a kind of for improving the method for the conductance of (increase) metal oxide semiconductor layer, such as, for improving the method for such layer in the conductance of the source electrode of metal oxide semiconductor films transistor and the position of drain contact partly.The increase of conductance can be a large amount of, such as, be at least one times of magnitude, such as, up to 3 times of magnitudes.
According to one side of the present disclosure, provide a kind of for increasing the method for metal oxide semiconductor layer in the conductance of pre-position, wherein the method comprises: by the deposited atop metal oxide layer of ald at metal oxide semiconductor layer, and this metal oxide layer, at pre-position and metal oxide semiconductor layer physical contact, docks with metal oxide semiconductor layer in pre-position thus.
Be surprised to find and deposit such metal oxide layer by ALD and cause metal oxide semiconductor layer to be at metal oxide layer and metal oxide semiconductor layer the conductance that there is increase position that direct physical contacts.
Metal oxide layer such as can comprise Al
2o
3, HfO
2, Ta
2o
5, ZrO
2or Ga
2o
3, the disclosure is not limited thereto.
In each embodiment of the present disclosure, metal oxide layer can be such as Al
2o
3layer.It such as can use trimethyl aluminium (TMA, Al (CH
3)
3) and water (H
2o) deposit as precursor.But, other precursors (such as such as triethyl aluminum and water or triisobutyl aluminium and water) can be used to form Al
2o
3layer.
In each embodiment of the present disclosure, metal oxide layer can be such as Ga
2o
3layer.Can be the precursor that this layer use and comprise such as three second first galliums and water, trimethyl gallium and water, triisopropyl gallium and water or tri-tert gallium and water, the disclosure is not limited thereto.
In each embodiment of the present disclosure, when forming metal oxide layer, different precursors can be mixed, or alternatively use different precursors.
Metal oxide layer such as can have the thickness in the scope that is between 10nm and 100nm, and it can such as deposit with the temperature be in the scope of (such as, between 150 DEG C and 170 DEG C) between 150 DEG C and 200 DEG C, and the disclosure is not limited thereto.
Method of the present disclosure can be advantageously utilised in the manufacture process for the thin-film transistor with metal-oxide semiconductor (MOS) active layer, to increase the conductance of the pre-position corresponding with source region and drain region partly, improve the charge injection from source electrode and drain contact by this.The method can be advantageously utilised in the manufacture process for autoregistration top-gate thin-film transistors.
The method also can be used in the manufacture process for the device (such as, diode or transistor-diode) based on other metal-oxide semiconductor (MOS)s, to improve the charge injection from contact.
Metal oxide semiconductor layer such as can comprise oxidation gallium indium zinc (GIZO, be also referred to as IGZO), or based on the semiconductor of other metal oxides, such as following compound (and without the need to indicating stechiometry): ZnO, ZnSnO, InO, InZnO, InZnSnO, LaInZnO, GaInO, HfInZnO, MgZnO, LaInZnO, TiO, TiInSnO, ScInZnO, SiInZnO and ZrInZnO, ZrZnSnO.But the disclosure is not limited to this, and the method can other suitable metal semiconductor compound couplings known with those skilled in the art.Usual thickness these semiconductor layers between 5nm and 50nm or between 6nm and 49nm provide by multiple method, and multiple method is such as such as to the sputter of precursor solution, hot evaporation, pulsed laser deposition and spin-coating, ink jet printing or a plating.
Also describe a kind of method for the manufacture of autoregistration top gate metal oxide semiconductor thin-film transistor, wherein method of the present disclosure is used to improve the conductance of metal oxide semiconductor layer in source electrode and drain region partly.In such device architecture, ALD metal oxide layer change source electrode below and the conductibility of drain region, and it also has the function of passivation and encapsulated layer.
Schematically show in Fig. 1 (a) to Fig. 1 (f) according to the example process flow for the manufacture of metal oxide semiconductor films transistor of the present disclosure.
First step shown in Fig. 1 (a), such as, by providing metal oxide semiconductor layer 12 on the substrate 10, such as GIZO layer with precursor solution sputtering, laser ablation or spin coating.In the example shown in Fig. 1 (a), substrate 10 comprises silicon substrate 101 and dielectric layer 102, such as silicon oxide layer.But, other suitable substrates can be used.The thickness of GIZO layer 12 such as can be in the magnitude of about 10nm or about 15nm to 20nm, such as, be between 10nm and 20nm, or be between 11nm and 19nm, but can use other suitable thickness.
Then, as shown in Fig. 1 (b), gate dielectric 13 (such as such as silicon oxide layer) is such as deposited over the top of metal oxide semiconductor layer 12 by plasma enhanced chemical vapor deposition.After this be the top (Fig. 1 (b)) grid electrode layer 14 (such as such as Mo layer) being deposited on gate dielectric 13.
Grid electrode layer 14 and gate insulator 13 are such as patterned to form gate electrode 141 and gate insulator 131, as shown in Fig. 1 (c) by dry etching subsequently.
Then, metal oxide semiconductor layer 12 is patterned, and limits the active layer 11 (Fig. 1 (d)) of thin-film transistor thus.Metal oxide semiconductor layer such as can pass through wet etching (such as using buffered HF or ethanedioic acid) and carry out patterning.The advantage of ethanedioic acid is used to be that it has good selectivity to each layer below to active layer patterning.Patterned gate electrode 141 limits channel region 110, source region 111 and drain region 112 in active layer 11, as schematically shown in Fig. 1 (d).Source electrode and drain region and channel region direct neighbor, and be self aligned.
In the example depicted in fig. 1, metal oxide semiconductor layer is patterned after carrying out patterning to grid electrode layer and gate dielectric.But the disclosure is not limited to this.Such as, metal oxide semiconductor layer also can be patterned in the later phases before grid manufacture process or after grid manufacture process.
Then, metal oxide layer 15 (such as such as Al
2o
3layer) be by ALD, such as use trimethyl aluminium (TMA, Al (CH
3)
3) and water (H
2o) deposit as precursor (shown in Fig. 1 (e)).Be surprised to find the such layer of deposition and can cause metal oxide semiconductor layer Al wherein
2o
3there is the conductance of increase the position that layer 15 contacts with metal oxide semiconductor layer 11 direct physical.Therefore, in the source region 111 and drain region 112 of metal oxide semiconductor layer 11, at least in the top of metal oxide semiconductor layer, obtain the conductance strengthened.Believe, due to the interaction between ALD precursor and metal oxide semiconductor layer surface, to there is a kind of doping effect or reduction reaction.Such as, as Al
2o
3tMA and H of ALD precursor
2o can react with IGZO surface.Such as, if there is H in the reaction
2o, O
2, O
3, then doping effect occurs.Top preferably have several nm (up to 10 or about 10nm) the degree of depth/thickness.If ALD metal oxide deposition combines (such as with additional doping, use Ca, see more than), then the conductance strengthened is expected in metal oxide semiconductor layer and extends darker, such as up to tens nm, as such as up to 20nm or up to 30nm.
Then, dielectric layer 16 (such as such as silicon nitride layer) is provided at metal oxide layer 15 top, then the position forming source electrode and drain contact is formed through this dielectric layer 16 or below the through hole of metal oxide layer 15.This through hole fills to form source electrode 21 and drain electrode 22 with suitable metal (such as such as Mo) subsequently.The structure obtained is schematically shown in Fig. 1 (f).
Fig. 2 illustrate according to method manufacture of the present disclosure as above, there is ALDAl
2o
3transfer characteristic (the I of the a-IGZO thin-film transistor of metal oxide layer 15
dS-V
gS).Fig. 3 illustrates the output characteristic (I of this transistor
dS-V
dS).
A-IGZOTFT shows high thermal stability and good electrical property.Observe 14.82cm
2the subthreshold swing of the field-effect mobility of/V.s, the threshold voltage of 3.6V, 0.42V/dec and about 10
8conduction and cut-off current ratio.
The impact of deviated stress on the electrical property of TFT is verified.The gate field corresponding to +/-1.0MV/cm in positive and negative direction is applied in room temperature in the dark and most reaches 10
4the stress time of second.(the V when the positive gate bias stress corresponding with full conduction status
dS=12V and V
gS=12V), observe the threshold voltage shift of 0.8V.(the V when back bias voltage stress
dS=0V and V
gS=-12V), observe the threshold voltage shift of 1.0V.Fig. 4 (a) and Fig. 4 (b) illustrate the transfer characteristic of different deviated stress time for the situation of negative gate bias stress (Fig. 4 (a)) and positive gate bias stress (Fig. 4 (b)): 0s (that is, not having deviated stress), 100s, 300s, 1000s, 3000s and 10000s.Fig. 5 illustrates the V according to stress time in both positive and negative directions
tHskew.By these results, draw to draw a conclusion: the stability under stress condition is very good.
Fig. 6 illustrates the initial transfer characteristic (open circles) of a-IGZOTFT (W/L=30/10 μm/μm) and the transfer characteristic (closed square) after annealing 2 hours in nitrogen with 150 DEG C.By these results, can draw to draw a conclusion: the impact of annealing steps on apparatus characteristic is negligible, thus indicates good thermal stability.
More than describe and describe some embodiment of the present disclosure in detail.But should be appreciated that and how detailed seem no matter above in the text, the present invention can otherwise realize.It should be noted that describe some feature of the present invention or in time, the use of particular term should not be used for implying that this term is redefined to be limited to any particular characteristics comprising the feature of the present invention or aspect be associated with described term in this article.
Although this detailed description illustrates, describes and point out the novel features of each aspect of the present invention being applied to each embodiment, be appreciated that those skilled in that art can make various omission to the form of shown equipment or process and details, substitute and change and do not depart from the generic concept of each aspect of the present invention.
Claims (12)
1., for improving the method for metal oxide semiconductor layer in the conductance of pre-position, comprising:
Substrate (10) provides metal oxide semiconductor layer (12);
On the top of described metal oxide semiconductor layer, provide metal oxide layer (15) by ald, wherein said metal oxide layer is at described precalculated position and described metal oxide semiconductor layer physical contact.
2. method according to claim 1, is characterized in that, described metal oxide layer (15) has the thickness in the scope of 10nm and 100nm.
3. the method according to any one in claim 1 or 2, is characterized in that, provides described metal oxide layer (15) to be that the temperature be in the scope between 150 DEG C and 200 DEG C completes.
4. the method according to any one in aforementioned claim, is characterized in that, described metal oxide semiconductor layer (12) is oxidation gallium indium zinc layers.
5. the method according to any one in aforementioned claim, is characterized in that, described metal oxide layer (15) is Al
2o
3layer.
6. method according to claim 5, is characterized in that, described Al
2o
3layer is with trimethyl aluminium and water (H
2o) deposit as reactant.
7. the method according to any one in aforementioned claim, is characterized in that, is also included in before the top of described metal oxide semiconductor layer provides described metal oxide layer:
Be provided in the reducing zone of described pre-position and described metal oxide semiconductor layer physical contact, described reducing zone comprises alkali metal or alkaline-earth metal;
Cause the chemical reduction reaction between described reducing zone and described metal oxide semiconductor layer; And
Described reducing zone and byproduct of reaction are removed from described reduction reaction.
8. for the manufacture of a method for autoregistration top gate metal oxide semiconductor thin-film transistor, make use of the method according to any one in claim 1 to 7, described method comprises:
Substrate (10) provides metal oxide semiconductor layer (12);
At the deposited atop gate dielectric (13) of described metal oxide semiconductor layer (12);
At the upper gate electrode layer (14) of described gate dielectric (13);
Grid electrode layer described in patterning (14) and described gate insulator (13) are to form gate electrode (141) and gate insulator (131);
Metal oxide semiconductor layer described in patterning (12), limits the source region (111) of described thin-film transistor, channel region (110) and drain region (112) thus; And
Carry out deposit metal oxide layers (15) by ald, increase the conductance of described metal oxide semiconductor layer wherein in the described source region (111) that contacts with described metal oxide semiconductor layer direct physical of described metal oxide layer and described drain region (112) thus.
9. method according to claim 8, is characterized in that, comprises further:
Dielectric layer (16) is provided at the top of described metal oxide layer (15);
Form the through hole through described dielectric layer (16) and described metal oxide layer (15); And
With metal filled described through hole to form source electrode (21) and drain electrode (22).
10. the method described in any one according to Claim 8 or in claim 9, is characterized in that, described method performs with the temperature lower than 200 DEG C.
11. methods as described in any one in claim 8 to 10, it is characterized in that, described substrate is the flexible substrate of low cost.
12. according to Claim 8 to the method described in any one in 11, and it is characterized in that, described substrate comprises PET (polyethylene terephthalate), PEN (Polyethylene Naphthalate) or PC (Merlon).
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|---|---|---|---|
| EP13177735.1 | 2013-07-24 | ||
| EP13177735 | 2013-07-24 | ||
| PCT/EP2014/062120 WO2015010825A1 (en) | 2013-07-24 | 2014-06-11 | Method for improving the electrical conductivity of metal oxide semiconductor layers |
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| EP3136446A1 (en) | 2015-08-28 | 2017-03-01 | Nederlandse Organisatie voor toegepast- natuurwetenschappelijk onderzoek TNO | Tft device and manufacturing method |
| US20200035717A1 (en) * | 2018-07-26 | 2020-01-30 | Sharp Kabushiki Kaisha | Thin film transistor substrate and method of producing thin film transistor substrate |
| JP2021128978A (en) * | 2020-02-12 | 2021-09-02 | 株式会社ジャパンディスプレイ | Semiconductor device and manufacturing method for the same |
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| US20090230389A1 (en) * | 2008-03-17 | 2009-09-17 | Zhizhang Chen | Atomic Layer Deposition of Gate Dielectric Layer with High Dielectric Constant for Thin Film Transisitor |
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| TWI660432B (en) | 2019-05-21 |
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