CN105405386B - Display device and grid driving circuit on array - Google Patents
Display device and grid driving circuit on array Download PDFInfo
- Publication number
- CN105405386B CN105405386B CN201610003272.6A CN201610003272A CN105405386B CN 105405386 B CN105405386 B CN 105405386B CN 201610003272 A CN201610003272 A CN 201610003272A CN 105405386 B CN105405386 B CN 105405386B
- Authority
- CN
- China
- Prior art keywords
- signal
- output end
- circuit
- coupled
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000000087 stabilizing effect Effects 0.000 claims abstract description 10
- 230000033228 biological regulation Effects 0.000 claims description 18
- 239000003990 capacitor Substances 0.000 claims description 13
- 230000008439 repair process Effects 0.000 claims description 6
- 239000000725 suspension Substances 0.000 claims description 6
- 230000002159 abnormal effect Effects 0.000 claims description 3
- 238000003698 laser cutting Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 10
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 238000007667 floating Methods 0.000 description 5
- 238000003491 array Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000007323 disproportionation reaction Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002045 lasting effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000010408 sweeping Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
A grid driving circuit on an array comprises a driving circuit, a control circuit and a voltage stabilizing circuit. The driving circuit is used for generating the scanning signal of the current stage. The control circuit comprises an output end, a pull-up unit and a pull-down unit. The pull-up unit is used for providing a pull-up control signal to the output end according to the front X-level scanning signal, the pull-down unit is used for providing a pull-down control signal to the output end according to the rear Y-level scanning signal, the output end is used for outputting the control signal according to the pull-up control signal or the pull-down control signal, and X and Y are positive integers. The voltage stabilizing circuit is coupled between the driving circuit and the output end and is used for stabilizing the scanning signal according to the control signal.
Description
Technical field
The invention relates to a kind of device and driving circuits, and in particular to grid on a kind of display equipment and array
Pole driving circuit.
Background technique
Answer consumer for the demand of electronic product, slimming has become the trend of Current electronic product, and display panel produces
Industry also follows current trend, develops gate driving circuit on array (Gate driver on Array, GOA) so that panel is more
Add slimming.So-called GOA is that gate driving circuit is configured in array substrate, to take the driving replaced and made by external silicon chip
Chip.Since GOA technology can be configured directly around panel, thus simplify production process, improves the degree of integration of display panel, make
Panel is obtained more to be thinned.
With the progress of science and technology, display panel industry more develops double drive GOA circuits, this technology is by two groups of GOA circuits
It is respectively arranged at the two sides of panel.If occurring between the drive signal line and output node of the GOA circuit of display panel either side short
Road, and lead to operation exception, then the signal wire that the GOA circuit of short circuit can will occur is truncated to repair this display panel.However, because
The GOA circuit of repairing side generates suspension joint node and causes its voltage regulator circuit abnormal formation leakage path, so that gate line voltage
Level decline, therefore through patched display panel, remain brightness disproportionation, the even situation of GOA circuit operation exception.
It can be seen that above-mentioned existing mode, it is clear that there are still inconvenient and defects, and have much room for improvement.It is above-mentioned in order to solve
Problem, related fields there's no one who doesn't or isn't painstakingly seeks solution, but does not develop solution appropriate yet for a long time.
Summary of the invention
Summary of the invention be intended to provide this disclosure simplify abstract so that reader have to this disclosure it is basic
Understand.The invention content is not the complete overview of this disclosure, and its be not intended to point out the embodiment of the present invention it is important/
Key component defines the scope of the present invention.
One of the content of present invention purpose is the gate driving circuit on providing a kind of array, and using improves asking for prior art
Topic.
In order to achieve the above object, the first technology aspect of the content of present invention be about gate driving circuit on a kind of array,
Include driving circuit, control circuit and voltage regulator circuit.Driving circuit is to generate the same level scanning signal.Control circuit includes output
End, pull-up unit and drop-down unit.Pull-up unit is to provide pull-up control signal to output according to preceding X grades of scanning signal
End, and drop-down unit, to provide drop-down control signal to output end according to rear class scanning signal, output end is to according to pull-up
Control signal or drop-down control signal and export control signal, and wherein X, Y are positive integer.Voltage regulator circuit be coupled to driving circuit with
Between output end, to carry out pressure stabilizing to scanning signal according to control signal.
In another embodiment, pull-up unit includes first end, control terminal and second end.First end is to X grades before receiving
Scanning signal.Control terminal is coupled to first end.Second end is coupled to output end.
In one embodiment, drop-down unit includes first end, control terminal and second end.First end is coupled to output end.Control
End processed is to Y grades of scanning signals after receiving.Second end is to be coupled to ground terminal.
In another embodiment, gate driving circuit further includes capacitor on array.Capacitor is coupled to output end, and to root
The voltage quasi position of output end is pulled up according to the first scanning signal, so that output end exports the second high levels and controls signal.
In another embodiment, pull-up control signal is that the first high levels control signal, and the second high levels control signal
Voltage level is higher than the voltage level of the first high levels control signal.
In another embodiment, generated after X grades of scanning signals before the first scanning signal is lain in.
In one embodiment, rear Y grades of scanning signal is generated after the first scanning signal.
In another embodiment, control circuit further includes voltage regulation unit, this voltage regulation unit couples output end, and to basis
Driving signal provided by voltage regulator circuit is with the control signal to output end output low level.
In another embodiment, driving signal includes the first driving signal and the second driving signal.Voltage regulation unit includes the
One switch and second switch, first switch and second switch respectively to according to the first driving signal and the second driving signal with will
Output end ground connection, wherein the first driving signal and the second driving signal have opposite phase.
In one embodiment, first switch includes that first end is coupled to output end, control terminal to receive the first driving letter
Number and second end be coupled to ground terminal, and second switch includes that first end is coupled to the output end, control terminal to receive the
Two driving signal and second end are coupled to ground terminal.
In order to achieve the above object, the second technology aspect of the content of present invention is about a kind of display equipment, it includes at least one
Scan line, the first driver and the second driver.First driver is located at one end of scan line, and the second driver is located at scanning
The other end of line.One of first driver and the second driver include gate driving on array described in the first technology aspect
Circuit.
In another embodiment, the pull-up unit of gate driving circuit includes first end, control terminal and second end on array.
First end is to X grades of scanning signals before receiving.Control terminal is coupled to first end.Second end is coupled to output end.
In one embodiment, the drop-down unit of gate driving circuit includes first end, control terminal and second end on array.The
One end is coupled to output end.Control terminal is to Y grades of scanning signals after receiving.Second end is to be coupled to ground terminal.
In another embodiment, gate driving circuit further includes capacitor on array.Capacitor is coupled to output end, and to root
The voltage quasi position of output end is pulled up according to the first scanning signal, so that output end, which exports the second high levels, controls signal.
In another embodiment, pull-up control signal is that the first high levels control signal, and the second high levels control signal
Voltage level is higher than the voltage level of the first high levels control signal.
In another embodiment, the first scanning signal is generated after preceding X grades of scanning signal.
In one embodiment, rear Y grades of scanning signal is generated after the first scanning signal.
In another embodiment, the control circuit of gate driving circuit further includes voltage regulation unit on array, this voltage regulation unit
Output end is coupled, and to the driving signal according to provided by voltage regulator circuit with the control signal to output end output low level.
In another embodiment, driving signal includes the first driving signal and the second driving signal.Voltage regulation unit includes the
One switch and second switch, first switch and second switch respectively to according to the first driving signal and the second driving signal with will
Output end ground connection, wherein the first driving signal and the second driving signal have opposite phase.
In one embodiment, the first switch of voltage regulation unit includes that first end is coupled to output end, control terminal to receive
First driving signal and second end are coupled to ground terminal, and second switch includes that first end is coupled to the output end, control terminal
Ground terminal is coupled to receive the second driving signal and second end.
Therefore, technology contents according to the present invention, the embodiment of the present invention is by providing grid on a kind of display equipment and array
The problem of pole driving circuit, using improves through patched display panel, remains brightness disproportionation, even GOA operation exception.
After refering to following description, persond having ordinary knowledge in the technical field of the present invention, which works as, can will readily appreciate that this
The essence spirit of invention and other goals of the invention and the technology used in the present invention means and state sample implementation.
Detailed description of the invention
For above and other purpose, feature, advantage and embodiment of the invention can be clearer and more comprehensible, institute's accompanying drawings are said
It is bright as follows:
Fig. 1 is the schematic diagram that gate driving circuit on a kind of array is painted according to one embodiment of the invention；
Fig. 2 is a kind of schematic diagram for the connection relationship being painted between circuit at different levels according to another embodiment of the present invention；
Fig. 3 is to be painted a kind of waveform diagram according to yet another embodiment of the invention；
Fig. 4 is the schematic diagram that gate driving circuit on a kind of array is painted according to further embodiment of this invention；
Fig. 5 is to be painted a kind of waveform diagram according to another embodiment of the present invention；
Fig. 6 is that a kind of schematic diagram for showing equipment is painted according to one embodiment of the invention.
Appended drawing reference are as follows:
100,100A: gate driving circuit G (n-X) on array: prime scanning signal
110: driving circuit G (n+Y): rear class scanning signal
112,114,116: pull-up unit G (n-R), G (n+S): scanning signal
118: drop-down unit LC1, LC2: signal source
120,120A: control circuit HC (n): driving signal
122: voltage regulation unit M: control signal
130: voltage regulator circuit N1, N2: node
600: display equipment P (n), K (n): driving signal
610: the first driver Out: output end
620: the second driver P1~P3: period
630: pixel region ST (n-R): initial signal
C: capacitor T32~T33, T42~T43, T51~T54,
G1~Gn: scan line T61~T64, T71~T74: switch
G (n): scanning signal Vss: ground terminal
G (z): scanning signal
According to usual operation mode, various features are not drawn to scale with element in figure, drafting mode be in order to
Specific features and element related to the present invention are presented in optimal manner.In addition, between different schemas, with the same or similar
Component symbol censures similar elements/components.
Specific embodiment
In order to keep the narration of this disclosure more detailed with it is complete, below for state sample implementation of the invention and specific
Embodiment proposes illustrative description；But this not implements or uses the unique forms of the specific embodiment of the invention.Embodiment party
The feature of multiple specific embodiments is covered in formula and to construction and the method and step for operating these specific embodiments and its
Sequentially.However, can also reach identical or impartial function and sequence of steps using other specific embodiments.
Unless this specification is defined otherwise, technology belonging to the meaning and the present invention of science and technology vocabulary used herein is led
Tool usually intellectual understands identical as usual meaning in domain.In addition, in the case of getting along well context conflict, this explanation
Singular noun used in book covers the complex number type of the noun；And also cover the singular type of the noun when used plural noun.
In addition, about coupling used herein ", can refer to two or multiple components mutually directly make entity or be electrically connected with
Touching, or mutually put into effect indirectly body or in electrical contact is also referred to as two or multiple component mutual operations or movement.
When display panel is using double frameworks for driving gate driving circuit (Gate driver on Array, GOA) on arrays,
That is, it is respectively arranged with GOA driving circuit in the opposite end of scan line, if the drive signal line of the GOA circuit of either side and defeated
Short circuit occurs between egress, then may cause the driving signal of GOA circuit output multi-pulse (multi pulse) and cause to grasp
Make exception, therefore be truncated by the signal wire that the GOA circuit of short circuit will occur for the mode of laser cutting to repair this display panel,
The driving signal of GOA circuit output multi-pulse is avoided, GOA circuit framework provided by the present invention can remain to after repairing
Normal operation, the side not being cut by laser still can normally export scanning signal, and not will receive laser preparing side GOA
The influence of suspension joint node produced by circuit maintains the operation of GOA circuit framework normal, more can further promote the pressure stabilizing of GOA circuit
Ability.
Referring to Fig. 1, it is the schematic diagram for being painted a kind of n-th grade of GOA circuit according to one embodiment of the invention, if through laser
After the signal wire HC (n) for cutting GOA circuit, suspension joint (floating) can be presented in the node Q for repairing the GOA voltage regulator circuit 130 of side
State.However, even if in this situation, when normal side GOA circuit (not shown) exports scanning signal, the present embodiment is repaired
Mending side GOA circuit will not make its voltage regulator circuit 130 open because of above-mentioned floating, cause scan line through voltage regulator circuit 130
Leakage path is produced, and then drags down normal side and repairs the level for the scanning signal G (n) that GOA circuit in side is exported.To improve
The problem of scanning signal G (n) level that GOA circuit after conventional repair is exported reduces, the present invention proposes a kind of GOA of improvement
Circuit does not increase and improves traditional pressure stabilizing mechanism in additional signal lines and the not increased situation of total number of transistors, improves in detail
Means explanation is as after.
As shown in Figure 1, n-th grade of GOA circuit 100 of the present embodiment includes driving circuit 110, control circuit 120 and pressure stabilizing
Circuit 130.In in operation, driving circuit 110 is to generate scanning signal G (n), with driving panel (not shown).To avoid
After being cut by laser the signal wire HC (n) of GOA circuit, the node Q of the driving circuit 110 of the GOA circuit of conventional repair side can be in
Existing floating simultaneously causes voltage regulator circuit 130 abnormal, and the embodiment of the present invention is configuration control circuit 120 in GOA circuit, and steady
Volt circuit 130 is coupled between driving circuit 110 and the control node Out of control circuit 120, and control circuit 120 is to basis
Preceding X grades of scanning signal G (n-X) and/or rear Y grades of scanning signal G (n+Y) are to export control signal M to voltage regulator circuit 130, to keep away
Exempt from the missing caused by node Q of the voltage regulator circuit 130 of traditional GOA circuit because connecting floating.Furthermore voltage regulator circuit 130
It can be used to carry out pressure stabilizing to scanning signal G (n).
Referring to Fig. 1, the 120 received preceding X grades of scanning signal G (n-X) of institute of control circuit and rear Y grades of scanning signal G (n+
It Y), is provided by the preceding X grades of GOA circuits and rear Y grades of GOA circuit of GOA circuit 100, GOA circuit 100 and above-mentioned forward and backward grade electricity
The overall architecture on road referring to Fig. 2, here, in the past, between late-class circuit and GOA circuit 100, it is each differ level Four for.Such as Fig. 2
Shown, GOA circuit 100 belongs to n-th grade of circuit, can be used to receive and sweep for 4 grades before preceding 4 grades (n-4) grade circuit provides
Signal G (n-4) is retouched, rear 4 grades of scanning signal G (n+4) provided by 4 grades (n+4) grade circuit after also can be used to receive.This
Outside, n-th grade of circuit also can provide scanning signal G (n) to preceding 4 grades of (n-4) grade circuits and rear 4 grades (n+4) grade circuit.
To make the operation of GOA circuit 100 shown in FIG. 1 it can be readily appreciated that referring to Fig. 3, it is according to the embodiment of the present invention
It is painted a kind of waveform diagram.As shown in Figure 1, control circuit 120 includes pull-up unit T71 and drop-down unit T74, and have defeated
Outlet Out.In in operation, also referring to Fig. 1 and Fig. 3, in period P1, preceding X grades of scanning signal G (n-X) is high-order calibration signal,
Then Y grades of scanning signal G (n+Y) are low level calibration signal, at this point, the pull-up unit T71 of control circuit 120 is to according to high levels
Preceding X grades of scanning signal G (n-X) output high levels control signal M to output end Out, to pull up output end Out.Pressure stabilizing
Switch T52, T54 of circuit 130 are opened according to the control signal M of high levels, to pull-down node N1.At this point, node N1 is defeated
The driving signal P (n) of low level out, switch T32, T42 of voltage regulator circuit 130 are closed according to the driving signal P (n) of low level
It closes.
In period P2, preceding X grades of scanning signal G (n-X) is converted to low level calibration signal, then Y grades of scanning signal G (n+Y) dimensions
Low level calibration signal is held, at this point, output end Out still persistently maintains the state of high levels.Switch T52, T54 root of voltage regulator circuit 130
The lasting unlatching according to the control signal M of high levels, with pull-down node N1, at this point, the driving signal P of node N1 output low level
(n), switch T32, T42 of voltage regulator circuit 130 are closed according to the driving signal P (n) of low level, the switch for avoiding circuit from penetrating
T32, T42 generate leakage path, to maintain the high levle of scanning signal G (n).
In period P3, preceding X grades of scanning signal G (n-X) maintains low level calibration signal, then Y grades of scanning signal G (n+Y) conversions
For high-order calibration signal, drop-down unit T74 to according to Y grades of scanning signal G (n+Y) after high levels to pull down output end Out, because
This, output end Out exports the control signal M of low level.Switch T52, T54 of voltage regulator circuit 130 believe according to the control of low level
Number M and close.At this point, node N1 can further accordance with high levels signal LC1 and be pulled to the states of high levels, node N1 output
The driving signal P (n) of high levels, switch T32, T42 of voltage regulator circuit 130 are opened according to the driving signal P (n) of high levels.
It should be noted that the mode of operation of another structure of voltage regulation (including switch T33, T43 and T61~T64) shown in FIG. 1 is similar to upper
Structure of voltage regulation (comprising switch T32, T42 and T51~T54) is stated, to keep invention description succinct, is not repeated in this.
In summary, referring to Fig. 1, the switch T71 and T74 of the control circuit 120 of GOA circuit 100 can be swept according to first X grades
Signal G (n-X) and rear two groups of signals of Y grades of scanning signal G (n+Y) are retouched to generate control signal, to control in voltage regulator circuit 130
Controlling circuit of voltage regulation (as switch T51~T54 and T61~T64), and then ensure the control node Q of suspension joint after laser cutting not
It will affect the output waveform of normal side GOA circuit (not shown) generation.In another embodiment, shown in GOA circuit 100
Parameter n, R, S, X, Y all can be positive integer, and wherein R, S, X, Y are, for example, 4, but are not limited.Furthermore the signal for controlling signal M is wide
Degree can be adjusted with the difference of scanning signal.
It please connect refering to fig. 1, specifically, the pull-up unit T71 of control circuit 120 includes first end, control terminal and the
Two ends, to X grades of scanning signal G (n-X) before receiving, the control terminal of pull-up unit T71 is coupled to the first end of pull-up unit T71
First end, and the second end of pull-up unit T71 is then coupled to output end Out.Furthermore the drop-down unit T74 of control circuit 120 is also
Include first end, control terminal and second end.The first end of drop-down unit T74 is coupled to output end Out, the control of drop-down unit T74
End processed is to Y grades of scanning signal G (n+Y) after receiving, and the second end of drop-down unit T74 is then to be coupled to ground terminal Vss.?
In one embodiment, driving circuit 110 includes pull-up unit 112,114,116 and drop-down unit 118, pull-up unit 112,114,
116 can distinguish basis signal scanning signal G (n-R), initial signal ST (n-R), frequency signal HC (n) to pull up scanning signal G
(n), drop-down unit 118 is according to scanning signal G (n+s) to pull down scanning signal G (n).
Fig. 4 is the schematic diagram that gate driving circuit on a kind of array is painted according to further embodiment of this invention.Compared to Fig. 1
GOA circuit 100, GOA circuit 100A in this further includes capacitor C, this capacitor C is coupled to output end Out, and to according to sweeping
It retouches signal G (n) and pulls up the voltage quasi position of output end Out, so that output end Out output has the control signal M of more high levels.
To make the operation of GOA circuit 100A shown in Fig. 4 it can be readily appreciated that referring to Fig. 5, it is according to another reality of the present invention
It applies example and is painted a kind of waveform diagram.In period P1, control circuit 120 according to X grades of scanning signal G (n-X) before high levels with
Export the control signal M of the first high levels L1.In period P2, capacitor C is to the scanning signal G (z) according to high levels and again
Output end Out is pulled up, so that output end Out exports the control signal M of the second high levels L2.As shown, above-mentioned second is high-order
The level of control signal M of the level of the control signal M of quasi- L2 higher than the first high levels L1.
In summary, referring to Fig. 4, can be according to preceding X in addition to the switch T71 and T74 of the control circuit 120 of GOA circuit 100
Grade scanning signal G (n-X) and afterwards two groups of signals of Y grades of scanning signal G (n+Y) control signal M to generate, to control voltage regulator circuit
Controlling circuit of voltage regulation (such as switch T51~T54 and T61~T64) in 130 separately configures a capacitor C and is connected to output end Out outside
And between G (z), wherein G (z) represents timing between preceding X grades of scanning signal G (n-X) and rear Y grades of scanning signal G (n+Y)
Any grid impulse (Gate Pulse), that is, Z is the positive integer between n-X and n+Y.Additionally configure above-mentioned capacitor C's
Purpose is the voltage in order to improve output end Out by coupling, improves the gate terminal voltage of switch T52, T54, T62, T64
To improve its pull-down capability.In this way, which setting for its thin film transistor (TFT) (Thin-Film Transistor, TFT) can be reduced
Count size.
It in another embodiment, please continue to refer to Fig. 4, the scanning signal G (z) of high levels is swept in preceding X grades of high levels
Retouch and generate after signal G (n-X), and rear Y grades of scanning signal G (n+Y) of high levels be in the scanning signal G (z) of high levels it
After generate.In other words, scanning signal G (z) can be in preceding X grades of scanning signal G (n-X) to rear Y grades of scanning signal G (n+Y) section
Scanning signal, such as the same level scanning signal G (n).
In another embodiment, control circuit 120A further includes voltage regulation unit 122, and voltage regulation unit 122 couples output end
Out can be used to an at least driving signal according to provided by voltage regulator circuit 130 (such as: driving signal K (n), P (n)) to defeated
The control signal M of outlet Out output low level.In the present embodiment, voltage regulation unit includes switch T72, T73, above-mentioned switch
T72, T73 according to driving signal K (n) and driving signal P (n) respectively output end Out to be grounded, thus to be able to export
The control signal M stabilization that end Out is exported is maintained at low level.
For make voltage regulation unit 122 shown in Fig. 4 operation it can be readily appreciated that referring to Fig. 5, before or during period P1 P2
Later, the control signal M that output end Out is exported is low level calibration signal, switch T52, T54 or switch of voltage regulator circuit 130
T62, T64 are closed according to the control signal M of low level.At this point, node N1 or N2 are defeated according to signal source LC1 or LC2 respectively
The driving signal P (n) or K (n) of high levels out, switch T72 or T73 can be held according to the driving signal P (n) or K (n) of high levels
It opens so that output end Out to be grounded, maintains control signal M in low level to stablize.In this way, no matter in any stage, it is defeated
Outlet Out can be controlled the control of the element inside circuit 120A, therefore be able to ensure that output end Out does not have suspension joint shape
Condition occurs.
In one embodiment, driving signal P (n), K (n) are respectively by the control of signal source LC1, LC2, and signal source
The opposite in phase of signal provided by LC1, LC2.Referring to Fig. 5, before or during period P1 after P2, voltage regulator circuit 130
Switch T52, T54 or switch T62, T64 closed according to the control signal M of low level, at this point, node N1 is according to signal source
High-order calibration signal that LC1 is provided and export the driving signal P (n) of high levels.Meanwhile signal source LC2 offer is anti-with signal source LC1
To low level calibration signal, low level calibration signal that node N2 is provided according to signal source LC2 and the driving signal K (n) for exporting low level.
Therefore, before or during period P1 after P2, driving signal P (n) and driving signal K (n) have opposite phase.
In another embodiment, referring to Fig. 4, switch T72 includes first end, control terminal and second end, first end coupling
It is connected to output end Out, control terminal is coupled to ground terminal Vss to receive driving signal K (n), second end.In addition, switch T73 packet
Containing first end, control terminal and second end, first end is coupled to output end Out, and control terminal is to receive driving signal P (n), and
Two ends are coupled to ground terminal Vss.
Fig. 6 is that a kind of schematic diagram for showing equipment is painted according to one embodiment of the invention.As shown, display equipment 600
Include at least scan line (one of such as scan line G1~Gn), the first driver 610, the second driver 620 and pixel region
630.In in configuration, the first driver 610 is located at one end of scan line (such as scan line G1), and the second driver 620 is located at and sweeps
Retouch the other end of line (such as scan line G1).One of above-mentioned first driver 610 and the second driver 620 are comprising shown in Fig. 1
GOA circuit 100 or GOA circuit 100A shown in Fig. 4.It follows that Fig. 1 and GOA circuit 100 shown in Fig. 4,100A can be answered
On double drive arrays in the framework of gate driving circuit.It should be noted that Fig. 1 and GOA circuit 100 shown in Fig. 4,100A
Basic framework in being described above, does not repeat in this.
By aforementioned present invention embodiment it is found that the application present invention has following advantages.The embodiment of the present invention is by offer
A kind of display equipment and GOA circuit, the voltage regulator circuit of this GOA circuit are coupled to the control node of control circuit, and control circuit is used
To export control signal according to scanning signals at different levels to voltage regulator circuit, it is in avoid the voltage regulator circuit coupling of traditional GOA circuit
Missing caused by the node Q of existing floating.In addition, the control circuit of GOA circuit additionally configures capacitor, with high by coupling
The scanning signal of level improves the voltage of the output end of control circuit, improves the gate terminal voltage of transistor to improve under it
Drawing ability.In this way, which the design size of its TFT can be reduced.
Although disclosing multiple specific embodiments of the invention in embodiment above, so it is not limited to this hair
It is bright, persond having ordinary knowledge in the technical field of the present invention, in the case of not departing from the principle of the present invention and spirit, when can
Various changes and modification are carried out to it, therefore protection scope of the present invention is worked as to attach claims institute defender and be
It is quasi-.
Claims (20)
1. gate driving circuit on a kind of array, characterized by comprising:
One drive circuit, to generate the same level scanning signal；
One control circuit includes an output end, a pull-up unit and a drop-down unit, and wherein the pull-up unit is to according to one
Preceding X grades of scanning signal provides a pull-up control signal to the output end, and the drop-down unit is to according to Y grades of scanning signals after one
A drop-down control signal is provided to the output end, the output end controlling signal or drop-down control signal according to the pull-up and
One control signal of output, wherein X, Y are positive integer；And
One voltage regulator circuit is coupled between the driving circuit and the output end, to be scanned according to the control signal to the same level
Signal carries out pressure stabilizing；And the control circuit exports the control signal to the voltage regulator circuit, to avoid laser cutting double drive array
After the signal wire of upper gate driving circuit, repairs gate driving circuit generation suspension joint node on the array of survey and cause its voltage regulator circuit
Abnormal formation leakage path.
2. gate driving circuit on array as described in claim 1, which is characterized in that the pull-up unit includes:
One first end, to receive the preceding X grades of scanning signal；
One control terminal is coupled to the first end；And
One second end is coupled to the output end.
3. gate driving circuit on array as described in claim 1, which is characterized in that the drop-down unit includes:
One first end is coupled to the output end；
One control terminal, to receive the rear Y grades of scanning signal；And
One second end, to be coupled to a ground terminal.
4. gate driving circuit on array as claimed in claim 1,2 or 3, which is characterized in that further include:
One capacitor is coupled to the output end, and the voltage quasi position to pull up the output end according to one first scanning signal, with
The output end is set to export one second high levels control signal.
5. gate driving circuit on array as claimed in claim 4, which is characterized in that it is one first high that the pull-up, which controls signal,
Level controls signal, and the voltage level which controls signal is higher than the voltage position of first high levels control signal
It is quasi-.
6. gate driving circuit on array as claimed in claim 4, which is characterized in that first scanning signal is in the preceding X
It is generated after grade scanning signal.
7. gate driving circuit on array as claimed in claim 6, which is characterized in that the rear Y grades of scanning signal be in this
It is generated after scan signal.
8. gate driving circuit on array as claimed in claim 4, which is characterized in that the control circuit further includes:
One voltage regulation unit couples the output end, to an at least driving signal according to provided by the voltage regulator circuit by the output
End ground connection is with the control signal to the output end one low level of output.
9. gate driving circuit on array as claimed in claim 8, which is characterized in that the driving signal includes one first driving
Signal and one second driving signal, which includes:
One first switch and a second switch, respectively to according to first driving signal and second driving signal with this is defeated
Outlet ground connection, wherein first driving signal and second driving signal have opposite phase.
10. gate driving circuit on array as claimed in claim 9, which is characterized in that the first switch includes a first end
It is coupled to the output end, a control terminal and is coupled to a ground terminal to receive first driving signal and a second end, and should
Second switch includes that a first end is coupled to the output end, a control terminal to receive second driving signal and a second end
It is coupled to a ground terminal.
11. a kind of display equipment, characterized by comprising:
At least scan line；
One first driver, positioned at one end of the scan line；And
One second driver, positioned at the other end of the scan line,
Wherein one of first driver and second driver include gate driving on array as described in claim 1
Circuit.
12. display equipment as claimed in claim 11, which is characterized in that pull-up unit of gate driving circuit on the array
Include:
One first end, to receive the preceding X grades of scanning signal；
One control terminal is coupled to the first end；And
One second end is coupled to the output end.
13. display equipment as claimed in claim 11, which is characterized in that drop-down unit of gate driving circuit on the array
Include:
One first end is coupled to the output end；
One control terminal, to receive the rear Y grades of scanning signal；And
One second end, to be coupled to a ground terminal.
14. the display equipment as described in claim 11,12 or 13, which is characterized in that gate driving circuit more wraps on the array
Contain:
One capacitor is coupled to the output end, and the voltage quasi position to pull up the output end according to one first scanning signal, with
The output end is set to export one second high levels control signal.
15. display equipment as claimed in claim 14, which is characterized in that the pull-up controls signal as the control of one first high levels
Signal, the voltage level which controls signal are higher than the voltage level of first high levels control signal.
16. display equipment as claimed in claim 14, which is characterized in that first scanning signal is believed in the preceding X grades of scanning
It is generated after number.
17. display equipment as claimed in claim 16, which is characterized in that the rear Y grades of scanning signal lies in the first scanning letter
It is generated after number.
18. display equipment as claimed in claim 14, which is characterized in that control circuit of gate driving circuit on the array
It further includes:
One voltage regulation unit couples the output end, to an at least driving signal according to provided by the voltage regulator circuit by the output
End ground connection is with the control signal to the output end one low level of output.
19. display equipment as claimed in claim 18, which is characterized in that the driving signal includes one first driving signal and one
Second driving signal, which includes:
One first switch and a second switch, respectively to according to first driving signal and second driving signal with this is defeated
Outlet ground connection, wherein first driving signal and second driving signal have opposite phase.
20. display equipment as claimed in claim 19, which is characterized in that the first switch includes that be coupled to this defeated for a first end
Outlet, a control terminal are coupled to a ground terminal, and the second switch packet to receive first driving signal and a second end
The output end, a control terminal is coupled to containing a first end to be coupled to one to receive second driving signal and a second end and connect
Ground terminal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104137721 | 2015-11-16 | ||
| TW104137721A TWI567710B (en) | 2015-11-16 | 2015-11-16 | Display device and gate driver on array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105405386A CN105405386A (en) | 2016-03-16 |
| CN105405386B true CN105405386B (en) | 2019-03-15 |
Family
ID=55470842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610003272.6A Expired - Fee Related CN105405386B (en) | 2015-11-16 | 2016-01-04 | Display device and grid driving circuit on array |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN105405386B (en) |
| TW (1) | TWI567710B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107612539B (en) * | 2017-09-30 | 2020-04-10 | 深圳市华星光电技术有限公司 | Method for processing clock input signal abnormity of level converter |
| CN109119036B (en) * | 2018-07-26 | 2020-07-28 | 深圳市华星光电技术有限公司 | Liquid crystal panel |
| CN109192157A (en) * | 2018-09-26 | 2019-01-11 | 深圳市华星光电技术有限公司 | GOA circuit and display device |
| CN109215557A (en) * | 2018-10-18 | 2019-01-15 | 深圳市华星光电技术有限公司 | GOA driving circuit and display panel |
| TWI699740B (en) * | 2018-12-14 | 2020-07-21 | 友達光電股份有限公司 | Sequential pulse generator |
| CN112509512B (en) * | 2020-12-14 | 2024-02-23 | 福建华佳彩有限公司 | GIP circuit and driving method |
| TWI783570B (en) * | 2021-07-12 | 2022-11-11 | 友達光電股份有限公司 | Driving device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102867478A (en) * | 2012-08-06 | 2013-01-09 | 友达光电股份有限公司 | Display and gate driver thereof |
| CN103137207A (en) * | 2012-11-22 | 2013-06-05 | 友达光电股份有限公司 | Shift temporary storage device |
| CN103325354A (en) * | 2013-02-25 | 2013-09-25 | 友达光电股份有限公司 | Gate drive circuit |
| KR20140101152A (en) * | 2013-02-08 | 2014-08-19 | 건국대학교 산학협력단 | Gate driver circuit for generating stable output signal using two clocks |
| CN104658467A (en) * | 2014-12-24 | 2015-05-27 | 友达光电股份有限公司 | Display device and repairing method thereof |
| CN104992658A (en) * | 2015-05-08 | 2015-10-21 | 友达光电股份有限公司 | Gate drive circuit |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI430242B (en) * | 2006-08-01 | 2014-03-11 | Samsung Display Co Ltd | Display device and method of driving a display device |
| TWI380275B (en) * | 2008-07-11 | 2012-12-21 | Wintek Corp | Shift register |
| TWI416530B (en) * | 2009-03-25 | 2013-11-21 | Wintek Corp | Shift register |
| TWI426521B (en) * | 2009-07-31 | 2014-02-11 | Wintek Corp | Bidirectional shift register |
| TWI406258B (en) * | 2010-03-11 | 2013-08-21 | Chunghwa Picture Tubes Ltd | Double-gate liquid crystal display device and related driving method |
| CN101846835B (en) * | 2010-06-11 | 2012-11-07 | 华映光电股份有限公司 | Opposed scanning signal transmitting system and method thereof |
| KR101794267B1 (en) * | 2011-01-13 | 2017-11-08 | 삼성디스플레이 주식회사 | Gate driving circuit and display device having them |
| TWI475538B (en) * | 2012-08-29 | 2015-03-01 | Giantplus Technology Co Ltd | A driving circuit for bi-direction scanning. |
-
2015
- 2015-11-16 TW TW104137721A patent/TWI567710B/en not_active IP Right Cessation
-
2016
- 2016-01-04 CN CN201610003272.6A patent/CN105405386B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102867478A (en) * | 2012-08-06 | 2013-01-09 | 友达光电股份有限公司 | Display and gate driver thereof |
| CN103137207A (en) * | 2012-11-22 | 2013-06-05 | 友达光电股份有限公司 | Shift temporary storage device |
| KR20140101152A (en) * | 2013-02-08 | 2014-08-19 | 건국대학교 산학협력단 | Gate driver circuit for generating stable output signal using two clocks |
| CN103325354A (en) * | 2013-02-25 | 2013-09-25 | 友达光电股份有限公司 | Gate drive circuit |
| CN104658467A (en) * | 2014-12-24 | 2015-05-27 | 友达光电股份有限公司 | Display device and repairing method thereof |
| CN104992658A (en) * | 2015-05-08 | 2015-10-21 | 友达光电股份有限公司 | Gate drive circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI567710B (en) | 2017-01-21 |
| TW201719606A (en) | 2017-06-01 |
| CN105405386A (en) | 2016-03-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105405386B (en) | Display device and grid driving circuit on array | |
| CN103730094B (en) | Goa circuit structure | |
| CN104282270B (en) | Gate drive circuit, displaying circuit, drive method and displaying device | |
| CN103680386B (en) | For GOA circuit and the display device of flat pannel display | |
| CN103928005B (en) | For the GOA unit of common driving grid and public electrode, driving circuit and array | |
| CN103985369B (en) | Array substrate row driving circuit and liquid crystal display device | |
| CN104517575B (en) | Shifting register and level-transmission gate drive circuit | |
| CN107958656A (en) | GOA circuits | |
| CN103117091B (en) | Shift buffer and driving method thereof | |
| CN104992662B (en) | GOA unit and its driving method, GOA circuits, display device | |
| CN104537987B (en) | Charging scanning and charge sharing scanning dual-output GOA circuit | |
| CN105405406A (en) | Gate drive circuit and display using same | |
| CN108962166A (en) | GOA circuit and liquid crystal display device with the GOA circuit | |
| CN106601206A (en) | GOA gate drive circuit and liquid crystal display device | |
| CN106448606A (en) | GOA (gate driver on array) driving circuit | |
| CN105957493B (en) | Display device and driving method thereof | |
| CN104810058A (en) | Shifting register, driving method of shifting register, grid driving circuit and display device | |
| CN105513552A (en) | Driving circuit, driving method and display device | |
| CN106910450A (en) | Gate driving circuit and display device | |
| CN105513530A (en) | Shift register and control method thereof | |
| CN104299652A (en) | Shifting register and driving method thereof as well as grid electrode driving circuit and display device | |
| CN106157916A (en) | A kind of drive element of the grid and drive circuit | |
| CN103426415A (en) | Drive circuit of liquid crystal display panel and waveform driving approach | |
| CN105185342A (en) | Grid drive substrate and liquid crystal display employing same | |
| CN107799088A (en) | A kind of GOA circuits and liquid crystal display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190315 Termination date: 20210104 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |