CN105372892B - array substrate and liquid crystal display panel - Google Patents
array substrate and liquid crystal display panel Download PDFInfo
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- CN105372892B CN105372892B CN201510955722.7A CN201510955722A CN105372892B CN 105372892 B CN105372892 B CN 105372892B CN 201510955722 A CN201510955722 A CN 201510955722A CN 105372892 B CN105372892 B CN 105372892B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
Abstract
It includes multi-strip scanning line that the present invention, which discloses a kind of array substrate and liquid crystal display panel, the array substrate,；Multiple data lines intersect with multi-strip scanning line array substrate is divided into multiple pixel regions；Each pixel region includes main pixel region and sub-pixel region, each sub-pixel region includes sharing electric capacity, and along the direction of the marginal position from array substrate to center, the capacitance of sharing electric capacity is sequentially reduced, and when being shown, current potential on the sub-pixel region of the marginal position of array substrate is less than the current potential on the sub-pixel region of center, so that the brightness in the sub-pixel region of array substrate center is greater than the brightness in the sub-pixel region of marginal position, achieve the purpose that eliminate two sides whiting with this, mentions high display quality.
Description
Technical field
The present invention relates to LCD Technology fields, more particularly to a kind of array substrate and liquid crystal display panel.
Background technique
Liquid crystal display has many merits such as thin fuselage, power saving, radiationless, is widely used.On existing market
Liquid crystal display be largely backlight liquid crystal display comprising liquid crystal display panel and backlight module；LCD display
The working principle of plate is liquid crystal molecule to be placed in the parallel glass substrate of two panels, and apply driving on two panels glass substrate
Voltage controls the direction of rotation of liquid crystal molecule, the light refraction of backlight module is come out generates picture.
In existing large scale liquid crystal display panel, the mode of bilateral turntable driving is generally taken to be driven, due to
The influence of delay circuit, the charge rate that will cause region of the liquid crystal display panel the right and left at driving chip position are higher than
The charge rate of panel intermediate region keeps liquid crystal display panel the right and left brighter and intermediate darker, that is, LCD display occurs
At left and right sides of plate the phenomenon that whiting, this has an adverse effect to the display quality of liquid crystal display.
Summary of the invention
The invention mainly solves the technical problem of providing a kind of array substrate and liquid crystal display panels, can eliminate liquid crystal
At left and right sides of display panel the phenomenon that whiting, high display quality is mentioned.
In order to solve the above technical problems, one technical scheme adopted by the invention is that：A kind of liquid crystal display panel, institute are provided
Stating liquid crystal display panel includes：
Array substrate, including：
Multi-strip scanning line is arranged in the array substrate；
Multiple data lines are arranged in the array substrate, and the multiple data lines and the multi-strip scanning line are mutual
Intersect so that the array substrate is divided into multiple pixel regions；
Color membrane substrates are oppositely arranged with the array substrate；
Liquid crystal layer is folded between the array substrate and the color membrane substrates；
Wherein, each pixel region includes main pixel region and sub-pixel region, each sub-pixel region packet
Sharing electric capacity is included, and along the marginal position from the array substrate to the direction of the center of the array substrate, it is described
The capacitance of sharing electric capacity is sequentially reduced, and when being shown, on the sub-pixel region of the marginal position of the array substrate
Current potential be less than the array substrate center sub-pixel region on current potential.
Wherein, the main pixel region in each pixel region includes：
Main switch element is arranged in the array substrate, and the main switch element includes：
Grid is electrically connected a corresponding scan line；
Source electrode is electrically connected a corresponding data line；
Drain electrode；
Main pixel electrode is arranged in the array substrate, and is electrically connected the drain electrode of the main switch element；
The sub-pixel region in each pixel region further includes：
Secondary switch element is arranged in the array substrate, and the secondary switch element includes：
Grid is electrically connected the corresponding scan line；
Source electrode is electrically connected the corresponding data line；
Drain electrode；
Sub-pixel electrode is arranged in the array substrate, and is electrically connected the drain electrode of the secondary switch element；
Share switch element, is arranged in the array substrate, the sharing switch element includes：
Grid is electrically connected next adjacent scan line of the corresponding scan line；
Source electrode is electrically connected the sub-pixel electrode；
Drain electrode；
The sharing electric capacity is electrically connected the drain electrode for sharing switch element；
Wherein, when the next adjacent scan line is enabled, the sharing switching elements conductive makes the sharing
Capacitor shares the charge on the sub-pixel electrode.
Wherein, the main pixel region area in each pixel region is less than the sub-pixel region area.
Wherein, the main switch element, the secondary switch element and the switch element of sharing are thin film transistor (TFT).
Wherein, described along the marginal position from the array substrate to the direction of the center of the array substrate
The different capacitances of the capacitance at least two of sharing electric capacity.
In order to solve the above technical problems, the present invention also provides a kind of array substrate, the array substrate includes：
Multi-strip scanning line；
Multiple data lines intersect with the multi-strip scanning line the array substrate is divided into multiple pixel regions
Domain；
Wherein, each pixel region includes main pixel region and sub-pixel region, each sub-pixel region packet
Sharing electric capacity is included, and along the marginal position from the array substrate to the direction of the center of the array substrate, it is described
The capacitance of sharing electric capacity is sequentially reduced, and when being shown, on the sub-pixel region of the marginal position of the array substrate
Current potential be less than the array substrate center sub-pixel region on current potential.
Wherein, the main pixel region in each pixel region includes：
Main switch element is arranged in the array substrate, and the main switch element includes：
Grid is electrically connected a corresponding scan line；
Source electrode is electrically connected a corresponding data line；
Drain electrode；
Main pixel electrode is arranged in the array substrate, and is electrically connected the drain electrode of the main switch element；
The sub-pixel region in each pixel region further includes：
Secondary switch element is arranged in the array substrate, and the secondary switch element includes：
Grid is electrically connected the corresponding scan line；
Source electrode is electrically connected the corresponding data line；
Drain electrode；
Sub-pixel electrode is arranged in the array substrate, and is electrically connected the drain electrode of the secondary switch element；
Share switch element, is arranged in the array substrate, the sharing switch element includes：
Grid is electrically connected next adjacent scan line of the corresponding scan line；
Source electrode is electrically connected the sub-pixel electrode；
Drain electrode；
The sharing electric capacity is electrically connected the drain electrode for sharing switch element；
Wherein, when the next adjacent scan line is enabled, the sharing switching elements conductive makes the sharing
Capacitor shares the charge on the sub-pixel electrode.
Wherein, the main pixel region area in each pixel region is less than the sub-pixel region area.
Wherein, the main switch element, the secondary switch element and the switch element of sharing are thin film transistor (TFT).
Wherein, along the marginal position from the liquid crystal display panel to the side of the center of the liquid crystal display panel
To the different capacitances of the capacitance at least two of the sharing electric capacity.
The beneficial effects of the invention are as follows：It is in contrast to the prior art, the array substrate of the invention and liquid crystal
Show panel by the direction along the marginal position from the array substrate to the center of the array substrate, by each institute
The capacitance for stating the sharing electric capacity in sub-pixel region is sequentially reduced, thus the different capacitances for passing through the sharing electric capacity
So that the current potential in the corresponding sub-pixel region is different, so that the sub-pixel region of the array substrate center is bright
Degree is greater than the brightness in the sub-pixel region of the marginal position of the array substrate, achievees the purpose that eliminate two sides whiting with this, mention
High display quality.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of array substrate of the invention；
Fig. 2 is the equivalent circuit diagram of Fig. 1；
Fig. 3 is the structural schematic diagram of liquid crystal display panel of the invention.
Specific embodiment
Referring to Fig. 1, being the structural schematic diagram of array substrate 1 of the invention.As shown in Figure 1, being set in the array substrate 1
There are multi-strip scanning line and multiple data lines, scan line and data line are located at the one side of the close liquid crystal layer of the array substrate 1, and
Multiple data lines and multi-strip scanning line intersect so that the array substrate 1 is divided into multiple pixel regions 2.Generally, more
It is arranged in parallel between data line, it is arranged in parallel between multi-strip scanning line, it mutually hangs down between data line and scan line
Straight to intersect, in other embodiments, other arrangements can also be used in multiple data lines and multi-strip scanning line.
It is the equivalent circuit diagram of array substrate 1 of the invention please refer to Fig. 2.Each pixel region 2 includes main pixel
Region 21 and sub-pixel region 22, the brightness of each pixel region 2 are the brightness and the sub-pixel of the main pixel region 21
The mixing of the brightness in region 22, the area of the main pixel region 21 is less than the area in the sub-pixel region 22, due to each
The sub-pixel region 22 includes sharing electric capacity Cdown, and the sharing electric capacity Cdown shares the electricity on the sub-pixel region 22
Lotus, so that the current potential on the sub-pixel region 22 is less than the current potential on the main pixel region 21, i.e., the described secondary picture when display
Brightness on plain region 22 is less than the brightness on the main pixel region 21, and when designing the array substrate 1 along from institute
The marginal position of array substrate 1 is stated to the direction of the center of the array substrate 1, the capacitor of the sharing electric capacity Cdown
Value is sequentially reduced, i.e., in the center of the array substrate 1, the capacitance of the sharing electric capacity Cdown is minimum, in the battle array
The capacitance of the marginal position of column substrate 1, the sharing electric capacity Cdown is maximum, since the sharing electric capacity Cdown can drag down institute
The current potential on sub-pixel region 22 is stated, allows for 1 marginal position of array substrate in this way due to the capacitor of sharing electric capacity Cdown
It is worth larger, larger to the sub-pixel region 22 drop-down current potential, the sub-pixel region 22 is darker, and in the array substrate 1
Middle position, since the capacitance of the sharing electric capacity Cdown is smaller, to the sub-pixel region 22 drop-down current potential it is less,
The 22 opposite edges position of sub-pixel region is brighter, in this way in actual displayed, time of the center of the array substrate 1
The brightness of pixel region 22 is higher than the brightness in the sub-pixel region 22 of the marginal position of the array substrate 1, simultaneously because institute
State the main pixel region of the marginal position of array substrate 1 described in the brightness ratio of the main pixel region 21 of the center of array substrate 1
The brightness in domain 21 is low, therefore makes the entire battle array after the luminance mix in the main pixel region 21 and the sub-pixel region 22
1 brightness throughout of column substrate is uniform, achievees the purpose that eliminate two sides whiting, mentions high display quality.
In the present embodiment, along the marginal position from the array substrate 1 to the center of the array substrate 1
Direction, the different capacitances of the capacitance at least two of the sharing electric capacity Cdown, can also according to the design needs, along from
The marginal position of the array substrate 1 to the center of the array substrate 1 direction, by the sharing electric capacity Cdown's
Capacitance is set as multiple and different capacitances.
As shown in Fig. 2, the main pixel region 21 in each pixel region 2 includes main switch element T1 and main pixel electrode
31, the sub-pixel region 22 in each pixel region 2 includes time switch element T2 and sub-pixel electrode 32, the main switch element
T1, the main pixel electrode 31, the secondary switch element T2 and the sub-pixel electrode 32 are separately positioned on the array substrate 1
On, the main switch element T1 includes grid, source electrode and drain electrode, and the grid of the main switch element T1 is electrically connected a correspondence
Scan line G1, the main switch element T1 source electrode be electrically connected a corresponding data line D1, the main switch element T1
Drain electrode electrically 31 connect with main pixel electrode.The secondary switch element T2 includes grid, source electrode and drain electrode, described switch member
The grid of part T2 is electrically connected corresponding scan line G1, and the source electrode of the secondary switch element T2 is electrically connected corresponding data line
The drain electrode of D1, the secondary switch element T2 and the sub-pixel electrode 32 are electrically connected.
In the present embodiment, the main pixel region 21 and the sub-pixel region 22 include liquid crystal capacitance Clc and storage
Capacitor Cst, the liquid crystal capacitance Clc is by the liquid crystal layer among pixel electrode and public electrode and pixel electrode and public electrode
It is formed, the storage capacitors Cst is formed by the grid of switch element and drain electrode and the grid insulating layer intermediate with drain electrode.
The sub-pixel region 22 further includes sharing switch element T3 and sharing electric capacity Cdown, the sharing switch element
T3 includes grid, source electrode and drain electrode, the grid for sharing switch element T3 be electrically connected corresponding scan line G1 it is adjacent under
One scan line G2, the source electrode for sharing switch element T3 are electrically connected the sub-pixel in the corresponding sub-pixel region 22
Electrode 32, the drain electrode for sharing switch element T3 are electrically connected the sharing electric capacity Cdown.When next adjacent scan line
When G2 is enabled, the sharing switch element T3 conducting makes the sharing electric capacity Cdown share the corresponding sub-pixel electrode 32
On charge.
In the present embodiment, the main switch element T1, the secondary switch element T2 and the sharing switch element T3
It is thin film transistor (TFT).
In liquid crystal display panel display, when scanning signal is scanned to the main switch element T1 and the secondary switch element
When the corresponding scan line G1 of T2, i.e., the described main switch element T1 and the corresponding scan line G1 of the secondary switch element T2 are enabled,
The main switch element T1 and the secondary switch element T2 conducting, the main pixel electrode 31 and the sub-pixel electrode 32 are simultaneously
Same potential is charged to, the at this moment described main pixel region 21 and the sub-pixel region 22 have same brightness, then, scanning letter
Number scanning lower scan line G2 adjacent to above-mentioned corresponding scan line G1, i.e. the adjacent lower scan line G2 is enabled, described
Main switch element T1 and the secondary switch element T2 are closed, and the sharing switch element T3 connecting with the scan line G2 is led
It is logical, the Partial charge of the sub-pixel electrode 32 is transferred on the sharing electric capacity Cdown, as the sharing electric capacity Cdown
Capacitance difference when, then it is also just different to be transferred to the charge on the sharing electric capacity Cdown for the sub-pixel electrode 32, that is, exists
In the case that voltage is certain, the capacitance of the sharing electric capacity Cdown the big, the electricity being transferred on the sharing electric capacity Cdown
Lotus is more, and the current potential on the sub-pixel electrode 32 is smaller, and the sub-pixel region 22 is darker, conversely, the then sub-pixel area
Domain 22 is brighter, therefore, when the direction along the marginal position from the array substrate 1 to the center of the array substrate 1,
When the capacitance of the sharing electric capacity Cdown is sequentially reduced, then the sub-pixel region 22 of the center of the array substrate 1
Brightness is higher than the brightness in the sub-pixel region 22 of the marginal position of the array substrate 1, simultaneously because the array substrate 1
The brightness of the main pixel region 21 of the marginal position of array substrate 1 described in the brightness ratio of the main pixel region 21 of center is low,
Therefore make the entire array substrate 1 bright everywhere after the luminance mix in the main pixel region 21 and the sub-pixel region 22
Degree uniformly, achievees the purpose that eliminate two sides whiting, mentions high display quality.
Referring to Fig. 3, being a kind of schematic diagram of liquid crystal display panel 2 of the present invention.The liquid crystal display panel 2 includes described
Array substrate 1, liquid crystal layer 3 and color membrane substrates 4, the liquid crystal layer 3 setting the array substrate 1 and the color membrane substrates 4 it
Between.
The array substrate passes through along the marginal position from the array substrate to the center of the array substrate
Direction, the capacitance of the sharing electric capacity in each sub-pixel region is sequentially reduced, to pass through the sharing
The different capacitances of capacitor make the current potential for corresponding to the sub-pixel region different, so that the array substrate center
Sub-pixel region brightness be greater than the array substrate marginal position sub-pixel region brightness, elimination two is reached with this
The purpose of side whiting, mentions high display quality.
Mode the above is only the implementation of the present invention is not intended to limit the scope of the invention, all to utilize this
Equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content, it is relevant to be applied directly or indirectly in other
Technical field is included within the scope of the present invention.
Claims (10)
1. a kind of liquid crystal display panel, which is characterized in that the liquid crystal display panel includes：
Array substrate, including：
Multi-strip scanning line is arranged in the array substrate；
Multiple data lines are arranged in the array substrate, and the multiple data lines intersect with the multi-strip scanning line
The array substrate is divided into multiple pixel regions；
Color membrane substrates are oppositely arranged with the array substrate；
Liquid crystal layer is folded between the array substrate and the color membrane substrates；
Wherein, each pixel region includes main pixel region and sub-pixel region, and each sub-pixel region includes point
Capacitor is enjoyed, and along the marginal position from the array substrate to the direction of the center of the array substrate, the sharing
The capacitance of capacitor is sequentially reduced, and when being shown, the electricity on the sub-pixel region of the marginal position of the array substrate
Position is less than the current potential on the sub-pixel region of the center of the array substrate.
2. liquid crystal display panel according to claim 1, which is characterized in that the main picture in each pixel region
Plain region includes：
Main switch element is arranged in the array substrate, and the main switch element includes：
Grid is electrically connected a corresponding scan line；
Source electrode is electrically connected a corresponding data line；
Drain electrode；
Main pixel electrode is arranged in the array substrate, and is electrically connected the drain electrode of the main switch element；
The sub-pixel region in each pixel region further includes：
Secondary switch element is arranged in the array substrate, and the secondary switch element includes：
Grid is electrically connected the corresponding scan line；
Source electrode is electrically connected the corresponding data line；
Drain electrode；
Sub-pixel electrode is arranged in the array substrate, and is electrically connected the drain electrode of the secondary switch element；
Share switch element, is arranged in the array substrate, the sharing switch element includes：
Grid is electrically connected next adjacent scan line of the corresponding scan line；
Source electrode is electrically connected the sub-pixel electrode；
Drain electrode；
The sharing electric capacity is electrically connected the drain electrode for sharing switch element；
Wherein, when the next adjacent scan line is enabled, the sharing switching elements conductive makes the sharing electric capacity
Share the charge on the sub-pixel electrode.
3. liquid crystal display panel according to claim 1, which is characterized in that the main picture in each pixel region
Plain region area is less than the sub-pixel region area.
4. liquid crystal display panel according to claim 2, which is characterized in that the main switch element, described switch member
Part is thin film transistor (TFT) with the switch element of sharing.
5. liquid crystal display panel according to claim 1, which is characterized in that along the marginal position from the array substrate
To the direction of the center of the array substrate, the different capacitances of the capacitance at least two of the sharing electric capacity.
6. a kind of array substrate, which is characterized in that the array substrate includes：
Multi-strip scanning line；
Multiple data lines intersect with the multi-strip scanning line the array substrate is divided into multiple pixel regions；
Wherein, each pixel region includes main pixel region and sub-pixel region, and each sub-pixel region includes point
Capacitor is enjoyed, and along the marginal position from the array substrate to the direction of the center of the array substrate, the sharing
The capacitance of capacitor is sequentially reduced, and when being shown, the electricity on the sub-pixel region of the marginal position of the array substrate
Position is less than the current potential on the sub-pixel region of the center of the array substrate.
7. array substrate according to claim 6, which is characterized in that the main pixel region in each pixel region
Domain includes：
Main switch element is arranged in the array substrate, and the main switch element includes：
Grid is electrically connected a corresponding scan line；
Source electrode is electrically connected a corresponding data line；
Drain electrode；
Main pixel electrode is arranged in the array substrate, and is electrically connected the drain electrode of the main switch element；
The sub-pixel region in each pixel region further includes：
Secondary switch element is arranged in the array substrate, and the secondary switch element includes：
Grid is electrically connected the corresponding scan line；
Source electrode is electrically connected the corresponding data line；
Drain electrode；
Sub-pixel electrode is arranged in the array substrate, and is electrically connected the drain electrode of the secondary switch element；
Share switch element, is arranged in the array substrate, the sharing switch element includes：
Grid is electrically connected next adjacent scan line of the corresponding scan line；
Source electrode is electrically connected the sub-pixel electrode；
Drain electrode；
The sharing electric capacity is electrically connected the drain electrode for sharing switch element；
Wherein, when the next adjacent scan line is enabled, the sharing switching elements conductive makes the sharing electric capacity
Share the charge on the sub-pixel electrode.
8. array substrate according to claim 6, which is characterized in that the main pixel region in each pixel region
Domain area is less than the sub-pixel region area.
9. array substrate according to claim 7, which is characterized in that the main switch element, the secondary switch element and
The sharing switch element is thin film transistor (TFT).
10. array substrate according to claim 6, which is characterized in that along the marginal position from the array substrate to
The direction of the center of the array substrate, the different capacitances of the capacitance at least two of the sharing electric capacity.
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| CN201510955722.7A CN105372892B (en) | 2015-12-17 | 2015-12-17 | array substrate and liquid crystal display panel |
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| CN106249499B (en) * | 2016-10-18 | 2019-07-23 | 深圳市华星光电技术有限公司 | Curved face display panel and curved-surface display device |
| CN106652805B (en) * | 2016-10-21 | 2019-03-19 | 上海天马微电子有限公司 | Display panel and display device |
| CN106652948B (en) * | 2016-12-27 | 2019-04-12 | 深圳市华星光电技术有限公司 | A kind of driving circuit and display panel |
| CN109658900B (en) * | 2019-02-28 | 2021-01-01 | 京东方科技集团股份有限公司 | Driving method, compensation circuit and driving device of display panel and display device |
| CN110109296A (en) * | 2019-04-12 | 2019-08-09 | 深圳市华星光电半导体显示技术有限公司 | A kind of array substrate and liquid crystal display device |
| CN110794626A (en) * | 2019-10-21 | 2020-02-14 | 深圳市华星光电半导体显示技术有限公司 | Pixel structure and liquid crystal display panel |
| CN111862831B (en) * | 2020-07-28 | 2021-06-04 | 惠科股份有限公司 | Display module and display device |
| CN115394237A (en) * | 2021-05-21 | 2022-11-25 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN114002884B (en) * | 2021-09-30 | 2022-10-21 | 惠科股份有限公司 | Array substrate, display panel and display |
| CN114815408B (en) * | 2022-04-14 | 2023-09-26 | Tcl华星光电技术有限公司 | Display panel and display device |
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| CN1967635A (en) * | 2005-11-15 | 2007-05-23 | 统宝光电股份有限公司 | Systems with reduced color lines at edges of associated display devices |
| CN104062824A (en) * | 2014-06-18 | 2014-09-24 | 深圳市华星光电技术有限公司 | Pixel structure and display panel with same |
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