CN105372683A - Real-time signal receiving and processing system of public frequency points of Beidou navigation satellite system and GPS - Google Patents

Abstract

The present invention discloses a real-time signal receiving and processing system of public frequency points of a Beidou navigation satellite system and a GPS. Signals of the public frequency points of the Beidou navigation satellite system and the GPS enter three RF radio frequency front end modules through the same antenna, are subjected to a series of amplification, filtering and down-conversion processing, and are converted to 2bit medium frequency digital signals through the A/D (Analog to Digital) conversion, and the medium frequency digital signals are acquired to the internal storage of an FPGA under the control of the FPGA, are stored to be a data block with a certain length in a ping-pong mode, and are transmitted to a computer in a block mode through a USB controller. The real-time signal receiving and processing system of public frequency points of a Beidou navigation satellite system and a GPS is able to perform rapid capture and real-time data processing of signals of the public frequency points of the Beidou navigation satellite system and the GPS on the software architecture of a computer platform, and the like, therefore positioning accuracy, reliability, integrity and availability of a single positioning system are substantially improved; and moreover, the software development on the basis of the software radio technology is performed, thereby getting rid of the algorithm of a traditional hardware receiver and realizing the reconfiguration of a research mode.

Description

The live signal receiving processing system of a kind of Beidou II and the public frequency of GPS

Technical field:

The present invention relates to a kind of Signal reception disposal system of navigator fix, be specifically related to a kind of Beidou II and GPS public frequency live signal receiving processing system.

Background technology:

" China Aerospace white paper in 2006 " is announced to start five large aerospace engineering at the five-year, and the second generation " Big Dipper " satellite navigation system wherein with military use will complete deployment in 4 years.Have expert to represent, after two generations " Big Dipper " satellite system has been disposed, accurate attack can be started to Small object by China, and the U.S. also has media to think, and the plan of the middle national expenditures Big Dipper is to suppress the military superiority of American satellite.Along with the lifting of china's overall national strength and the life of satellite navigation and location system overall permeation ordinary people, Kosovo War and second time Gulf War GPS of America guidance high precision is also had to hit the temptation of weapon, the global navigation satellite system building a similar GPS starts to bring into schedule, formal construction " Big Dipper " satellite navigation and location system (" No. two, the Big Dipper ") from 2007.

" Big Dipper " satellite navigation and location system needs transmitting 35 satellites, has more 11 fully than GPS.According to planning, " Big Dipper " satellite navigation and location system will be made up of 5 satellites and 30 non-geo satellites, adopt " Dongfanghong "-No. 3 satellite platforms.30 non-geo satellites are subdivided into again 27 medium earth orbit satellites (MEO) and 3 inclined GEO satellite (IGSO) compositions, and 27 MEO satellites are evenly distributed in three planes at 55 degree, inclination angle, orbit altitude 21500 kilometers." Big Dipper " satellite navigation and location system will provide open service and authorization service.Open service provides free location at service area, and test the speed and time service service, positioning precision is 10 meters, and time service precision was 50 nanoseconds, and rate accuracy is 0.2 meter per second.Authorization service is then the vest of military use, and will provide safer and more high-precision location to authorized user, and test the speed, time service service, additional succession is from the communication service function of Big Dipper pilot system.

Beidou II adopts the carrier frequency identical with GPS and modulation system, but uses different pseudo-random codes and data coding mode, and GPS can not process Beidou II signal.And the receiver that can process Beidou II signal on a small quantity also just does aftertreatment by conventional GPS receivers, but can not as real-time application.Usually, warm start about 1 second, automatically the processing time of location was greater than 10 seconds at tens seconds the cold start-up time of GPS hardware receiver.Therefore, software study quick capturing method is adopted to be have using value very much, especially based on the software processing method of the compatible Beidou II/GPS positioning signal of software radio thought, not only also do not have product-level terminal to occur, and there is the development & application advantage of Reconfigurability.

Summary of the invention:

The object of the invention is to the defect overcoming prior art existence, provide a kind of Beidou II and GPS public frequency live signal receiving processing system.

A kind of Beidou II of the present invention and GPS public frequency real-time reception processing signals system, comprise Beidou II and the public frequency of GPS the one RF RF front-end module that a Max2741 is master chip, a GRM7520 is Beidou II and the public frequency of GPS the 2nd RF RF front-end module of master chip, a GP2015 is Beidou II and the public frequency of GPS the 3rd RF RF front-end module of master chip, a Spartan3 Series FPGA chip, a CY7C68013A as USB controller.

Beidou II and the public frequency live signal of GPS enter three RF RF front-end modules by the same antenna, through a series of amplification, filtering and down-converted, and the digital intermediate frequency signal of 2bit is converted to by A/D, digital intermediate frequency signal is under the control of FPGA, in the internal storage of collected FPGA, the data block of certain length is stored as, finally by USB controller, by Bulk transport on computing machine with ping-pong; Wherein:

Two digital intermediate frequency signal lines, if sampling clock line and three SPI DLL (dynamic link library) control lines in Beidou II and the public frequency of GPS the one RF RF front-end module Max2741 chip are drawn all respectively, and are connected on the programmable I/O mouth of Spartan3 Series FPGA;

Two digital intermediate frequency signal lines and the if sampling clock line of Beidou II and the public frequency of GPS the 2nd RF RF front-end module GRM7520 chip are drawn respectively, and are connected on the programmable I/O mouth of Spartan3 Series FPGA;

Two digital intermediate frequency signal lines, two differential clocks output lines and an if sampling clock signal line in Beidou II and the public frequency of GPS the 3rd RF RF front-end module GP2015 are drawn respectively, and are connected on the programmable I/O mouth of Spartan3 Series FPGA;

USB controller CY7C68013A chip is connected on the programmable I/O mouth of Spartan3 Series FPGA;

Spartan3 Series FPGA chip reads the data of which RF RF front-end module, then controlled with crossing USB transmission instruction by host computer procedure; FPGA by the 2bit intermediate frequency data read in chronological sequence little-endian merge into 1Byte data, the 2bit data placement namely read at first is at minimum 2 of 1Byte data; Data are stored in the FIFO of FPGA inside with ping-pong, and form data block, a data block comprises the data of the integral multiple of 4ms; When data are filled with a data block, submit to USB controller, USB controller obtains data in SlaveFIFO mode from FPGA, and transmits data in Bulk transport mode to computing machine, and every secondary data is transmitted as a data block data.

Computing machine processes the data block data received, and concrete steps are as follows:

Step one: software initialization.Read configuration file, the PRN value corresponding according to configuration file initialization 12 passage, wherein path 10 ~ 12 are fixed as Beidou II passage, and passage 1 ~ 9 is fixed as GPS passage; Read local carrier lookup file and CA code lookup file;

Step 2: three threads starting corresponding three RF RF front-end modules, is respectively digital independent and Base-Band Processing thread, localization process thread, data display thread;

Digital independent and Base-Band Processing thread are set to limit priority, and circulation performs reads intermediate frequency data block and carries out this process of Base-Band Processing; Base-Band Processing is a state machine flow process, and have fast Acquisition, wait, serial acquisition, confirm, push, follow the tracks of and free time totally seven kinds of states, the 12 passages in turn machine of getting the hang of process; During software startup, all passage original states of enabling are set to fast Acquisition state, and the passage original state of not enabled is set to idle condition.This thread triggers one-time positioning process event after each seconds arrives;

Localization process thread is set to time high priority, and circulation performs to be waited for localization process event and positions process.When each positioning calculation event arrives, position process; Localization process completes Beidou II signal decoding, Beidou II information extraction, GPS information extraction, its computation of pseudoranges, location compute and position correction according to each channels track result, and triggers a presented event;

Data display thread is set to lowest priority, and circulation performs waits for presented event and display useful information.After each presented event arrives, renewal once shows data;

Step 3: judge whether software exits, if exited, stops all threads, and discharges the storage space that software takies.

In step 2, the fast Acquisition process method step of Beidou II and GPS public frequency live signal is as follows:

Step one: the method being converted to 1 byte by every 2bit, is decomposed into 4 intermediate frequency datas by each byte of data block;

Step 2: sample again to intermediate frequency data, makes the data length of every millisecond become L from N, L be less than n 2 power side's length, sampling rate is N/L, due to sampling after data length be 2 power side, greatly reduce the processing time of FFT;

Step 3: use circle convolution method to carry out correlation computations in frequency field, and the data block of 4 milliseconds is carried out non-coherent addition, improve signal to noise ratio (S/N ratio).Its measure for fulfill is:

$\left|R\[m\]\right|=\underset{i=0}{\overset{3}{\Σ}}\left|IFFT\right\{\left(FFT\right(S_i\[n\]\·\exp \[j\·2\mathrm{\π}fn\])\×{\mathrm{FFT}}^{*}(CA\[n\])\left\}\right|$

In formula, R [m] represents correlation output result, S _i[n] represents input intermediate-freuqncy signal, and CA [n] represents the local C/A code produced, and f represents the local carrier frequency produced;

Step 4: be divided by by the mean value of the maximal value in R [m] and R [m], namely Max (R [m])/Avg (R [m]), if ratio is greater than decision threshold, thinks and captures satellite-signal, if m=m ₁time R [m] obtain maximal value, then the starting point of CA code is m ₁× N/L; Otherwise renewal local carrier frequency, searches for next Frequency point.

the invention has the advantages that:

(1) based on software radio thought, the hardware technology scheme of system only has radio-frequency front-end to downconvert to ifd module, and data acquisition below and positioning signal process all realize in software environment, are no longer dependent on the framework of common hardware receiver.

(2) system architecture of " many radio-frequency front-end+FPGA " is adopted, the local carrier adopting intermediate frequency data to obtain according to lookup table mode and CA code carry out related progressive, in conjunction with the software processing method of real-time releasing memory, by wherein integrated for the software processing method of many advanced persons, realize system-level method innovation.

(3) after software cold start-up, in 5 seconds, complete the search of all Beidou II and the public frequency live signal of GPS.

(4) because local carrier and CA code produce all in advance and be stored in carrier wave look-up table and CA code lookup file, do not need real-time generation, use the bit arithmetic method of improvement in addition, greatly reduce the operand of software, improve processing speed and the efficiency of software.

Accompanying drawing illustrates:

Fig. 1 is the system architecture diagram that inventive method realizes;

In figure: 1---a RF radio-frequency module Max2741;

2---the 2nd RF radio-frequency module GRM7520;

3---the 3rd RF radio-frequency module GP2015;

4---FPGA module;

5---usb bus controller.

Fig. 2 is RF module Max2741 circuit theory diagrams.

Fig. 3 is the 2nd RF module GRM7520 circuit theory diagrams.

Fig. 4 is the 3rd RF module GP2015 circuit theory diagrams.

Fig. 5 is usb bus controller CY7C68013A circuit theory diagrams.

Fig. 6 is FPGA-X3CS400 control circuit schematic diagram.

Fig. 7 is software engineering protocol procedures figure.

Fig. 8 is Base-Band Processing state machine diagram.

Fig. 9 is localization process process flow diagram.

Embodiment:

Below in conjunction with accompanying drawing and embodiment, the present invention is further described.The present invention includes hardware technology scheme and software engineering scheme two parts.

Hardware technology scheme as shown in Figure 1, Beidou II and the public frequency live signal of GPS enter radio-frequency front-end (RF) module by the same antenna, through a series of amplification, filtering and down-converted, and be converted to the digital intermediate frequency signal of 2bit by A/D.Digital intermediate frequency signal, under the control of FPGA, in the inside FIFO of collected FPGA, is stored as the data block of certain length with ping-pong.Finally by USB controller, by Bulk transport on computing machine.This hardware plan mainly comprises following a few part:

As shown in Figure 2, a Max2741 is Beidou II and the public frequency of GPS the one RF RF front-end module of master chip, and the if sampling frequency that this module uses is 13MHz.Two digital intermediate frequency signal lines of Max2741, if sampling clock line and three SPI DLL (dynamic link library) control lines are drawn all respectively, and are connected on the programmable I/O mouth of FPGA.

As shown in Figure 3, a GRM7520 is Beidou II and the public frequency of GPS the 2nd RF RF front-end module of master chip, and the if sampling frequency that this module uses is 16.368MHz.Two digital intermediate frequency signal lines of GRM7520 and if sampling clock line are drawn respectively, and are connected on the programmable I/O mouth of FPGA.

As shown in Figure 4, a GP2015 is Beidou II and the public frequency of GPS the 3rd RF RF front-end module of master chip, and the sample frequency that this module uses is 5.714MHz.Two digital intermediate frequency signal lines of GP2015, two differential clocks output lines and an if sampling clock signal line are drawn respectively, and are connected on the programmable I/O mouth of FPGA.

As shown in Figure 5, a CY7C68013A is as USB controller, and the inner FIFO of CY7C68013A is configured to 512x4 buffering, and 8 position datawires of FIFO are connected with FPGA with write line.Obtain data in SlaveFIFO mode from FPGA, and transmit data in Bulk transport mode to computing machine, every secondary data is transmitted as the data of a data block.

As shown in Figure 6, the fpga chip of a Spartan3XC3S400, is connected to the intermediate frequency data line of three RF radio-frequency front-ends, if sampling clock line, control line, the read-write control line of CY7C68013A, interface clock line and data line above.FPGA, according to the level state of PA1 and PA7 of coupled CY7C68013A, selects reading three radio-frequency modules.During PA1|PA7=00, select GRM7520 module; During PA1|PA7=01, select GP2015 module; During PA1|PA7=10, select Max2741 module.

The block storage space (blockMemory) of Spartan3XC3S400 inside is configured to 2 pieces of FIFO, is respectively A and B, and the size of every block FIFO is 16384x8bit.

Spartan3XC3S400 by the 2bit intermediate frequency data read in chronological sequence little-endian merge into 1Byte data, the 2bit data placement namely read at first is at minimum 2 of 1Byte data, and this process is realized by 8bit shift register.

1Byte data after merging are stored in the FIFO of FPGA inside, form data block.If what read is the data of GRM7520 module, then data block comprises the data of 4ms, and length is 16368Byte; If what read is the data of Max2741 module, then data block comprises the data of 4ms, and length is 13000Byte; If what read is the data of GP2015 module, then data block comprises the data of 8ms, and length is 11428Byte.

The operation of inner 2 FIFOA and B of FPGA uses ping-pong.While FIFOA records intermediate frequency data, the data of FIFOB are transferred to CY7C68013A.After the data of the full data block of FIFOA record, switch to FIFOB to carry out data record, and the data of FIFOA are transferred to CY7C68013A, switch in turn afterwards.If FIFOA data record has been expired, and now the data of FIFOB there also are not end of transmission, then the data monoblock in FIFOA has abandoned, and because monoblock data are the integral multiples in CA code cycle, therefore can not cause the change of CA code phase.

Software engineering scheme as shown in Figure 7, software becomes the reading if sampling data of block by USB interface, by intermediate frequency data in units of millisecond, related progressive is carried out with the local carrier obtained by look-up table mode and CA code, the result of related progressive is used to carry out catching, following the tracks of process, use tracking results to carry out Beidou II and the public frequency signal decoding of GPS, location Calculation and positioning result correction, and upgrade one-time positioning output p.s..The concrete steps that software performs are as follows:

Step one: software initialization.Read configuration file, the PRN value corresponding according to configuration file initialization 12 passage, wherein path 10 ~ 12 are fixed as Beidou II passage, and passage 1 ~ 9 is fixed as GPS passage; Read local carrier lookup file and CA code lookup file.

Step 2: three threads starting corresponding three RF RF front-end modules, is respectively digital independent and Base-Band Processing thread, localization process thread, data display thread.

Digital independent and Base-Band Processing thread are set to limit priority, and circulation performs reads intermediate frequency data block and carries out this process of Base-Band Processing.This thread triggers one-time positioning process event after each seconds arrives.

Localization process thread is set to time high priority, and circulation performs to be waited for localization process event and positions process.When each positioning calculation event arrives, position process.Localization process completes Beidou II signal decoding, Beidou II information extraction, GPS information extraction, its computation of pseudoranges, location compute and position correction according to each channels track result, and triggers a presented event.

Data display thread is set to lowest priority, and circulation performs waits for presented event and display useful information.After each presented event arrives, renewal once shows data.

Step 3: judge whether software exits, if exited, stops all threads, and discharges the storage space that software takies.

Fast Acquisition Processing Algorithm described in software scenario is implemented as follows:

Step one: the method being converted to 1 byte by every 2bit, is decomposed into 4 intermediate frequency datas by each byte of data block.

Step 2: sample again to intermediate frequency data, makes the data length of every millisecond become L from N, L be less than n 2 power side's length, sampling rate is N/L, due to sampling after data length be 2 power side, greatly reduce the processing time of FFT.

Step 3: use circle convolution method to carry out correlation computations in frequency field, and the data block of 4 milliseconds is carried out non-coherent addition, improve signal to noise ratio (S/N ratio).Its measure for fulfill is:

$\left|R\[m\]\right|=\underset{i=0}{\overset{3}{\Σ}}\left|IFFT\right\{\left(FFT\right(S_i\[n\]\·\exp \[j\·2\mathrm{\π}fn\])\×{\mathrm{FFT}}^{*}(CA\[n\])\left\}\right|$

In formula, R [m] represents correlation output result, S _i[n] represents input intermediate-freuqncy signal, and CA [n] represents the local C/A code produced, and f represents the local carrier frequency produced.

Step 4: be divided by by the mean value of the maximal value in R [m] and R [m], namely Max (R [m])/Avg (R [m]), if ratio is greater than decision threshold, thinks and captures satellite-signal, if m=m ₁time R [m] obtain maximal value, then the starting point of CA code is m ₁× N/L.Otherwise renewal local carrier frequency, searches for next Frequency point.

As shown in Figure 8, Base-Band Processing is a state machine flow process, and have fast Acquisition, wait, serial acquisition, confirm, push, follow the tracks of and free time totally seven kinds of states, the 12 passages in turn machine of getting the hang of process.During software startup, all passage original states of enabling are set to fast Acquisition state, and the passage original state of not enabled is set to idle condition.In fast Acquisition state, if passage captures satellite-signal, enter waiting status.After all satellite-signals are completed a fast Acquisition process, then all passages enter pushing status from waiting status, or enter serial acquisition state from fast Acquisition state, afterwards channel status only at serial acquisition, confirm, push and follow the tracks of in this one of four states and change.

Base-Band Processing main task carries out related progressive, and utilize accumulation results to carry out catching, following the tracks of process.Input data are a data point with 2bit, and 4 data points are stored as a byte, as shown in table 1:

Sign bit	Amplitude position	Value
			0	0	+1
0	1	+3
			1	0	-1
1	1	-3

Table 1 if sampling signal

Local carrier and CA code quantize with 1bit, and be that a data point stores with 2bit, 4 data points are stored as a byte, as shown in Table 2:

Sign bit	Amplitude position	Value
			0	0	+1
1	0	-1

Table 2 local carrier and CA coded signal

In the present invention, inputting the related progressive that intermediate-freuqncy signal and local carrier and CA code are carried out, is undertaken by step-by-step XOR.Wherein sign bit and sign bit carry out XOR, and XOR is carried out in amplitude position and amplitude position.On computers, each use word word carries out xor operation, and therefore an xor operation includes 8 data points.After xor operation completes, obtain accumulation results by lookup table mode.

Local carrier is made up of the cosine signal of homophase and orthogonal sinusoidal signal, Frequency point centered by the medium-frequency IF of intermediate-freuqncy signal, take 100Hz as frequency interval, store the carrier wave sampled value of a millisecond between-10kHz ~ 10kHz, as shown in Equation 1, the carrier wave sampled value that 201 carrier frequencies are corresponding is had.

I_carrier[n]＝cos(2π·F _c·[n]/Fs)

Q_carrier[n]＝sin(2π·F _c·[n]/Fs)(1)

Wherein: Fc is local carrier frequency, Fc=intermediate frequency ± 100 × i (Hz), i=-100 ,-99....+99 ,+100, Fs is sample frequency, [n]=0,1,2..... (N-1), and N is the sampling number of 1ms.

Local CA code with 1/16 sampled point for phase step, storing initial phase place from the sampled value of a millisecond of instant, the lead and lag CA code of 0 ~ 4 sampled point, as shown in Equation 2,

$CA\_prompt\[n\]=CA(\frac{F_{CA}}{Fs}\·\[n\]+\mathrm{\τ})$

$CA\_late\[n\]=CA(\frac{F_{CA}}{Fs}\·\[n\]+\mathrm{\τ}+0.5)$

$CA\_early\[n\]=CA(\frac{F_{CA}}{Fs}\·\[n\]+\mathrm{\τ}-0.5)$

Formula 2

Wherein: CA () is CA code function, F _cAfor CA code frequency, Fs is sample frequency, and τ is code start-phase τ=i × F _cA/ (16 × F _s), i=0,1 ... 63, [n]=0,1,2..... (N-1), N is the sampling number of 1ms.

As shown in Figure 9, specifically to perform step as follows for localization process flow process:

Step one: GPS text extracts, the tracking results according to passage extracts gps navigation message, and main three subframes extracting GPS text, obtain satellite time and satellite ephemeris.

Step 2: customer location calculates, calculates the relative pseudorange of user to satellite according to tracking results, uses satellite kind difference to revise pseudorange, uses satellite ephemeris to calculate satellite position, use relative pseudorange and satellite position calculation user coordinates.

Step 3: Beidou II signal decoding, uses Viterbi algorithm to decode.

Step 4: Beidou II information extraction, the Beidou II information type extracted as required comprises: type 6-satellite integrity information, Class1 8-ionospheric grid point shielding mark, type 24-fast/slow composed correction amount, type 25-slowly correcting value, type 26-ionosphere delay correcting value.

Step 5: satellite clock correction and ephemeris correction, uses information type 24 pairs of satellite clock correction and co-ordinates of satellite to revise.

Step 6: ionospheric corrections, according to the user coordinates obtained in step 2 and satellite position, calculate latitude and the longitude of ionosphere pierce point (IPP), determine which 4 net point IPP is positioned at, use information type 26 to obtain ionosphere delay data corresponding to 4 net points, utilize interpolation method to obtain the ionosphere time delay to user of vertical ionospheric time delay corresponding to IPP and satellite.

Step 7: the correction of customer location, the ionosphere time delay obtained in the satellite clock correction and step 6 obtained in step 5 is used to revise the relative pseudorange in step 2, use revised relative pseudorange and revised co-ordinates of satellite to recalculate customer location, obtain revised user coordinates.

Claims (1)

1. a Beidou II and GPS public frequency live signal receiving processing system, it comprises the Beidou II and the public frequency of GPS the one RF RF front-end module that a Max2741 is master chip, a GRM7520 is Beidou II and the public frequency of GPS the 2nd RF RF front-end module of master chip, a GP2015 is Beidou II and the public frequency of GPS the 3rd RF signal processing module of master chip, a Spartan3 Series FPGA chip, one, as the CY7C68013A of USB controller, is characterized in that:

Beidou II and the public frequency live signal of GPS enter three RF RF front-end modules by the same antenna, again through a series of amplification, filtering and down-converted, and the digital intermediate frequency signal of 2bit is converted to by A/D, digital intermediate frequency signal is under the control of FPGA, in the internal storage of collected FPGA, the data block of certain length is stored as, finally by USB controller, by Bulk transport on computing machine with ping-pong; Wherein:

Two digital intermediate frequency signal lines, if sampling clock line and three SPI DLL (dynamic link library) control lines in one RF RF front-end module Max2741 chip of Beidou II and the public frequency of GPS are drawn all respectively, and are connected on the programmable I/O mouth of Spartan3 Series FPGA;

Two digital intermediate frequency signal lines and the if sampling clock line of the 2nd RF RF front-end module GRM7520 chip of Beidou II and the public frequency of GPS are drawn respectively, and are connected on the programmable I/O mouth of Spartan3 Series FPGA;

Two digital intermediate frequency signal lines, two differential clocks output lines and an if sampling clock signal line in 3rd RF signal processing module GP2015 of Beidou II and the public frequency of GPS are drawn respectively, and are connected on the programmable I/O mouth of Spartan3 Series FPGA;

USB controller CY7C68013A chip is connected on the programmable I/O mouth of Spartan3 Series FPGA;

Spartan3 Series FPGA chip reads the data of which RF RF front-end module, then controlled with crossing USB transmission instruction by host computer procedure; FPGA by the 2bit intermediate frequency data read in chronological sequence little-endian merge into 1Byte data, the 2bit data placement namely read at first is at minimum 2 of 1Byte data; Data are stored in the FIFO of FPGA inside with ping-pong, and form data block, a data block comprises the data of the integral multiple of 4ms; When data are filled with a data block, submit to USB controller, USB controller obtains data in SlaveFIFO mode from FPGA, and transmits data in Bulk transport mode to computing machine, and every secondary data is transmitted as a data block data.