CN105355606A - Novel system-in-package - Google Patents
Novel system-in-package Download PDFInfo
- Publication number
- CN105355606A CN105355606A CN201510633468.9A CN201510633468A CN105355606A CN 105355606 A CN105355606 A CN 105355606A CN 201510633468 A CN201510633468 A CN 201510633468A CN 105355606 A CN105355606 A CN 105355606A
- Authority
- CN
- China
- Prior art keywords
- substrate
- chip
- metal
- mosfet chip
- low side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Abstract
The embodiment of the invention discloses a novel system-in-package, which comprises a substrate, a high-end MOSFET chip, a first metal terminal, a low-end MOSFET chip, a broken line metal sheet, an integrated circuit IC chip and at least one passive device. According to the novel system-in-package, the passive devices in a packaged circuit are arranged at two sides of the broken line metal sheet, so that protection on electromagnetic interference of the passive devices by the broken line metal sheet is achieved. Meanwhile, the IC chip is arranged on the substrate through a metal ball in an inverted manner to form a shortest circuit, so that the resistance is reduced. The two MOSFET chips are stacked on the substrate by a mold stacking process, so that the dimension of the system-in-package is reduced.
Description
Technical field
The embodiment of the present invention relates to semiconductor packaging, particularly relates to the encapsulation of a kind of novel system level.
Background technology
As shown in Figure 1, for by 2 N-type mos field effect transistor (Metal-Oxide-SemiconductorField-EffectTransistor, the circuit diagram of the power switching device MOSFET) be connected to form, its middle and high end (HighSide, HS) drain D 1 of MOSFET connects voltage input (Vin) end, its source S 1 connects low side (LowSide, LS) drain D 2 of MOSFET, the source S 2 of low side MOSFET then connects ground wire (Gnd) end.Usually, between the Vin-Gnd two ends of this power switching device, be also arranged in parallel a bypass circuit electric capacity C, the setting of this electric capacity is the impulse in order to voltage when suppressing power switch starts, to promote the performance of this power switching device.Further, as shown in Figure 2, be connected in parallel a power controller (PowerIntegratedCircuit, PIC) at the two ends of the grid G 1 of high-end MOSFET and the grid G 2 of low side MOSFET, then form a DC-to-DC (DC-DC) transducer.
In current semiconductor packaging, dc-dc encapsulating structure constantly by each components and parts integration packaging, thus makes this semiconductor packages move towards microminiaturized.Therefore, on semiconductor, the density of components and parts also constantly increases thereupon, thus electromagnetic interference between components and parts is increased, and system radiating is badly in need of improving.
Summary of the invention
The embodiment of the present invention provides a kind of novel system level to encapsulate, and to realize shield electromagnetic interference, improves system radiating efficiency simultaneously.
Embodiments provide the encapsulation of a kind of novel system level, this encapsulation comprises:
Substrate, for carrying the components and parts in encapsulating structure;
MOSFET chip, is arranged on substrate surface, and bottom it, high-end drain electrode is electrically connected with Input voltage terminal by substrate wiring;
The first metal end, one end of described the first metal end is connected with substrate circuit, and the other end is arranged on high-end MOSFET chip surface, for connecting the high-end source electrode of high-end MOSFET chip;
Low side MOSFET chip, is arranged at the first metal end sub-surface, and the bottom of low side MOSFET chip is low side drain electrode, and described low side drain electrode is contacted with the high-end source electrode at high-end MOSFET chip top by the first metal end;
Broken line type sheet metal, the horizontal end of described broken line type sheet metal includes the second metal terminal, and the second metal terminal connects low side MOSFET chip top low side source electrode, and perpendicular end is electrically connected with substrate ground terminal;
IC chip, is arranged at substrate surface, is connected respectively, controls for power by substrate circuit with the grid of high-end MOSFET chip with low side MOSFET chip;
At least one passive device, for being arranged on the relevant position of broken line type sheet metal both sides substrate circuit according to the corresponding demand of circuit, forms complete DC-DC power switching circuitry.
Further, described broken line type sheet metal is T-shaped sheet metal.
Further, the horizontal end of described T-shaped sheet metal is by the surface coverage containing components and parts direction of whole encapsulating structure.
Further, described broken line type sheet metal is L-type sheet metal.
Further, described encapsulation also comprises: rectangular metal plate, covers the top of inductance component in circuit.
Further, described IC chip uses lead key closing process to be connected with substrate circuit.
Further, described IC chip uses controlled collapsible chip connec-tion to be connected with substrate circuit.
Further, described IC chip is connected by Metal Ball with substrate circuit.
Further, described MOSFET chip uses superposition mould process to be arranged on substrate.
The present invention, by the passive device in encapsulated circuit is arranged on broken line type sheet metal both sides, realizes the protection of broken line type sheet metal to the electromagnetic interference of passive device.Meanwhile, IC chip is arranged on substrate by Metal Ball upside-down mounting, forms the shortest circuit, lowers resistance.Two MOSFET chips use superposition mould process are stacking and are arranged on substrate, decrease the size of this system in package.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of power switching device in prior art;
Fig. 2 is the circuit diagram of the dc-dc in the embodiment of the present invention;
Fig. 3 A is the vertical view of a kind of novel system encapsulating structure in the embodiment of the present invention one; Fig. 3 B is the encapsulating structure planing surface figure along the A-A direction in Fig. 3 A; Fig. 3 C is the encapsulating structure planing surface figure along the B-B direction in Fig. 3 A;
Fig. 4 A is the vertical view of a kind of novel system encapsulating structure in the embodiment of the present invention two; Fig. 4 B is the encapsulating structure planing surface figure along the A-A direction in Fig. 4 A; Fig. 4 C is the encapsulating structure planing surface figure along the B-B direction in Fig. 4 A.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, illustrate only part related to the present invention in accompanying drawing but not entire infrastructure.
Embodiment one
Fig. 3 A is the vertical view of a kind of novel system encapsulating structure in the embodiment of the present invention one, system in package in the present embodiment is applicable to dc-dc, and this system in package comprises: substrate 1, high-end MOSFET chip 2, the first metal end 3, low side MOSFET chip 6, broken line type sheet metal 7, IC chip 10 and at least one passive device 8.
Wherein, substrate 1 is the substrate with being printed with circuit, and this substrate can be printed substrate, also can be a substrate being covered with lead frame.
High-end MOSFET chip 2, is arranged on substrate 1, and bottom it, high-end drain electrode is electrically connected with Input voltage terminal by substrate wiring.This high-end MOSFET chip 2 has multiple with the connected mode of substrate 1, can be connected with substrate 1 by plain conductor 4, also can be fixed by conducting resinl 5 and be electrically connected.The connected mode of components and parts and substrate circuit in the present embodiment, preferably when wanted link is positioned at the top of substrate 1 end to be connected, selects conducting resinl 5 to connect; Otherwise, select plain conductor 4 to connect.
The first metal end 3, be arranged on high-end MOSFET chip 2 and show, one end is connected with substrate circuit, and the other end is arranged on high-end MOSFET chip 2 surface, for connecting the high-end source electrode of high-end MOSFET chip 2.This first metal end 3 can be arbitrary shape, is preferably L-type, and one end that wherein L-type the first metal end is shorter can be connected with substrate circuit by conducting resinl 5, and longer one end can be electrically connected by conducting resinl 5 and high-end MOSFET chip 2.
Low side MOSFET chip 6 is arranged on the first terminal 3 surface, and the bottom of low side MOSFET chip 6 is low side drain electrode, and described low side drain electrode is contacted with the high-end source electrode at high-end MOSFET chip 2 top by the first metal end 3.This low side MOSFET chip 6 can be any-mode with the connected mode of high-end MOSFET chip 2, such as can be connected by wire level, the present embodiment is preferably low side MOSFET chip 6 and is arranged on high-end MOSFET chip 2 by the first metal end 3 is stacking, thus reduces semiconductor package size.
Broken line type sheet metal 7, the horizontal end of described broken line type sheet metal 7 includes the second metal terminal 9, second metal terminal 9 and connects low side MOSFET chip 6 top low side source electrode, and perpendicular end is electrically connected with substrate ground wire.The shape of this broken line type sheet metal 9 can be the various shapes such as arc, and the present embodiment is preferably T-shaped, and the horizontal end of this T-shaped sheet metal can by the surface coverage containing components and parts direction of whole encapsulating structure.Make the passive device being arranged on these T-shaped sheet metal both sides not by the impact of electromagnetic interference, this encapsulation simultaneously can improve radiating efficiency by the horizontal end of the T-shaped sheet metal of its surface coverage.
IC chip 10, is arranged at substrate surface, is connected respectively, controls for power by substrate circuit with the grid of high-end MOSFET chip 2 with low side MOSFET chip 6.Wherein, this IC chip 10 is arranged at substrate 1 surface based fashion, and lead key closing process can be used to be connected with substrate circuit, and controlled collapsible chip connec-tion can also be used to be connected with substrate circuit.For forming the shortest circuit, reduce resistance, the present embodiment utilizes controlled collapsible chip connec-tion to realize the connection of IC chip 10 and substrate circuit preferably through Metal Ball 11, and this Metal Ball 11 can be achieved a fixed connection by conducting resinl 5 with the connecting portion of substrate circuit and IC chip 10.
At least one passive device 8, for being arranged on the relevant position of substrate circuit according to the corresponding demand of circuit, forms complete DC-DC power switching circuitry.Wherein, for avoiding passive device 8 not by the impact of electromagnetic interference, this one or more passive device 8 is preferably arranged on the both sides of the perpendicular end of T-shaped sheet metal 7 by the present embodiment.
The operation principle of this kind of novel system encapsulating structure: the high-end drain electrode in bottom arranging high-end MOSFET chip 2 on substrate 1, is electrically connected with Input voltage terminal by substrate wiring.Low side MOSFET chip 6, is arranged on high-end MOSFET chip 2 by the first metal end 3 is stacking, and the bottom low side drain electrode of low side MOSFET chip 6 is contacted with the high-end source electrode at high-end MOSFET chip 2 top by the first metal end 3.Low side MOSFET chip 6 top low side source electrode, is electrically connected by the perpendicular end of T-shaped sheet metal 7 and substrate ground terminal and forms path.For realizing the control of power, IC chip 10, is utilized Metal Ball 11 upside-down mounting to be arranged at substrate 1 surface, is connected respectively by substrate circuit with the grid of high-end MOSFET chip 2 with low side MOSFET chip 6.For the impulse of voltage when suppressing power switch starts, circuit also adds the passive devices 8 such as one or more electric capacity and inductance, is arranged at the both sides of the perpendicular end of T-shaped sheet metal 7.Thus form complete DC-DC power commutation circuit.
The technical scheme of the present embodiment, by at least one passive device is arranged on the both sides that T-shaped sheet metal erects end, and the horizontal end of T-shaped sheet metal is by the surface coverage containing components and parts direction of whole encapsulating structure, shield electromagnetic interference to the impact having no chance device, and the horizontal end of T-shaped sheet metal improves the radiating efficiency of this system in package.Meanwhile, IC chip is arranged on substrate by Metal Ball upside-down mounting, forms the shortest circuit, lowers resistance.Two MOSFET chips use superposition mould process are stacking and are arranged on substrate, decrease the size of this system in package.
Embodiment two
Fig. 4 A is the vertical view of a kind of novel system encapsulating structure in the embodiment of the present invention two, and T-shaped sheet metal, on the basis of the system seal structure described in embodiment one, is replaced with L-type sheet metal and rectangular metal plate by the present embodiment.This system in package is applicable to DC-to-DC converter, and this system in package comprises: substrate 1, high-end MOSFET chip 2, the first metal end 3, low side MOSFET chip 6, L-type sheet metal 12, rectangular metal plate 13, IC chip 10 and at least one passive device 8.
Wherein, L-type sheet metal 12 is for there being type conducting metal, and the ground terminal of this conducting metal one end connection substrate circuit, the other end connects low side MOSFET chip 6 top low side source electrode.This conducting metal can be any broken line shape, be preferably L-type, one end that wherein L-type the first metal end is shorter can be connected with the ground terminal of substrate circuit by conducting resinl 5, and longer one end can be electrically connected by the top low side source electrode of conducting resinl 5 with low side MOSFET chip 6.
For protection passive device 8 is not by the impact of electromagnetic interference, increase the top that rectangular metal plate 13 covers on this passive device 8, for the impact of shield electromagnetic interference.
The technical scheme of the present embodiment, by rectangular metal plate being covered on the top of passive device, shield electromagnetic interference to the impact having no chance device, and the horizontal end of L-type sheet metal improves the radiating efficiency of MOSFET chip in this system in package.Meanwhile, IC chip is arranged on substrate by Metal Ball upside-down mounting, forms the shortest circuit, lowers resistance.Two MOSFET chips use superposition mould process are stacking and are arranged on substrate, decrease the size of this system in package.
Note, above are only preferred embodiment of the present invention and institute's application technology principle.Skilled person in the art will appreciate that and the invention is not restricted to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute and can not protection scope of the present invention be departed from.Therefore, although be described in further detail invention has been by above embodiment, the present invention is not limited only to above embodiment, when not departing from the present invention's design, can also comprise other Equivalent embodiments more, and scope of the present invention is determined by appended right.
Claims (9)
1. a novel system level encapsulation, is characterized in that, comprising:
Substrate, for carrying the components and parts in encapsulating structure;
High-end mos field effect transistor MOSFET chip, is arranged on substrate surface, and bottom it, high-end drain electrode is electrically connected with Input voltage terminal by substrate wiring;
The first metal end, one end of described the first metal end is connected with substrate circuit, and the other end is arranged on high-end MOSFET chip surface, for connecting the high-end source electrode of high-end MOSFET chip;
Low side MOSFET chip, is arranged at the first metal end sub-surface, and the bottom of low side MOSFET chip is low side drain electrode, and described low side drain electrode is contacted with the high-end source electrode at high-end MOSFET chip top by the first metal end;
Broken line type sheet metal, the horizontal end of described broken line type sheet metal includes the second metal terminal, and the second metal terminal connects low side MOSFET chip top low side source electrode, and perpendicular end is electrically connected with substrate ground terminal;
IC chip, is arranged at substrate surface, is connected respectively, controls for power by substrate circuit with the grid of high-end MOSFET chip with low side MOSFET chip;
At least one passive device, for being arranged on the relevant position of broken line type sheet metal both sides substrate circuit according to the corresponding demand of circuit, forms complete DC-to-DC DC-DC power switching circuitry.
2. novel system level encapsulation according to claim 1, is characterized in that:
Described broken line type sheet metal is T-shaped sheet metal, has the function of the electromagnetic interference of protection passive device, and to the whole function being packaged with heat radiation.
3. novel system level encapsulation according to claim 2, is characterized in that:
The horizontal end of described T-shaped sheet metal is by the surface coverage containing components and parts direction of whole encapsulating structure.
4. novel system level encapsulation according to claim 1, is characterized in that:
Described broken line type sheet metal is L-type sheet metal.
5. novel system level encapsulation according to claim 4, is characterized in that, also comprise:
Rectangular metal plate, covers the top of inductance component in circuit.
6. novel system level encapsulation according to claim 1, is characterized in that:
Described IC chip uses lead key closing process to be connected with substrate circuit.
7. novel system level encapsulation according to claim 1, is characterized in that:
Described IC chip uses controlled collapsible chip connec-tion to be connected with substrate circuit.
8. novel system level encapsulation according to claim 7, is characterized in that:
Described IC chip is connected by Metal Ball with substrate circuit.
9. novel system level encapsulation according to claim 1, is characterized in that:
Described MOSFET chip uses superposition mould process to be arranged on substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510633468.9A CN105355606B (en) | 2015-09-28 | 2015-09-28 | A kind of novel system grade encapsulation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510633468.9A CN105355606B (en) | 2015-09-28 | 2015-09-28 | A kind of novel system grade encapsulation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105355606A true CN105355606A (en) | 2016-02-24 |
| CN105355606B CN105355606B (en) | 2019-05-28 |
Family
ID=55331545
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510633468.9A Active CN105355606B (en) | 2015-09-28 | 2015-09-28 | A kind of novel system grade encapsulation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105355606B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101419964A (en) * | 2007-10-26 | 2009-04-29 | 英飞凌科技股份公司 | Device with a plurality of semiconductor chips |
| US20120064667A1 (en) * | 2006-04-24 | 2012-03-15 | Rajeev Joshi | Semiconductor die package including multiple dies and a common node structure |
| CN102468292A (en) * | 2010-10-29 | 2012-05-23 | 万国半导体股份有限公司 | Packaging body structure for direct current-direct current convertor |
| EP2525401A2 (en) * | 2011-05-19 | 2012-11-21 | International Rectifier Corporation | Common drain exposed conductive clip for high power semiconductor packages |
| CN103515370A (en) * | 2012-06-21 | 2014-01-15 | 尼克森微电子股份有限公司 | Power semiconductor package and manufacturing method thereof |
-
2015
- 2015-09-28 CN CN201510633468.9A patent/CN105355606B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120064667A1 (en) * | 2006-04-24 | 2012-03-15 | Rajeev Joshi | Semiconductor die package including multiple dies and a common node structure |
| CN101419964A (en) * | 2007-10-26 | 2009-04-29 | 英飞凌科技股份公司 | Device with a plurality of semiconductor chips |
| CN102468292A (en) * | 2010-10-29 | 2012-05-23 | 万国半导体股份有限公司 | Packaging body structure for direct current-direct current convertor |
| EP2525401A2 (en) * | 2011-05-19 | 2012-11-21 | International Rectifier Corporation | Common drain exposed conductive clip for high power semiconductor packages |
| CN103515370A (en) * | 2012-06-21 | 2014-01-15 | 尼克森微电子股份有限公司 | Power semiconductor package and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105355606B (en) | 2019-05-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105981274B (en) | Semiconductor module for electric power | |
| CN101656250B (en) | Compact co-packaged semiconductor dies with elevation-adaptive interconnection plates | |
| US9853378B2 (en) | Substrate and terminals for power module and power module including the same | |
| CN102709282B (en) | Multi-chip packaging structure, converter module and packaging method | |
| US8148815B2 (en) | Stacked field effect transistor configurations | |
| CN103782380B (en) | semiconductor module | |
| CN109713890B (en) | Power modules with electromagnetic interference (EMI) shielding, cooling, or both shielding and cooling along two or more sides | |
| US8735957B2 (en) | Vertical MOSFET transistor with a vertical capacitor region | |
| US20140063744A1 (en) | Vertically Stacked Power FETS and Synchronous Buck Converter Having Low On-Resistance | |
| US9136207B2 (en) | Chip packaging structure of a plurality of assemblies | |
| US10134718B2 (en) | Power semiconductor module | |
| TWI512937B (en) | Flip - mounted package for integrated switching power supply and its flip - chip packaging method | |
| CN202042483U (en) | Package structure of power semiconductor device | |
| CN102468292B (en) | Packaging body structure for direct current-direct current convertor | |
| CN102760724A (en) | Integrally-packaged power semiconductor device | |
| CN107026575A (en) | Storehouse electronic structure | |
| CN104752389A (en) | Mosfet Pair With Stack Capacitor And Manufacturing Method Thereof | |
| US9054088B2 (en) | Multi-component chip packaging structure | |
| US20170213783A1 (en) | Multi-chip semiconductor power package | |
| US20120068681A1 (en) | Integrated Circuit Package With Reduced Parasitic Loop Inductance | |
| JP2017123358A (en) | Power module | |
| CN107492531B (en) | Semiconductor device with a plurality of semiconductor chips | |
| WO2014192348A1 (en) | Semiconductor device | |
| CN109841598B (en) | Multiphase half-bridge driver package and method of manufacture | |
| WO2018007062A1 (en) | Low-inductance power module design |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |