CN1053335A - Variable long code sequential decoding method and programmable circuit thereof - Google Patents

Abstract

The invention provides a kind of variable long code sequential decoding method and programmable circuit thereof, it is ordered list relevant with code word of structure in a variable length code system, in decode procedure, regarding a number as with the code-element string headed by the word to be decoded in the code stream, by the size order between the element of determining ordered set in itself and the ordered list concern discern decoded.The present invention directly discerns whole codeword and deciphers, and has been completely free of the damp code method of discerning code element one by one, thereby can improve decoding speed significantly.

Description

Variable long code sequential decoding method and programmable circuit thereof

The present invention relates to a kind of variable length code interpretation method and programmable circuit thereof.

The modern data communication technology is the essential a kind of instrument of informationized society, and people are also more and more higher to the requirement of communications speed.Source encoding can improve communications speed by data compression coding, thereby be widely used in the communications fields such as voice, image, literal, data, this code that is used for the source encoding of data compression purpose is a variable length code, decoding for variable length code will improve its decoding speed, at first must improve the speed of identification avriable length codes.The variable length code decoding method that extensively adopts both at home and abroad mostly is based on tree-like search decoding method at present, in the recent period, disclosing a kind of publication number in China's " Gazette of Patent for Invention " is CN1043413A, denomination of invention is the invention of " universal encode and decode method with variable length code and programmable circuit ", wherein also relates to relatively decoding method of a kind of variable length code.The decoding method of above-mentioned these variable length codes all needs the code element in the code stream discerned one by one and deciphers, and has therefore limited the raising of decoding speed, is difficult to satisfy the more requirement of high-speed data communication.

In order to overcome above-mentioned deficiency, the purpose of this invention is to provide a kind of variable long code sequential decoding method and programmable circuit thereof, it is directly whole codeword to be discerned to decipher, and has been completely free of the interpretation method of discerning code element in the prior art one by one, thereby can have improved decoding speed significantly.The present invention is applied widely, and algorithm is simple, realizes flexibly easily with circuit, is suitable for making general programmable variable length code decoder ic, with software or soft, hardware combine realize then having programming simple, flexibly, advantage such as average operating instruction number is few.

The objective of the invention is to realize by following technical proposals.

For a variable length code system, construct an ordered list relevant with code word, in decode procedure, regarding a number as with the code-element string headed by the word to be decoded in the code stream, by the size order between the element of determining an ordered set in itself and the ordered list concern discern decoded.Ordered list is to constitute like this: add the identical figure place l of several zero formations after each code word _mPosition (l _mBe not less than maximum code length) number, again these are counted by () order rearranges an ordered set or from big to small from small to large, then each message elements and code length are arranged according to the order of elements in the pairing ordered set, this has just constituted ordered list.The code word identifying is: get l from the stem of stream to be decoded _mIndividual code element is as a l _mFigure place, which determine to be inserted in when the ordered set merging of inserting in the ordered list makes this set still orderly after the element (or before if will count, unactual the insertion), the pairing code of this element first code that is exactly stream to be decoded then, leave out the code element that is translated sign indicating number from stream stem to be decoded then, the residue code stream as a new stream to be decoded, is repeated said process, can translate second, the 3rd sign indicating number or the like, till stream to be decoded has all been translated.Above-mentioned sequential decoding method can be realized by a kind of programmable circuit Fig. 8, as shown in Figure 8, this circuit is made up of deletion circuit 1, sign indicating number space identification circuit 2, control circuit 5 and memory, and memory is made up of message elements memory 3 and code length memory 4.The deletion circuit is l before having deletion stream stem to be decoded and having been translated the code element of sign indicating number and taken out residue stream to be decoded _mThe circuit of the function of individual code element, code word identification circuit are exactly the circuit with identification code word function, and memory is used for storing message elements (or message elements address) and code length, and control circuit is then coordinated the course of work between the each several part circuit.Stream to be decoded is with l _mIndividual code element is one group of parallel input deletion circuit, and the deletion circuit is with the preceding l of stream to be decoded _mIndividual code element is parallel exports to the code word identification circuit, and the code word identification circuit identifies this l _mBehind first sign indicating number of individual code element, address in memory inputs to memory with corresponding message elements and code length, and corresponding message elements is just from memory output, and corresponding code length is feeding deletion circuit then, after the deletion circuit is finished deletion action, will remain the preceding l of stream to be decoded again _mIndividual code element is sent into the code word identification circuit, proceeds decoding, the residue no more than l of unit to be decoded in the deletion circuit _mWhen individual, just from stream to be decoded, be taken into next group l _mIndividual code element is replenished.

Below will the present invention is described in further detail by specific embodiment.Be provided with information source X,

X wherein ₁, x ₂..., x _nThe message elements of expression information source, P (x) are the probability that x occurs, glossary of symbols S={s ₁, s ₂..., s _R, s wherein ₁, s ₂..., S _RIt is the symbol that is used for constituting code.Usually S is made of multi-system R (R 〉=2) system numeral, and correspondingly is called as R system source encoding.S={0 in binary source coding for example, 1}, S={0 in the ternary source encoding, 1,2} or the like.But, element " 0, " must be arranged in S and suppose S _RIt is greatest member wherein.Under the situation of given R, use certain encryption algorithm (for example huffman coding method, Shannon compiling method or the like), find out the code of each message elements, constitute code set C={c ₁, c ₂..., c _n, wherein each code c by several digital " numeric strings " different in size of forming of R system among the S, is variable length code, and satisfies the prefix coee condition, in other words, has non-lengthened code characteristic.Suppose that Fig. 1 represents the mapping table of message elements collection X and code set C, as shown in Figure 1,, construct ordered list earlier in order to decipher.

If l _Max=max{l ₁, l ₂, l _n, get and satisfy l _m〉=l _MaxA l _m, construction set D={d ₁, d ₂, d _n, element d wherein _iWith code c _iCorresponding relation be: for code $c_i={b_1}^{\left(i\right)}{b_2}^{\left(i\right)}\·\·\·{b_{l_i}}^{\left(i\right)},$ B wherein _j ⁽ⁱ⁾∈ S (claims b _j ⁽ⁱ⁾Be code element), j=1,2 ... l _i(1), has I=1,2 ... n (2).

Because for different code c, the numeric string difference on formula (1) the right, and have non-lengthened code characteristic, so the element d among the set D is regarded as l _mWhen position R system was counted, each element was unequal mutually.In view of the above, can obtain ordered set D={d ' with element among the D by (or from big to small, their decoding principle is identical, below be example with sequence arrangement from small to large) sequence arrangement from small to large ₁, d ' ₂..., d ' _n, d ' wherein _i∈ D, i=1,2 ..., n, and d ' _i＜d ' _j, for i＜j, i, j ∈ 1,2. ..., n} (3) is the ordered list of a decoding usefulness of base configuration with ordered set D ' then, Fig. 2 is the ordered list that is used for variable length code decoding, as shown in Figure 2, code set C '=C ' ₁, C ' ₂..., C ' _nCode among the code set C rearranges by the order of pairing d ' and obtains, in like manner, corresponding message elements and corresponding code length also use the same method and obtain.

Utilize this ordered list, the sequential decoding method of variable length code is as follows: owing to the code stream of representing message elements is not add continuous arrangement of any space character by the code in the code collection to constitute, and each code all is a R system numeric string, so connecing the code stream (stream to be decoded) of the message first of herding is a code string, also be time-limited R system numeric string, can be expressed as

W=b ₁b ₂B _p, b wherein _{I ∈ S}, i=1,2 ..., p (4) w can and can only be split into a series of codes in the code collection, and to cut apart be unique.

Its decoding step is:

The-step: get the preceding l among the stream w to be decoded _mIndividual code element is as a l _mPosition R system number $w^{\&prime;}=b_1,{\mathrm{<figure-callout\; id="2"\; label="b"\; filenames="9010893100201.png"\; state="\{\{state\}\}">b</figure-callout>}}_2\&CenterDot;\&CenterDot;\&CenterDot;b_{l_m},$ Some positions must constitute certain code c before it ".

Second step: judge w ' 〉=d ' _nC whether sets up, if then " must be d ' _nPairing code c ' _nIf not, then at the middle searching i of ordered set D ', make d ' _i≤ w '＜d ' _I+1Set up (must find), can determine c " must be d ' _iPairing code c ' _i

Below confirm the correctness of above-mentioned judgement, before this, earlier these two characteristics are proved with two characteristics.

(characteristic 1): in ordered set D ', any given element d ' _i, can in set D, find an identical with it element d _j(because D ' has identical element with D, and being one to one) is for satisfying condition J=1,2 ..., the l of n-1 _mPosition R system is counted α, has

α＜d ' _k, for k＞i, k ∈ 2,3 ..., n} proves: use reduction to absurdity.Suppose α 〉=d ' _k, then

Again because k＞i knows d ' by formula (3) _k＞d ' _iSo, $d_k^{\&prime;}>d_i^{\&prime;}=d_j={b_1}^{\left(j\right)}{b_2}^{\left(j\right)}\&CenterDot;\&CenterDot;\&CenterDot;{b_{l_j}}^{\left(j\right)}00\&CenterDot;\&CenterDot;\&CenterDot;0---\left(6\right)$ (l _m-l _i) position establishes d ' _k=d _g, then $d_k^{\&prime;}={b_1}^{\left(g\right)}{b_2}^{\left(g\right)}\&CenterDot;\&CenterDot;\&CenterDot;{b_{l_g}}^{\left(g\right)}00\&CenterDot;\&CenterDot;\&CenterDot;0$ Wherein ${b_1}^{\left(g\right)}{b_2}^{\left(g\right)}\&CenterDot;\&CenterDot;\&CenterDot;{g_{l_g}}^{\left(g\right)}=c_g---\left(7\right)$ (l _m-l _g) position can know d ' by inference by formula (5) and formula (6) _kPreceding l _iThe position must for ${b_1}^{\left(j\right)}{b_2}^{\left(j\right)}\&CenterDot;\&CenterDot;\&CenterDot;{b_{l_j}}^{\left(j\right)},$ Be code word c _jContrast formula (7) can be known by inference, if l _g=l _j, c then _gWith c _jIdentical, so d ' _k=d ' _i, with formula (3) contradiction; If l _g＞l _i, c then _gBecome c _iProlongation, perhaps l _g＜l _i, c then _jBecome c _gProlongation.Equal non-lengthened code characteristic contradiction that has with former code set.So α 〉=d ' _kHypothesis be false." characteristic 1 " proposition is correct, and card is finished.

[characteristic 2] establishes u is at a certain code c _iThe back increases several R system numerals arbitrarily and extends to length overall is l _mThe R system number of position, so:

(1) if u＜d ' _k, c then _jCan not be d ' _kOr among the D ' than d ' _kThe pairing code of big element;

(2) if u 〉=d ' _k, c then _iCan not be than d ' among the D ' _kThe pairing code of little element.Proof: according to above-mentioned hypothesis, u can be expressed as

Wherein ${b_1}^{\left(i\right)}{b_2}^{\left(i\right)}\&CenterDot;\&CenterDot;\&CenterDot;{b_{l_i}}^{\left(i\right)}=c_i,b_{j\&Element;S},$ j＝1，2，…，(l _m-l _i)

Still prove " characteristic 2 " assign a topic it (1) and (2) with reduction to absurdity.

(1) supposes c _iBe d ' _kOr among the D ' than d ' _kThe pairing code of big element obviously has This and (1) middle condition u＜d ' _kContradiction is so hypothesis is false." characteristic 2 " assigns a topic it (1) correctly.

(2) suppose c _iBe than d ' among the D ' _kThe pairing code of little element, again because

According to " characteristic 1 " u＜d ' is arranged _k, this and (2) middle condition u 〉=d ' _kContradiction, so hypothesis is false, " characteristic 2 " assigns a topic they (2) correctly, card is finished.

Judicious foundation in decoding step the second step is described now.

If w ' 〉=d ' _n, assigning a topic they (2) according to " characteristic 2 ", C " can not be than d ' among the D ' _nSo the pairing code of little element is C " must be d ' _nPairing code c ' n; If d ' _i≤ w '＜d ' _I+1, assigning a topic it (1) according to " characteristic 2 ", C " can not be d ' _I+1Or among the D ' than d ' _I+1The pairing code of big element, assigning a topic they (2) C according to " characteristic 2 " " also can not be to compare d among the D ' _iSo the pairing code of little element is C " must be d ' _iPairing code c ' _i

Therefore the judgement of deciphering step the second step is correct.

The 3rd step: judged C " is pairing code C ' of definite d ' among the ordered set D ', has translated first sign indicating number exactly; Corresponding message elements x ' is exported in a suitable manner (or storage), then preceding l ' (C ' the code length) position that constitutes C ' in the formula (4) is left out, regard the residue code stream as a new code string or numeric string w, forward the first step to, proceed decoding, till whole code stream w has been translated.

Enforcement the present invention relates to second step that a key factor that sequential decoding method improves decoding speed significantly is to carry out fast the decoding step, from the data structure viewpoint, decoding step the second step be equivalent to determine with a given new element insert one orderly linear and tabulate and make the still orderly insertion position of this table (unactual insertion), therefore can utilize the various quick insertion algorithm of ordered list such as binary chop insertion algorithm, segmentation arithmetic progression method, hash address method etc., determine code fast.Below the application of wherein several quick insertion algorithms in sequential decoding method is described with a concrete variable length code system.

If Fig. 3 is message elements and a code word correspondence table in the concrete binary system variable length code system.Press Fig. 2 form, the ordered list Fig. 4 that is configured to decipher, wherein l _mGetting 8 is to handle also desirable l when realizing with hardware for the ease of 8 bit machines _m=6, message elements x among Fig. 4 _iCan store message elements itself or message elements address with digital form.

Method one: binary chop insertion algorithm.

Directly adopt Fig. 4, determine to be inserted in after which element with well-known binary chop insertion algorithm if 8 bits that preceding 8 code elements in the stream to be decoded are formed are inserted with ordered sets D ' time, can determine code by decoding step 2 again, at this moment need store ordered set D ' among Fig. 4, corresponding message elements and three groups of data of corresponding code length, when the total number of code is n, discerns a sign indicating number and need search for [log at most ₂N]+2 ((A) expression get the maximum integer that is not more than A) are inferior, when maximum code length the big and total number of code word more for a long time, the raising of decoding speed is comparatively remarkable.An advantage of binary chop insertion algorithm is that committed memory is few.

Method two: segmentation arithmetic progression method.

Element among the ordered set D ' among Fig. 4 is expanded to the segmentation arithmetic progression as shown in Figure 5 and Figure 6, Fig. 5 is the ordered list that is used for segmentation arithmetic progression method, Fig. 6 is a segmentation first address indicator index table, the pairing message elements of the element that increases among Fig. 5 and code length are with more consistent than its little and the most close pairing message elements of existing element and code length, utilize segmentation arithmetic progression method, need among storage Fig. 5 segmented index address pointer and four groups of data of tolerance in the message elements and code length and Fig. 6.Preceding 8 code elements in getting stream to be decoded are as one 8 bit w ' time, and the code identification step is as follows:

(1) get w ' preceding 4 as a binary number w ₁, with w ₁For sequence number is got segmented index address pointer w among Fig. 6 ₂, judge corresponding tolerance w ₃Whether be zero, if, then among the w ' first sign indicating number be exactly among Fig. 5 sequence number be w ₂Code, its corresponding message elements and code length are also corresponding to be found.

(2) if not, get among the w ' back 4 as a binary number, divided by tolerance w ₃, obtain discussing w ₄(remainder is given up), then among the w ' first sign indicating number be exactly among Fig. 5 sequence number for (w ₂+ w ₄) code, its corresponding message elements and code length are also corresponding to be found.

The advantage of utilizing segmentation arithmetic progression method is need not search for, as long as judge and step calculating can be determined decodedly that shared internal memory is also few through a step.

Method three: hash address method.

This is a kind of method of determining code with hash address storage method.Element among the ordered set D ' among Fig. 4 is expanded and stored by the hash address, Fig. 7 is the ordered list that is used for hash address storage method, as shown in Figure 7, the pairing message elements of element that increases is the same with situation in the method two with code length, at this moment need store message elements and two groups of data of code length by Fig. 7.Preceding 8 code elements in getting stream to be decoded are as one 8 bit w ' time, if with w ' move to right two (left side zero paddings) obtain w ₅, then first among the w ' sign indicating number be exactly among Fig. 7 sequence number be w ₅Code, its corresponding message elements and code length are also corresponding to be found.Utilizing hash address storage method is to exchange higher decoding speed for more storage capability, and it neither needs search, does not also need to calculate just can determine word to be decoded.

This shows, the sequential decoding method that the present invention relates to is by the structure ordered list relevant with code word, make and determine that decoded process is converted into the process of the size order relation of determining number, thereby can utilize the distinctive character of ordered list, adopt various quick insertion algorithms, discern whole codeword apace.

As one of means of the sequential decoding method of the variable length code of implementing the present invention relates to, Fig. 8 has provided programmable variable-length sign indicating number decoding circuit.

In the decoding circuit of Fig. 8, being stored in memory cell is fixed length l _mPosition (l _mBe not less than maximum code length) memory in grouping (promptly with l _mIndividual code element is one group) decoded stream 6, under the effect of the control signal 8 that control-signals generator 5 is sent, get the preceding some groups of successively parallel input deletion circuit 1 of stream group to be decoded, deletion circuit 1 is to finish decoding three steps of step the, promptly leaves out the code stream stem and has been translated l before the code element of sign indicating number and the output residue stream to be decoded _mA kind of circuit of individual code element, 1 state output gives 5, when the state indication when 1 need not to delete or deletion action finishes, 5 produce a control signal, output with the 1 enter code word identification circuit 2 that walks abreast, the 2nd, finish decoding step the second step, promptly discern a kind of circuit that code word and output are identified pairing message elements of sign indicating number and the address of code length in message elements memory 3 and code length memory 4 (all by the sequential storing in the ordered list), 2 state exports to 5, when the state indication when 2 identifies a code word, 5 produce a control impuls with the parallel input 3 and 4 of 2 output, 5 again output control pulse 13 trigger external circuits and receive corresponding message elements from the memory 3 of data/address bus 7 and line output, make the parallel input deletion of the corresponding code length circuit 1 in 4 simultaneously, then 1 carries out deletion action, after finding to finish deletion action, the no more than l of residue code element in 1 _mIndividual, then pulse signal of 1 output gives 5,5 just with next group l in the stream to be decoded _mThe parallel input 1 of code element is through adjusting the preceding l of 1 output residue again stream to be decoded _mIndividual code element to 2 is proceeded decoding.

Among Fig. 8 in the memory 3,4 message elements and code length data before work decoding, send into by data/address bus 7, chip selection signal 9, address signal 10, read-write 11 and clock signal 12 are all provided by external circuit.

As the necessary factor that constitutes above-mentioned programmable variable-length sign indicating number decoding circuit, Fig. 9, Figure 10 and Figure 11, Figure 12 have provided each two kinds of the implementation methods of deletion circuit 1 and code word identification circuit 2 respectively.

In the deletion circuit of Fig. 9, stream to be decoded is counted first group and second group of l from stem _mBy data/address bus 6 input shift registers 14 and 15, reset signal 20 is passed through control-signals generator 18 with l to individual code element by external control circuit _m17 zero clearings of system subtract counter, 14 content are the preceding l of stream to be decoded _mIndividual code element is exported by 6 under 18 control; The corresponding code length that is translated sign indicating number can preset (l by external control circuit by 6 inputs _m+ 1) the system subtract counter 16, enabling signal 19 is by 18, make clock signal 12 give 14,15,16 and subtract counter 17, make it to move to left or count, 15 content enters 14 when moving to left, output status signal 22 gives 18 and external circuit when 16 reduce to zero, stops displacement and counting, and 14 content is exactly the preceding l of residue stream to be decoded _mCode element is exported by 6 under 18 controls again; In displacement and counting process, if subtract counter 17 is from reducing to zero greater than zero, be that output pulse signal 21 gives 18 and external circuit, stop displacement and counting, external control circuit passes through data/address bus 6 parallel inputs 15 with next set of symbols of stream to be decoded, and restarts displacement and counting with reset signal 20.

In the deletion circuit of Figure 10, stream to be decoded is counted first group and second group of l from stem _mIndividual code element by data/address bus 6 respectively and be advanced into one by (l _m+ 1) first in the registers group 23 of individual register composition and (l _m+ 1) individual register, i in the while 23 (i=2,3 ..., l _m) individual register i position to the (l of first register _m+ 1) content of (i-1) of individual register position.The accumulator initial value is 0 in the arithmetic operation unit 24, and as selecting signal to send into 23, the content of selecting first register is under the control of control-signals generator 25 and line output; After code is identified, external control circuit by 6 with corresponding code length send into 24 with accumulator in content add up, if its result is less than l _m, then output status signal 50 is given external circuit, and to make in 23 with accumulator value in 24 be that the content of register of sequence number is from 6 and line output; If accumulation result is not less than l _m, then accumulator contents deducts l _m, and send a pulse signal to control-signals generator 25,25 with (l in 23 _m+ 1) individual content of registers is given first register, sends a pulse signal 26 to external circuit again, and external circuit is with next group l in the stream to be decoded _mCode element input (l _m+ 1) individual register will in 23 be that the content of registers of sequence number is from 6 outputs with the accumulator value again.

In the sign indicating number space identification circuit of Figure 11, the preceding l of stream to be decoded _mIndividual unit is walked abreast input registers 27 (some code elements before the storage) and 28 (storing all the other code elements) by data/address bus 34 by external circuit, 27 content outputs to segmentation first address pointer memory 29 and segmentation tolerance memory 30,28 content in divider 31 divided by 30 output (being tolerance), gained merchant and output (being first address) addition in adder 32 of 29,32 send status signal 36 to external circuit, simultaneously with addition result from data/address bus 35 and line output, the order of control-signals generator 33 control above-mentioned steps is carried out.First address and tolerance value were sent into by data/address bus 34 before work decoding in the memory 29,30.

In the code word identification circuit of Figure 12, the preceding l of stream to be decoded _mIndividual code element is passed through data/address bus 39 parallel input shift registers 37 by external circuit, control-signals generator 38 is sent control impuls and is given 37, make it to move to right some position 38 is sent status signal 40 and is given external circuit then, simultaneously with the content in 37 from data/address bus 39 and line output.

In Fig. 9, Figure 10, Figure 11, Figure 12, chip selection signal 9, address signal 10, read-write 11 and clock signal 12 provide by external circuit.

The present invention can promote the use of the decoding of any variable length code system.

Claims (10)

1. the interpretation method of a variable length code, it is characterized in that for a variable length code system, construct an ordered list relevant with code word, regarding a number as with the code-element string headed by the word to be decoded in the code stream, by determine its with ordered list in size order between the element of an ordered set concern and discern decodedly that its ordered list is to add the identical figure place l of several zero formations after each code word _mPosition (l _mBe not less than maximum code length) number, again these numbers are formed ordered set D ' by the sequence arrangement of (or from big to small) from small to large, each message elements and code length are arranged according to the order of elements among the pairing ordered set D ' constituted then.

2. variable length code decoding circuit, it is characterized in that it is by deletion circuit (1), code word identification circuit (2), message elements memory (3), code length memory (4) and control-signals generator (5) are formed, and stream packets to be decoded also is advanced into (1), (1) (2) are sent in output, (2) (3) and (4) are given in output under the control of (5), the content of (4) sends back to (1), and the content of (3) as a result of and line output.

3. interpretation method according to claim 1, it is characterized in that obtain ordered set D '=(d ' ₁, d ' ₂..., d ' _n(with from small to large the order be example) and ordered list after, the step of deciphering is as follows:

(1) gets preceding l among the stream to be decoded w _mIndividual code element is as a l _mFigure place $w^{\&prime;}=b_1{b}_2\&CenterDot;\&CenterDot;\&CenterDot;b_{l_m},$ Some positions must constitute certain code c before it ";

(2) judge w ' 〉=d ' _nWhether (D ' middle greatest member) sets up, if then c " must be d ' _nPairing code, if not, then at the middle searching i of ordered set D ', make d ' _i≤ w '＜d _I+1, set up, can determine c " must be d ' _iPairing code;

(3) having judged c " is among the ordered set D ' behind pairing code of definite d '; the corresponding message elements in the ordered list is exported in a suitable manner (or storage); leave out constituting the individual code element of preceding l ' (the corresponding code length in the ordered list) that is translated sign indicating number among the stream W to be decoded then; the residue code stream is regarded as a new stream W to be decoded; forward the first step to; proceed to decipher, till whole code stream has been translated.

4, according to claim 1 and 3 described interpretation methods, it is characterized in that in decoding step (2), utilize ordered list to adopt the binary chop insertion algorithm to discern word to be decoded.

5, according to claim 1 and 3 described interpretation methods, it is characterized in that in decoding step (2), utilize ordered list to adopt segmentation arithmetic progression method to discern word to be decoded.

6, according to claim 1 and 3 described interpretation methods, it is characterized in that in decoding step (2), utilize ordered list to adopt and discern word to be decoded by hash address storage method.

7, decoding circuit according to claim 2, it is characterized in that deleting circuit (1) is by shift register (14) and (15), can preset subtract counter (16), subtract counter (17) and control-signals generator (18) are formed, stream packets to be decoded also is advanced into (14) and (15), and the content of (14) as a result of and line output; Translated parallel enter (16) of corresponding code length of sign indicating number, under the control of (18), (15) content serial moves into (14), make (16) and (17) counting simultaneously, (16) output control (18) produces control signal, the content that makes (14) as a result of and line output, the output control (18) of (17) produces control signal, makes next set of symbols of stream to be decoded and is advanced into (15).

8, decoding circuit according to claim 2, it is characterized in that deleting circuit (1) is to comprise (l by one _m+ 1) registers group of individual register (23) and having adds, the arithmetic operation unit (24) and the control-signals generator (25) of subtraction and comparing function form, stream packets to be decoded also is advanced into (23), parallel send into (24) of corresponding code length of sign indicating number have been translated, (24) (23) are sent in a output, to select a content of registers in (23) as line output also; (24) another output triggers (25) and produces control signal, makes next set of symbols of stream to be decoded and is advanced into (23).

9, decoding circuit according to claim 2, it is characterized in that code word identification circuit (2) is by register (27) and (28), the segmentation first address pointer memory (29) of segmentation arithmetic progression, segmentation tolerance memory (30), divider (31), the circuit that adder (32) and control-signals generator (33) are formed with segmentation arithmetic progression method identification code word, the preceding l of stream to be decoded _mTwo parts were parallel before and after individual code element was divided into enters (27) and (28) respectively, and the content of (27) outputs to (29) and (30), and the content of (28) is the output divided by (30) in (31), its merchant output addition with (29) in (32), its result and line output.

10, decoding circuit according to claim 2 is characterized in that code word identification circuit (2) is made up of shift register (37) and control-signals generator (38), with the circuit of hash address storage method identification code word, the preceding l of stream to be decoded _mIndividual code element also is advanced into (37), and the output of (38) control (37) is shifted, and the content of (37) as a result of and line output then.

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