CN105322918A - Method for reducing power consumption of power-on process - Google Patents
Method for reducing power consumption of power-on process Download PDFInfo
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- CN105322918A CN105322918A CN201510685354.9A CN201510685354A CN105322918A CN 105322918 A CN105322918 A CN 105322918A CN 201510685354 A CN201510685354 A CN 201510685354A CN 105322918 A CN105322918 A CN 105322918A
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Abstract
The invention discloses a method for reducing power consumption of a power-on process. The method comprises the following steps of defaulting an inner low-speed clock to a clock of a waiting time counter in a reset process after hardware reset is completed; when the waiting time counter counts to a certain time, opening an inner high-speed crystal oscillator and reading a waiting time parameter of a program area; after parameter reading is completed, closing the inner high-speed crystal oscillator; and finishing the waiting time, completing reset of a digital circuit and entering a normal working condition. By adopting a scheme for counting the waiting time based on the low-speed clock, controlling opening of the high-speed crystal oscillator and reading the storage parameter of the program area, the working time of the high-speed crystal oscillator can be effectively controlled to achieve a purpose of reducing the power consumption of a reset process finally.
Description
Technical field
The invention belongs to the technical field of single-chip microcomputer, particularly a kind of method of electrical power consumed on single-chip microcomputer.
Background technology
Along with processing speed is more and more faster, clock frequency significantly improves; On the other hand, single-chip microcomputer, in power up, needs to carry out some configuration and adjustment, therefore needs to wait for regular hour just completing circuit reset, enters normal mode of operation; 3rd, according to different application scenarioss, need the time difference waited for, need certain position that is in advance stored in memory space the stand-by period, reseting procedure will read out in advance waiting time.In reseting procedure, a direct-open inner high speed clock will bring very large power wastage, especially high to power consumption requirements application, such as: wearable device, and the equipment etc. of frequent switching on and shutting down.
Patent application 200610073411.9 discloses a kind of electrify restoration circuit, this application is a kind of particularly suitable with the electrify restoration circuit in the Circuits System of clock oscillator, it comprises switched-capacitor circuit, unidirected discharge device and squaring circuit, and wherein switched-capacitor circuit receives the clock signal exported by clock oscillator.Electrify restoration circuit provided by the present invention utilizes the clock oscillator in Circuits System, by using switched-capacitor circuit, in the various state change processes of system, all creates reliable power-on reset signal, has dependable performance, advantage that power consumption is lower.But this patent application utilizes clock oscillator to produce power-on reset signal, the clock for internal system does not improve, and in power up, uses inner high speed crystal oscillator to carry out time counting always, still there is the power wastage problem of high frequency clock.
Summary of the invention
For solving the problem, the object of the present invention is to provide a kind of method reducing power up power consumption, the method suitably can control the startup of power up high speed crystal oscillator, avoids the waste of power consumption.
Another object of the present invention is to provide a kind of method reducing power up power consumption, and the method is avoided shifting to an earlier date the partial parameters such as read waiting time, raises the efficiency.
For achieving the above object, technical scheme of the present invention is as follows.
Reduce a method for power up power consumption, the method comprises the steps:
1), after hardware reset completes, give tacit consent to the clock of inner low-speed clock as latency counter in reseting procedure;
2), when latency counter count down to the regular hour, open inner high speed crystal oscillator, the fetch program district stand-by period parameter;
3), after parameter reads, inner high speed crystal oscillator is closed;
4), continue to use inner low-speed clock to carry out stand-by period counting, the stand-by period is complete, completes digital circuit and resets, enter normal operating conditions.
The present invention is based on the scheme that low-speed clock carries out stand-by period counting, controls the unlatching of high speed crystal oscillator and fetch program district's stored parameter, effectively can control the operating time of high speed crystal oscillator, finally reach the object reducing reseting procedure power consumption.
Described step 2) in, the stand-by period parameter being stored in program area is read by high-frequency clock, and other parameters.
Further, described stand-by period parameter is fixed options, and such as: 0 represents 1ms, 1 represents 10ms, and 2 represent 50ms, and 3 represent 100ms ....; Other parameter described includes crystal oscillator calibration value.
Because power consumption is directly proportional to clock frequency.Compared with all using high-frequency clock (tens more than MHz) with whole electrification reset process, electrification reset process uses low-speed clock (tens KHz) significantly to reduce.Therefore, the present invention not only reduces reseting procedure because of the long-time power consumption penalty of opening high speed crystal oscillator and bringing, and decreases the in running order power consumption in program storage area.
Accompanying drawing explanation
Fig. 1 is the circuit structure diagram that the present invention implements.
Fig. 2 is the reseting procedure principle schematic that the present invention implements.
Fig. 3 is the control flow chart that the present invention implements.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Please refer to shown in Fig. 1, Fig. 2,
1) after powering to single-chip microcomputer, voltage reaches operating voltage, then hardware reset completes, and reset circuit has put hardware reset settling signal.And open inner low-speed clock (low_clk_en is effective).
2) use inner low-speed clock to carry out latency counter counting, now, latency counter only accepts the signal of inner low-speed clock module.
3) latency counter counting reaches 300us, and open high-frequency clock module, high-frequency clock start signal high_clk_en is effective.
4) after high-frequency clock is stable, by high-frequency clock (high_clk) to program area read module.
5) program area read module reads the stand-by period parameter and other parameters that are stored in program area by high-frequency clock.Stand-by period is fixed options, and such as: 0 represents 1ms, 1 represents 10ms, and 2 represent 50ms, and 3 represent 100ms ....; Read crystal oscillator calibration value.
6) the stand-by period parameter read uses to latency counter by program area read module.
7) parameter has read, closing high-speed clock (high_clk_en is invalid).
8) latency counter continues to utilize low-speed clock to count down to the read stand-by period.
9) digital circuit has resetted, and enters normal operating conditions.
And the structure implemented of the present invention simple, be easy to realize, can significantly reduce shunt running and control cost, save chip cost.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (3)
1. reduce a method for power up power consumption, the method comprises the steps:
1), after hardware reset completes, give tacit consent to the clock of inner low-speed clock as latency counter in reseting procedure;
2), when latency counter count down to the regular hour, open inner high speed crystal oscillator, the fetch program district stand-by period parameter;
3), after parameter reads, inner high speed crystal oscillator is closed;
4), continue to use inner low-speed clock to carry out stand-by period counting, the stand-by period is complete, completes digital circuit and resets, enter normal operating conditions.
2. the method reducing power up power consumption as claimed in claim 1, is characterized in that described step 2) in, the stand-by period parameter being stored in program area is read by high-frequency clock.
3. the method reducing power up power consumption as claimed in claim 2, it is characterized in that described stand-by period parameter is fixed options, also include other parameter, other parameter described includes crystal oscillator calibration value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510685354.9A CN105322918A (en) | 2015-10-21 | 2015-10-21 | Method for reducing power consumption of power-on process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510685354.9A CN105322918A (en) | 2015-10-21 | 2015-10-21 | Method for reducing power consumption of power-on process |
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| Publication Number | Publication Date |
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| CN105322918A true CN105322918A (en) | 2016-02-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201510685354.9A Pending CN105322918A (en) | 2015-10-21 | 2015-10-21 | Method for reducing power consumption of power-on process |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050151596A1 (en) * | 2004-01-09 | 2005-07-14 | Sunplus Technology Co., Ltd. | Fast wake-up crystal oscillating circuit |
| CN101022272A (en) * | 2006-03-26 | 2007-08-22 | 珠海炬力集成电路设计有限公司 | Power on reset circuit |
| CN102111135A (en) * | 2009-12-24 | 2011-06-29 | 上海华虹Nec电子有限公司 | Power-on reset circuit |
| CN103324268A (en) * | 2013-05-29 | 2013-09-25 | 东南大学 | Low-power design method for wireless sensor network core chip |
| CN204070724U (en) * | 2014-07-07 | 2015-01-07 | 宁夏力远计算机科技有限公司 | A kind of construction safety helmet based on GPS |
-
2015
- 2015-10-21 CN CN201510685354.9A patent/CN105322918A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050151596A1 (en) * | 2004-01-09 | 2005-07-14 | Sunplus Technology Co., Ltd. | Fast wake-up crystal oscillating circuit |
| CN101022272A (en) * | 2006-03-26 | 2007-08-22 | 珠海炬力集成电路设计有限公司 | Power on reset circuit |
| CN102111135A (en) * | 2009-12-24 | 2011-06-29 | 上海华虹Nec电子有限公司 | Power-on reset circuit |
| CN103324268A (en) * | 2013-05-29 | 2013-09-25 | 东南大学 | Low-power design method for wireless sensor network core chip |
| CN204070724U (en) * | 2014-07-07 | 2015-01-07 | 宁夏力远计算机科技有限公司 | A kind of construction safety helmet based on GPS |
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Application publication date: 20160210 |