CN105306026B - A kind of double pulse generator of turnable pulse width - Google Patents
A kind of double pulse generator of turnable pulse width Download PDFInfo
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- CN105306026B CN105306026B CN201510745579.9A CN201510745579A CN105306026B CN 105306026 B CN105306026 B CN 105306026B CN 201510745579 A CN201510745579 A CN 201510745579A CN 105306026 B CN105306026 B CN 105306026B
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Abstract
A kind of double pulse generator of turnable pulse width, it is characterised in that described double pulse generator includes pulse and circuit, delay circuit and dipulse generation circuit occurs;The single pulse signal of circuit generation periodically or non-periodically occurs for pulse;Single pulse signal is input to delay circuit, produces 4 road single pulse signals;4 road single pulse signals are input to dipulse and circuit occur, and produce dipulse signal;Described pulse occurs circuit and includes aperiodicity pulse generating circuit and recurrent pulses generation circuit, and the output port and recurrent pulses of aperiodicity pulse generating circuit occur the output port parallel connection of circuit, switched by a way switch;Also exportable single pulse signal, single pulse signal and dipulse signal are switched described double pulse generator by another way switch.
Description
Technical field
The present invention relates to a kind of double pulse generator.
Background technology
When the design and debugging of Power Electronic Circuit, first have to enter power electronic devices (IGBT, MOSFET, JFET etc.)
Row type selecting.The Main Basiss of type selecting are the databooks that manufacturer provides, but these data are to be based on some specific test circuits
Get, have very big difference with practical application circuit.Therefore, exist before the use, it is necessary to test to obtain device by dipulse
All kinds of indexs in physical circuit, to assess the overall performance of major loop and drive circuit.
The premise for carrying out dipulse test is to obtain the dipulse signal of adjustable pulse width.In order to reach test purpose and not
Damage device, dipulse signal has following features, and first pulse is larger (10~50us), second pulse compared with
Small (3~8us), the pulsewidth of interval between two pulses and second pulse is close to (3~10us).In order to control opening process
The size of middle main circuit current, the pulsewidth of two pulses and interval be able to will continuously be adjusted.
At present, the mode for obtaining dipulse signal mainly has two kinds:One kind is obtained using signal generator;Another kind is
Obtained using Programming of programmable controller such as DSP.
Signal generator can with the higher dipulse signal of output accuracy, such as, Agilent-33522, Wonder Wave
Dipulse signal can be produced Deng AWG;MFS-2A, BS1520A etc. are then that special dipulse signal occurs
Device.But using signal generator the shortcomings that be mainly to obtain meeting above-mentioned requirements dipulse signal needs it is complex
Set, many signal generators can not even be realized;The most volume of signal generator is larger, and wants Alternating Current Power Supply, using very
It is inconvenient;Signal generator is expensive, limits it and promotes the use of.
The higher dipulse signal of precision can also be obtained using programmable controller, which can utilize electric power nearby
Controller on electronic circuit, without external circuitses.But its major defect be need by be programmed to pulse-pair output and
Pulse-width regulated, technical sophistication are unfavorable for promoting;It is extremely inconvenient and adjusting pulsewidth must change code and programming again every time;I.e.
Make easily carry out pulse-width regulated by modes such as external knobs, can not also realize it is continuous, smoothly adjust.
The content of the invention
The shortcomings that it is an object of the invention to overcome prior art, propose a kind of double-pulse signal generator.Nothing of the present invention
Need to program, the pulsewidth of output signal can be conveniently adjusted;By simply switching switching, it is possible to achieve dipulse signal and list
The switching of pulse signal, and the switching of cyclical signal and non-periodic signals.The present invention only needs modification electric capacity, resistance etc. passive
The value of device, just rewritable pulsewidth, the scope of frequency, principle is simple, and scalability is strong;Cost is cheap, reliable operation.
To reach above-mentioned purpose, the present invention uses following technical scheme:
Main circuit of the present invention includes three parts altogether:Pulse occurs circuit, delay circuit and dipulse and circuit occurs.Three
The order that partial circuit flows through according to signal is sequentially connected in series, i.e., the simple venation of circuit generation periodically or non-periodically occurs for pulse
Rush signal;Single pulse signal is input to delay circuit, produces 4 road single pulse signals;4 road single pulse signals are input to dipulse hair
Raw circuit, produces dipulse signal.
Described pulse occurs circuit and includes aperiodicity pulse generating circuit and recurrent pulses generation circuit.Non- week
The output port that circuit occurs for the output port and recurrent pulses of phase property pulse generating circuit is in parallel, is cut using first switch
Change, described first switch is also that the switching of double pulse generator output aperiodicity pulse signal and cyclic pulse signal is opened
Close.Aperiodicity pulse generating circuit is made up of reseting switch circuit and monostable flipflop;Recurrent pulses occur circuit by
RC circuits and Schmidt trigger are formed.Under recurrent pulses output condition, the value for adjusting potentiometer can be with realization to frequency
The regulation of rate and pulsewidth.
The sequencing that described delay circuit flows through according to signal is divided into negative circuit, delay circuit one, delay circuit
Two and delay circuit three, negative circuit, delay circuit one, delay circuit two and delay circuit three be sequentially connected in series.Negative circuit is by 1
Road Schmidt trigger is formed.Delay circuit one, delay circuit two are identical with the structure of delay circuit three, prolong including 1 RC
When circuit and No. 2 Schmidt triggers.Potentiometer, 2 resistance and electric capacity are followed in series to form RC delay circuits, the time of delay
It can be adjusted by potentiometer;The input connection input signal of No. 1st Schmidt trigger, the 1st tunnel schmidt trigger
The output end series-opposing diode of device, is connected to the tie point of resistance and potentiometer in RC delay circuits, controls filling for electric capacity
Electric discharge;The input of No. 2nd Schmidt trigger is directly connected to the tie point of resistance and potentiometer, that is, the sun of diode
Pole, with the discharge and recharge of electric capacity, export the signal of varying level.The signal conversion process of delay circuit is as follows, first by anti-
The single pulse signal that circuitry phase pulse occurs circuit evolving is anti-phase;The 1st tunnel Schmidt passed through again in delay circuit one touches
Hair device obtains signal A, and No. 2nd Schmidt trigger obtains signal B;Signal B is input to delay circuit two, by the 1st Lu Shimi
Special trigger obtains signal B1, No. 2nd Schmidt trigger obtains signal B2;Signal B2Input time delay circuit three, by the 1st tunnel
Schmidt trigger obtains signal C, and No. 2nd Schmidt trigger obtains signal D.
Described dipulse occurs the sequencing that circuit flows through according to signal and is divided into and not circuit and filter circuit;
And not circuit and filter circuit are sequentially connected in series.And not circuit is made up of 3 tunnel NAND gates and second switch.Second switch
For single-pole double-throw switch (SPDT).Signal A, B are passed through the 2nd tunnel NAND gate and produce signal E, and signal C, D are passed through the 3rd tunnel NAND gate and produce signal
F;Two inputs of second switch connect the output end of the 2nd tunnel NAND gate and the output end of power module respectively, and second is opened
The output end for being connected to the 2nd tunnel NAND gate is closed, then signal E and signal F is passed through the 1st tunnel NAND gate and produces dipulse signal G;By second
Switch is connected to the output end of power module, then high level signal VH and signal F is passed through the 1st tunnel NAND gate and produces single pulse signal
G1;Signal G or signal G1The filter circuit that the Schmidt trigger connected by 2 roads is formed obtains final dipulse signal H
Or single pulse signal H1。
Brief description of the drawings
Fig. 1 is the circuit structure block diagram of the present invention;
Fig. 2 is the schematic diagram of aperiodicity pulse generating circuit in the present invention;
Fig. 3 is the schematic diagram that circuit occurs for recurrent pulses in the present invention;
Fig. 4 a, Fig. 4 b and Fig. 4 c are delay circuit one, delay circuit two, the schematic diagram of delay circuit three respectively;
The schematic diagram of Fig. 5 right and wrongs logic circuit and filter circuit;
Fig. 6 a, Fig. 6 b are the signal sketch during present invention generation dipulse signal and single pulse signal respectively.
Embodiment
The present invention is further illustrated with reference to the accompanying drawings and detailed description.
Fig. 1 show the circuit structure block diagram of the present invention, and it occurs circuit, delay circuit, dipulse by pulse and occurred
Circuit is formed;Specifically include power supply, aperiodicity pulse generating circuit, recurrent pulses and circuit, negative circuit, delay electricity occurs
Lu Yi, delay circuit two, delay circuit three, and not circuit and filter circuit and switching switch S1。
Power input is 12VDC, by power module IC15VDC is obtained, is powered for each several part circuit.Following narration is used
VCC5VDC is represented, high level signal refers to 5V, and low level signal refers to 0V.
Described pulse occurs circuit and includes aperiodicity pulse generating circuit and recurrent pulses generation circuit.Fig. 2
The schematic diagram of aperiodicity pulse generating circuit is shown, it is made up of monostable flipflop and reseting switch circuit.Monostable
In trigger, timer IC28 pin meet power supply VCC, 4 pin connect high level, and 6 pin pass through the second electric capacity C2Ground connection, and pass through first
Potentiometer R2Meet power supply VCC, 5 pin pass through the 3rd electric capacity C3Ground connection, 7 pin are hanging, and 2 pin meet the first Schmidt trigger U1Output end
As the input of trigger signal, 3 pin are output pin;In reseting switch circuit, reset switch S and the first electric capacity C1Parallel connection,
Reset switch S one end connection VCC, reset switch S other end concatenation first resistor R1Ground connection, and it is connected to the first Schmidt
Trigger U1Input.As pressing reset switch a S, the first Schmidt trigger U1Will produce one it is low level touch
Pulse is sent out, makes timer IC23 pin export a high level pulse signal, here it is the mechanism of aperiodicity pulses generation.
Adjust the first potentiometer R2Size can adjust output pulse pulsewidth.
Fig. 3 show the schematic diagram that circuit occurs for recurrent pulses, 3rd resistor R3, the second potentiometer R4With the 4th electric capacity
C4RC delay circuits in series.Second Schmidt trigger U2Input connect the 4th electric capacity C4, the second Schmidt trigger
U2Output end connection 3rd resistor R3.Assuming that the second Schmidt trigger U2Original state be that input is low level, output
Hold as high level, then the 4th electric capacity C4Charging, the second Schmidt trigger U2Input level improve constantly, until reaching high
Level threshold, the second Schmidt trigger U2Output end be reversed to low level;After level reversion, the 4th electric capacity C4Start to discharge,
Until input terminal voltage reaches low level threshold value, output end inverts back high level again.So the circuit is after the power-up, can not
Periodically pulsing signal is given birth in stopping pregnancy, and here it is mechanism caused by recurrent pulses.Due to the 4th electric capacity C4The discharge and recharge time
Constant is all (R3+R4)·C4, so the second potentiometer R of regulation4Pulse width and pulse period can be adjusted.
First switch S1For single-pole double-throw switch (SPDT), first switch S1Two input one end connection timer IC23 pin, separately
One end connects the second Schmidt trigger U2Output end, it is possible to achieve the switching of cyclical signal and non-periodic signals.
The sequencing that described delay circuit flows through according to signal is divided into negative circuit, delay circuit one, delay circuit
Two and delay circuit three.Negative circuit, delay circuit one, delay circuit two and delay circuit three are sequentially connected in series.
Negative circuit is by No. 1 Schmidt trigger U3Form;3rd Schmidt trigger U3Input connecting valve S1's
Output end, input signal can be filtered and anti-phase.
It is respectively delay circuit one, delay circuit two, the schematic diagram of delay circuit three shown in Fig. 4 a, Fig. 4 b and Fig. 4 c.Prolong
When circuit one in, the 4th Schmidt trigger U4Input connection negative circuit in the 3rd Schmidt trigger U3Output end,
4th Schmidt trigger U4Output end connect the first diode D1Negative electrode;3rd potentiometer R7, the 5th resistance R5With the 6th
Resistance R6, the 5th electric capacity C5It is followed in series to form RC delay circuits;First diode D1Anode and the 5th Schmidt trigger U5
Input be connected, and be connected to the 5th resistance R5With the 6th resistance R6Tie point on.P11For the 4th Schmidt trigger U4's
Input signal, P12For the 4th Schmidt trigger U4Output signal, P13For the 5th Schmidt trigger U5Output signal.It is false
If circuit is in stable state, P11For high level, P12For low level, P13For high level;If P11Saltus step is low level, P12Almost at once
Saltus step is high level, the 5th electric capacity C5Start to charge up, until the 5th Schmidt trigger U5Input terminal voltage reach high level threshold
Value, P13Ability saltus step is low level;Thus, by adjusting the 5th electric capacity C5Charge constant, that is, the 3rd potentiometer R7's
Value can be to control time delay.Delay circuit two and delay circuit three are identical with the internal structure of delay circuit one, and
Respectively by the 4th potentiometer R10With the 5th potentiometer R13Control time delay.Delay circuit one, delay circuit two and delay circuit
Three are sequentially connected in series, i.e. the 5th Schmidt trigger U5Output end connect the 6th Schmidt trigger U6Input, the 7th apply it is close
Special trigger U7Output end connect the 8th Schmidt trigger U8Input.
Described dipulse occurs the sequencing that circuit flows through according to signal and is divided into and not circuit and filter circuit;
And not circuit and filter circuit are sequentially connected in series.Circuit, which occurs, for described dipulse can export single pulse signal, pulse
Signal and dipulse signal pass through second switch S2Switching.
Fig. 5 show the schematic diagram of and not circuit and filter circuit, and and not circuit is by three tunnel NAND gate U12、
U13、U14With second switch S2Form, second switch S2Two inputs connect the second NAND gate U respectively13Output end and electricity
Source module IC1Output end, realize the switching of single pulse signal and dipulse signal;First NAND gate U12Two inputs point
Lian Jie not the 3rd NAND gate U14Output end and second switch S2Output end;Second NAND gate U13Two inputs connect respectively
Meet the 4th Schmidt trigger U in delay circuit one4Output end and the 5th Schmidt trigger U5Output end;3rd with
NOT gate U14Two inputs connect the 8th Schmidt trigger U in delay circuit three respectively8Output end and the 9th apply it is close
Special trigger U9Output end;So signal A, B, C, D are respectively to induction signal P12、P13、P32、P33, VH refers to high level signal.The
One NAND gate U12Output end connect the tenth Schmidt trigger U10Input, the tenth Schmidt trigger U10Output end
Connect the 11st Schmidt trigger U11Input, the 11st Schmidt trigger U11Output end output dipulse signal;
Tenth Schmidt trigger U10With the 11st Schmidt trigger U11Filter circuit in series.
Fig. 6 a, Fig. 6 b show the signal sketch in the course of work of the present invention, and aperiodicity pulse is only analyzed in figure
Situation, the simply repetition of this sketch in the case of recurrent pulses, generation is periodic dipulse signal or periodically
Single pulse signal.
If first switch S1It is connected to aperiodicity pulse generating circuit.Individual pulse signal is input to by negative circuit
Delay circuit one, i.e. signal P11;By the 4th Schmidt trigger U4Produce signal P12, i.e. signal A in Fig. 5;Again by the
Five Schmidt trigger U5Produce signal P13, i.e. signal B in Fig. 5.Signal B is input to delay circuit two, produces signal P23,
P23With the same phases of signal B, simply lagged on the time.P23Delay circuit three is input to, by the 8th Schmidt trigger U8Produce letter
Number P32, i.e. signal C in Fig. 5;Pass through the 9th Schmidt trigger U again9Produce signal P33, i.e. signal D in Fig. 5.Signal A and non-letter
Number B, produce signal E;Signal C and non-signal D, produce signal F;Second switch S2It is connected to the second NAND gate U13Output end, letter
Number E and non-signal F, produce dipulse signal;Second switch S2It is connected to power module IC1Output end, high level signal VH with it is non-
Signal F, produce single pulse signal.
Shown in Fig. 6 a and Fig. 6 b, the pulsewidth of the first pulse of dipulse signal depends on delays of the B relative to A, i.e., by the 3rd
Potentiometer R7It is adjusted;Interval between dipulse signal pulse depends on P23Relative to B delay, i.e., by the 4th potentiometer R10
It is adjusted;The pulsewidth of second pulse of dipulse signal, that is, the pulsewidth of single pulse signal, depending on D prolonging relative to C
When, i.e., by the 5th potentiometer R13Regulation.
According to above-mentioned technical proposal, the passive device such as the electric capacity of double pulse generator one embodiment of the present invention, resistance is adopted
With following parameter, the first electric capacity C1For 1nF, the second electric capacity C2For 3.3uF, the 3rd electric capacity C3For 0.01uF, the 4th electric capacity C4For
3.3uF, the 5th electric capacity C5For 1nF, the 6th electric capacity C6For 1nF, the 7th electric capacity C7For 560PF;First resistor R1For 1k Ω, the 3rd
Resistance R3For 4.7k Ω, the 5th resistance R5For 5.1k Ω, the 6th resistance R6For 330 Ω, the 8th resistance R8For 5.1k Ω, the 9th electricity
Hinder R9For 330 Ω, the 11st resistance R11For 2k Ω, the 12nd resistance R12For 330 Ω;First potentiometer R2For 0~500k Ω,
Two potentiometer R4For 0~470k Ω, the 3rd potentiometer R7For 0~500k Ω, the 4th potentiometer R10For 0~50k Ω, the 5th current potential
Device R13For 0~50k Ω.Double pulse generator parameter is as follows:
(1) under periodicity output condition, 1~100Hz of frequency is adjustable;
(2) the first pulse of dipulse, 3~238us are adjustable;
(3) second pulse of dipulse, that is, pulse pulsewidth, 1~14us are adjustable;
(4) pulse spacing, 3~25us are adjustable.
The value of resistance, electric capacity and potentiometer can easily change the basic ginseng of dipulse signal in modification delay circuit
Number, to meet different application demands, scalability is very strong.
Claims (7)
1. a kind of double pulse generator of turnable pulse width, it is characterised in that described double pulse generator includes pulse
Circuit occurs for circuit, delay circuit and dipulse;The single pulse signal of circuit generation periodically or non-periodically occurs for pulse;
Single pulse signal is input to delay circuit, produces 4 road single pulse signals;4 road single pulse signals are input to dipulse and circuit occur,
Produce dipulse signal;Described pulse occurs circuit and includes aperiodicity pulse generating circuit and recurrent pulses generation electricity
Road;The output port that circuit occurs for the output port and recurrent pulses of aperiodicity pulse generating circuit is in parallel, passes through first
Switch S1Switching.
2. according to the double pulse generator of the turnable pulse width described in claim 1, it is characterised in that described aperiodicity pulse
Generation circuit is made up of reseting switch circuit and monostable flipflop;In reseting switch circuit, reset switch S and the first electric capacity C1
Parallel connection, reset switch S one end connection VCC, reset switch S other end concatenation first resistor R1Ground connection, and be connected to first and apply
Schmitt trigger U1Input;In monostable flipflop, timer IC28 pin meet power supply VCC, 4 pin connect high level, and 6 pin lead to
Cross the second electric capacity C2Ground connection, and pass through the first potentiometer R2Meet power supply VCC, 5 pin pass through the 3rd electric capacity C3Ground connection, 7 pin are hanging, 2 pin
Meet the first Schmidt trigger U1Input of the output end as trigger signal, 3 pin are output pin.
3. according to the double pulse generator of the turnable pulse width described in claim 1, it is characterised in that described recurrent pulses hair
In raw circuit, 3rd resistor R3, the second potentiometer R4With the 4th electric capacity C4RC delay circuits in series;Second schmidt trigger
Device U2Input connect the 4th electric capacity C4, the second Schmidt trigger U2Output end connection 3rd resistor R3。
4. according to the double pulse generator of the turnable pulse width described in claim 1, it is characterised in that the first switch S1One
Individual input connection timer IC23 pin, another input connects the second Schmidt trigger U2Output end, property performance period
The switching of signal and non-periodic signals.
5. according to the double pulse generator of the turnable pulse width described in claim 1, it is characterised in that described delay circuit according to
The sequencing that signal flows through is divided into negative circuit, delay circuit one, delay circuit two and delay circuit three;Negative circuit, prolong
When circuit one, delay circuit two and delay circuit three be sequentially connected in series;Negative circuit is by the 3rd Schmidt trigger U3Form;3rd
Schmidt trigger U3Input connection first switch S1Output end, by input signal filtering and it is anti-phase;Delay circuit one,
Delay circuit two is identical with the structure of delay circuit three;
In delay circuit one, the 4th Schmidt trigger U4Input connection negative circuit in the 3rd Schmidt trigger U3's
Output end, the 4th Schmidt trigger U4Output end connect the first diode D1Negative electrode;3rd potentiometer R7, the 5th resistance
R5With the 6th resistance R6, the 5th electric capacity C5RC delay circuits are followed in series to form, delay time is by the 3rd potentiometer R7Regulation;The
One diode D1Anode and the 5th Schmidt trigger U5Input be connected, and be connected to the 5th resistance R5With the 6th resistance
R6Tie point on;The structure of delay circuit two and delay circuit three is identical with the structure of delay circuit one, and respectively by the 4th
Potentiometer R10With the 5th potentiometer R13Control time delay;5th Schmidt trigger U5Output end connect the 6th Schmidt touch
Send out device U6Input, the 7th Schmidt trigger U7Output end connect the 8th Schmidt trigger U8Input.
6. according to the double pulse generator of the turnable pulse width described in claim 1, it is characterised in that electricity occurs for described dipulse
The sequencing that road flows through according to signal is divided into and not circuit and filter circuit;And not circuit and filter circuit are successively
Series connection;And not circuit is by three tunnel NAND gate U12、U13、U14With second switch S2Form, second switch S2Two inputs
The second NAND gate U is connected respectively13Output end and power module IC1Output end, realize single pulse signal and dipulse signal
Switching;First NAND gate U12Two inputs connect the 3rd NAND gate U respectively14Output end and second switch S2Output
End;Second NAND gate U13Two inputs connect the 4th Schmidt trigger U in delay circuit one respectively4Output end and
5th Schmidt trigger U5Output end;3rd NAND gate U14Two inputs connect respectively in delay circuit three the 8th
Schmidt trigger U8Output end and the 9th Schmidt trigger U9Output end;First NAND gate U12Output end connection the
Ten Schmidt trigger U10Input, the tenth Schmidt trigger U10Output end connect the 11st Schmidt trigger U11
Input, the 11st Schmidt trigger U11Output end output dipulse signal;Tenth Schmidt trigger U10With the tenth
One Schmidt trigger U11Filter circuit in series.
7. according to the double pulse generator of the turnable pulse width described in claim 1, it is characterised in that electricity occurs for described dipulse
Road can export single pulse signal, and single pulse signal and dipulse signal pass through second switch S2Switching.
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CN105958979B (en) * | 2016-06-15 | 2018-11-30 | 湖南工业大学 | Locomotive traction motor tach signal detection device |
US9991777B2 (en) * | 2016-07-20 | 2018-06-05 | Texas Instruments Incorporated | Method and circuitry for generating pulse width modulated signals |
CN110311658A (en) * | 2018-03-20 | 2019-10-08 | 山东朗进科技股份有限公司 | A kind of pulse generating circuit |
CN108847831B (en) * | 2018-05-29 | 2020-08-25 | 昆明理工大学 | High-performance pulse signal processing circuit and implementation method thereof |
CN109274357B (en) * | 2018-09-21 | 2023-07-18 | 昆明理工大学 | Pulse modulation circuit with duty ratio unchanged with frequency and modulation method thereof |
CN110601680A (en) * | 2019-08-22 | 2019-12-20 | 宜宾市叙芯半导体有限公司 | Edge switching circuit and switching method of integrated magnetic isolation chip |
CN111654267B (en) * | 2020-05-28 | 2024-02-13 | 广东浪潮大数据研究有限公司 | Adjustable pulse generator |
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US8466725B2 (en) * | 2008-08-13 | 2013-06-18 | Pierre F. Thibault | Method and device for generating short pulses |
CN203911746U (en) * | 2014-05-22 | 2014-10-29 | 美的集团股份有限公司 | IGBT tube driving circuit of intelligent power module and intelligent power module |
CN104539141A (en) * | 2014-12-08 | 2015-04-22 | 深圳市科陆电子科技股份有限公司 | Switching power supply double-pulse pulse width constraint circuit and implement method thereof |
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US8466725B2 (en) * | 2008-08-13 | 2013-06-18 | Pierre F. Thibault | Method and device for generating short pulses |
CN203911746U (en) * | 2014-05-22 | 2014-10-29 | 美的集团股份有限公司 | IGBT tube driving circuit of intelligent power module and intelligent power module |
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