CN105304642B - A kind of array substrate and its manufacturing method - Google Patents
A kind of array substrate and its manufacturing method Download PDFInfo
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- CN105304642B CN105304642B CN201510617622.3A CN201510617622A CN105304642B CN 105304642 B CN105304642 B CN 105304642B CN 201510617622 A CN201510617622 A CN 201510617622A CN 105304642 B CN105304642 B CN 105304642B
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Abstract
The present invention provides a kind of array substrate and its manufacturing method, array substrate is equipped with viewing area and the frame glue area positioned at periphery, water-blocking groove is equipped between the viewing area and frame glue area of array substrate, the lower section of the water-blocking groove has etch stop layer, the etch stop layer is made of semiconductor layer material or made of metal, and ito thin film is covered on water-blocking groove.The present invention causes metal routing short-circuit by the etching barrier layer of setting water-blocking groove to prevent ITO from remaining on metal routing.
Description
Technical field
The present invention relates to liquid crystal display manufactures, especially array substrate and its manufacturing method.
Background technique
Liquid crystal display has the characteristics that frivolous, power saving, large scale, has been accepted by the public, and liquid crystal display substitutes CRT
Display, liquid crystal display are known as mainstream display technology.With the continuous development of LCD technology, narrow frame is known as liquid crystal display
Trend of the curtain as liquid crystal display.
It is as shown in Figure 1 the structural schematic diagram of liquid crystal display panel, liquid crystal display panel includes the array base being oppositely arranged
Plate 1 and color membrane substrates 2, array substrate 1 and color membrane substrates 2 in neighboring area by frame glue 3 by being bonded, in array substrate
1 and the opposite alignment film (PI) 4 that is equipped with of color membrane substrates 2, wherein the display area of liquid crystal display panel is known as the area AA, peripheral region
Domain is known as non-display area BB (rim area), and the frame size of liquid crystal display panel refers to viewing area apart from LCD display edges of boards
The distance of edge 5.
Referring to Fig.2, non-display area BB (rim area) size mainly includes viewing area and wiring film (PI) boundary distance a,
Alignment film (PI) close to frame 2 boundary and frame glue 2 close to the distance between boundary alignment film (PI) b, the width c of frame glue 3, with
And frame glue 3 is close to the distance d at boundary to the liquid crystal display panel edge 5 at liquid crystal display panel edge 5.
In order to reduce frame size, a kind of way is the distance b for reducing alignment film and frame glue at present.Reduce alignment film with
The premise of the distance of frame glue is that alignment film cannot be contacted with frame glue, the reason is that the material that alignment film is insulating properties will lead in frame glue
Gold goal can not be in electrical contact with the ITO in array substrate, in addition can also reduce the adherence of frame glue and array substrate.
There are mainly two types of the modes of the more mature wide coating orientation coating solution of application at present, and one is use alignment films
The mode that galley is transferred；Another kind is ink jet type mode of printing, and ink jet type mode of printing does not need production galley, if
Cost is greatly saved in standby simple structure, but the safe distance that ink jet type mode of printing needs is larger.Generally pass through at present
Waterwall is made on color membrane substrates, water-blocking groove is made in array substrate, controls PI precision.
As shown in figure 3, making water-blocking groove 11 or waterwall in array substrate 1, being made in the corresponding position of color membrane substrates 2
Waterwall 21 or water-blocking groove, water-blocking groove or waterwall can prevent the spilling of alignment liquid 4, but the waterwall or water-blocking groove made
But the size for further increasing rim area, is unfavorable for further narrow frame.
In 5 photoetching processes of back channel etching (BCE), water-blocking groove 11 is made in array substrate 1, is generally used
4th photoetching process, that is, contact hole technique.Contact hole technique is usually to use dry etching, always dry etching to array first layer
Metal 14 stops.Since 11 segment difference of water-blocking groove is larger, in the 5th photoetching process of array, the light inside water-blocking groove 11 will lead to
Photoresist is thicker relative to the photoresist in outside, therefore will appear the photoresist exposure inside water-blocking groove in photoresist exposure process
It is insufficient, cause ITO inside water-blocking groove that ITO residual 12 occurs, as shown in figure 4,13 being gold goal in Fig. 4,14 be the first metal
Layer, 15 be terminal ITO.
As shown in figure 5, these regions are generally metal routing since water-blocking groove 11 is between viewing area and sealant
16 position will lead to adjacent metal wire 16 and short circuit 18 occur, cause not connecting with terminal 17 when ITO 12 is remained
It connects.And when the panel for using organic insulator, generation ITO residual is easier when making water-blocking groove causes metal routing short-circuit.
Summary of the invention
It is an object of the invention to the etch stop layers by setting water-blocking groove, prevent ITO from remaining on metal routing and lead
Cause the array substrate and its manufacturing method of metal routing short circuit.
The present invention provides a kind of array substrate, and array substrate is equipped with viewing area and the frame glue area positioned at periphery, in array base
Water-blocking groove is equipped between the viewing area and frame glue area of plate, the lower section of the water-blocking groove has etch stop layer.
Wherein, the etch stop layer is made of semiconductor layer material.
Wherein, the etch stop layer is made of metal.
Wherein, the etch stop layer is made of the metal material formed data line.
Wherein, ito thin film is covered on water-blocking groove.
Wherein, the array substrate is the array substrate of narrow frame.
The present invention provides a kind of manufacturing method of array substrate again, includes the following steps:
It include scan line, the by first layer metal figure step 1: forming first layer metal figure on the glass substrate
One metal routing, surrounding terminals；
Step 2: depositing gate insulation layer in the array substrate for forming above-mentioned first step pattern；
Step 3: the deposited semiconductor layer in the array substrate for forming above-mentioned second step pattern, is formed by photoetching process
Channel layer and etching barrier layer positioned at periphery；
Step 4: depositing second layer metal film in the array substrate for forming above-mentioned third step figure, passing through photoetching work
Skill forms second layer metal figure, and the second metallic pattern includes data line and source-drain electrode；
5th step, in the array substrate for forming above-mentioned 4th step figure, deposit passivation layer；
6th step, in the array substrate for forming above-mentioned 5th step figure, coating photoresist is formed by photoetching process
Contact hole and the recess portion on etch stop layer, the recess portion are waterwall；
7th step deposits ito thin film in the array substrate for forming above-mentioned 6th step figure, by photoetching process, is formed
Pixel electrode, terminal electrode.
The present invention provides a kind of manufacturing method of array substrate again, includes the following steps:
It include scan line, the by first layer metal figure step 1: forming first layer metal figure on the glass substrate
One metal routing, surrounding terminals；
Step 2: depositing gate insulation layer in the array substrate for forming above-mentioned first step pattern；
Step 3: the deposited semiconductor layer in the array substrate for forming above-mentioned second step pattern, is formed by photoetching process
Channel layer；
Step 4: depositing second layer metal film in the array substrate for forming above-mentioned third step figure, passing through photoetching work
Skill forms second layer metal figure, and the second metallic pattern includes data line, source-drain electrode and etch stop layer；
5th step, in the array substrate for forming above-mentioned 4th step figure, deposit passivation layer；
6th step, in the array substrate for forming above-mentioned 5th step figure, coating photoresist is formed by photoetching process
Contact hole and the recess portion on etch stop layer, the recess portion are waterwall；
7th step deposits ito thin film in the array substrate for forming above-mentioned 6th step figure, by photoetching process, is formed
Pixel electrode, terminal electrode.
Wherein, the 7th step, is again covered with ito thin film on the water-blocking groove.
Wherein, the water-blocking groove is located in the first metal routing region.
The present invention causes metal to be walked by the etching barrier layer of setting water-blocking groove to prevent ITO from remaining on metal routing
Line short circuit.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of available liquid crystal display panel；
Fig. 2 is the rim area component part schematic diagram of the liquid crystal display panel of Fig. 1；
Fig. 3 is the panel schematic diagram using waterwall and water-blocking groove of Fig. 1；
Fig. 4 is that production waterwall causes ITO to remain schematic diagram in existing back channel etching backboard process；
Fig. 5 is the schematic diagram that the residual of water-blocking groove ITO shown in Fig. 4 leads to metal routing short circuit；
Fig. 6 is the schematic diagram of array substrate water blocking groove location of the present invention；
Fig. 7 is the schematic diagram of array substrate water blocking groove location first embodiment of the present invention；
Fig. 8 is sectional view of the Fig. 7 in the direction C-C '；
Fig. 9 is the schematic diagram of array substrate water blocking groove location second embodiment of the present invention；
Figure 10 is sectional view of the Fig. 9 in the direction C-C '；
Specific embodiment
In the following with reference to the drawings and specific embodiments, the present invention is furture elucidated, it should be understood that these embodiments are merely to illustrate
It the present invention rather than limits the scope of the invention, after the present invention has been read, those skilled in the art are to of the invention each
The modification of kind equivalent form falls within the application range as defined in the appended claims.
Fig. 6 show the structural schematic diagram of narrow frame array substrate, and array substrate is equipped with viewing area AA and positioned at periphery
Frame glue area BB, is equipped with water-blocking groove 50 between the viewing area AA and frame glue area BB of array substrate, and the lower section of water-blocking groove 50 has erosion
Carve barrier layer.
The etch stop layer of 50 lower section of water-blocking groove is kept off made of semiconductor material or made of metal material material
Sink 50 covers ito thin film.
The schematic diagram of first embodiment for a kind of narrow frame of the present invention in array substrate as shown in Figure 7 and Figure 8, this
In one embodiment, the etch stop layer of 50 lower section of water-blocking groove is semiconductor material.
Array substrate is equipped with the criss-cross scan line 10 and data line 20, gate insulator being located on glass substrate 100
Layer 80, semiconductor layer 90, alignment film 60, with the etching barrier layer 91 made of semiconductor layer material, frame glue 30 and be located at frame
The terminal 40 in 30 outside of glue, and recess portion 50 is set in array substrate, i.e. water-blocking groove 50, water-blocking groove 50 is located in frame glue 30
Side is located on the outside of the A-A of viewing area, it may be assumed that water-blocking groove 50 is located between viewing area AA and frame glue area BB.
Etch stop layer 91 is set to 50 lower section of waterwall, and waterwall 50 can prevent the ITO in watertight layer manufacturing process
Remain in first layer metal 200 (10 layers of scan line), causes metal routing short-circuit.
Wherein, first layer metal 200 includes scan line 10, metal routing and surrounding terminals 30.
The etch stop layer 91 made of the recess portion following settings semiconductor layer material for forming waterwall 50, work as generation
When ITO is remained, it can only stay on semiconductor layer 90, without remaining to first layer metal 200.
Gate insulation layer 80 is spaced between semiconductor layer 90 and first layer metal 200, etching barrier layer and semiconductor layer 90 are same
When formed, and the material of etch stop layer and semiconductor layer 90 that material is made is identical.
A kind of manufacturing method of narrow frame array substrate of the present invention, including the following steps:
The first step, on the glass substrate deposited metal film, coating photoresist form the by first time photoetching process
One layer of 200 figure of metal, 200 figure of first layer metal include scan line 10, the first metal routing, surrounding terminals 40.
Second step deposits gate insulation layer 80 in the array substrate for forming above-mentioned first step pattern.
Third step, the deposited semiconductor layer 90 in the array substrate for forming above-mentioned second step pattern, passes through second of photoetching
Technique forms channel layer, and the etching barrier layer 91 positioned at periphery.
4th step, in the array substrate for forming above-mentioned third step figure, deposited metal film passes through third time photoetching work
Skill forms second layer metal figure, including data line 20, source-drain electrode.
5th step, in the array substrate for forming above-mentioned 4th step figure, deposit passivation layer 70.
6th step, in the array substrate for forming above-mentioned 5th step figure, coating photoresist passes through fourth lithography work
Skill forms termination contact hole 110, first layer metal and second layer metal contact hole, termination contact hole and metal routing region
Recess portion 50, which is waterwall 50, which is located at the upper surface of the etch stop layer 91 that is formed by semiconductor layer 90.
7th step deposits ito thin film, passes through the 5th photoetching work in the array substrate for forming above-mentioned 6th step figure
Skill forms pixel electrode 120, terminal electrode and first layer metal and second layer metal articulamentum, and also covers in waterwall 50
Ito thin film is covered.
The present invention is used as water-blocking groove Etch Passivation 90 by semiconductor layer 90, to prevent ITO from remaining on metal routing
Cause metal routing short-circuit.
The schematic diagram of second embodiment for a kind of narrow frame of the present invention in array substrate as shown in Figure 9 and Figure 10 is identical
Appended drawing reference indicate identical components.
In a second embodiment, etching barrier layer is made of second metal layer 300, and waterwall 50 is arranged in second metal layer
300 top.
It, can also be in 300 disposed thereon ito thin film of second metal layer, using the suspension of large area in order to avoid metal exposure
Metal is likely to form accumulation of static electricity, and designs corresponding discharge loop.
The manufacturing method of second embodiment, including the following steps:
The first step, on the glass substrate deposited metal film, coating photoresist form the by first time photoetching process
One layer of 200 figure of metal, 200 figure of first layer metal include scan line 10, the first metal routing, surrounding terminals 40.
Second step deposits gate insulation layer 80 in the array substrate for forming above-mentioned first step pattern.
Third step, the deposited semiconductor layer 90 in the array substrate for forming above-mentioned second step pattern, passes through second of photoetching
Technique forms channel layer.
4th step, in the array substrate for forming above-mentioned third step figure, deposited metal film passes through third time photoetching work
Skill forms second layer metal figure, including data line 20, source-drain electrode and etch stop layer 301.
5th step, in the array substrate for forming above-mentioned 4th step figure, deposit passivation layer 70.
6th step, in the array substrate for forming above-mentioned 5th step figure, coating photoresist passes through fourth lithography work
Skill forms termination contact hole 110, first layer metal and second layer metal contact hole, termination contact hole and metal routing region
Recess portion 50, which is waterwall 50, which is located at the etch stop layer 301 formed by second metal layer 300
Above.
7th step deposits ito thin film, passes through the 5th photoetching work in the array substrate for forming above-mentioned 6th step figure
Skill forms pixel electrode 120, terminal electrode and first layer metal and second layer metal articulamentum, and also covers in waterwall 50
Ito thin film is covered.
The present invention causes metal to be walked by the etching barrier layer of setting water-blocking groove to prevent ITO from remaining on metal routing
Line short circuit.
Claims (10)
1. a kind of array substrate, array substrate is equipped with viewing area and the frame glue area positioned at periphery, array substrate viewing area and
Water-blocking groove is equipped between frame glue area, it is characterised in that: passivation layer is formed in array substrate, water-blocking groove is formed in the passivation layer,
The lower section of the water-blocking groove has etch stop layer, and the etch stop layer is located on gate insulation layer, and the gate insulation layer is located at
On first layer metal.
2. array substrate according to claim 1, it is characterised in that: the etch stop layer is made of semiconductor layer material
's.
3. array substrate according to claim 1, it is characterised in that: the etch stop layer is made of metal.
4. array substrate according to claim 1, it is characterised in that: the etch stop layer is by the metal that forms data line
Made of material.
5. array substrate according to claim 1 to 4, it is characterised in that: cover ito thin film on water-blocking groove.
6. array substrate according to claim 5, it is characterised in that: the array substrate is the array substrate of narrow frame.
7. the manufacturing method of -6 any array substrates according to claim 1, which comprises the steps of:
It include scan line, the first gold medal by first layer metal figure step 1: forming first layer metal figure on the glass substrate
Belong to cabling, surrounding terminals；
Step 2: depositing gate insulation layer in the array substrate for forming above-mentioned figure；
Step 3: the deposited semiconductor layer in the array substrate for forming above-mentioned figure, by photoetching process formed channel layer and
Etching barrier layer positioned at periphery；
Step 4: depositing second layer metal film in the array substrate for forming above-mentioned figure, second is formed by photoetching process
Layer metallic pattern, the second metallic pattern includes data line and source-drain electrode；
5th step, in the array substrate for forming above-mentioned figure, deposit passivation layer；
6th step, in the array substrate for forming above-mentioned figure, coating photoresist, by photoetching process, formed contact hole and
Recess portion on etch stop layer, the recess portion are waterwall；
7th step deposits ito thin film in the array substrate for forming above-mentioned figure, by photoetching process, forms pixel electrode,
Terminal electrode.
8. the manufacturing method of -6 any array substrates according to claim 1, which comprises the steps of:
It include scan line, the first gold medal by first layer metal figure step 1: forming first layer metal figure on the glass substrate
Belong to cabling, surrounding terminals；
Step 2: depositing gate insulation layer in the array substrate for forming above-mentioned figure；
Step 3: the deposited semiconductor layer in the array substrate for forming above-mentioned figure, forms channel layer by photoetching process；
Step 4: depositing second layer metal film in the array substrate for forming above-mentioned figure, second is formed by photoetching process
Layer metallic pattern, the second metallic pattern includes data line, source-drain electrode and etch stop layer；
5th step, in the array substrate for forming above-mentioned figure, deposit passivation layer；
6th step, in the array substrate for forming above-mentioned figure, coating photoresist, by photoetching process, formed contact hole and
Recess portion on etch stop layer, the recess portion are waterwall；
7th step deposits ito thin film in the array substrate for forming above-mentioned figure, by photoetching process, forms pixel electrode,
Terminal electrode.
9. according to the manufacturing method of any array substrate of claim 7-8, which is characterized in that the 7th step, described
Ito thin film is again covered on water-blocking groove.
10. according to the manufacturing method of any array substrate of claim 7-8, which is characterized in that the water-blocking groove is located at the
In one metal routing region.
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| CN201510617622.3A CN105304642B (en) | 2015-09-24 | 2015-09-24 | A kind of array substrate and its manufacturing method |
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| CN105304642B true CN105304642B (en) | 2019-05-17 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109273410A (en) * | 2018-09-12 | 2019-01-25 | 重庆惠科金渝光电科技有限公司 | Display panel processing method and display panel |
| CN209070278U (en) * | 2019-01-02 | 2019-07-05 | 京东方科技集团股份有限公司 | A kind of array substrate |
| CN113809270B (en) * | 2021-10-22 | 2023-09-12 | 昆山国显光电有限公司 | Display panel and preparation method thereof |
| CN114267251A (en) * | 2021-12-16 | 2022-04-01 | Tcl华星光电技术有限公司 | Display device and splicing display device |
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| CN101866583A (en) * | 2010-02-26 | 2010-10-20 | 信利半导体有限公司 | Rear cover and manufacturing method thereof |
| CN102135687A (en) * | 2009-11-03 | 2011-07-27 | 深超光电（深圳）有限公司 | Display panel |
| CN103033992A (en) * | 2012-12-21 | 2013-04-10 | 京东方科技集团股份有限公司 | Liquid crystal display substrate and preparation method thereof and liquid crystal display device |
| CN104216189A (en) * | 2014-09-26 | 2014-12-17 | 南京中电熊猫液晶显示科技有限公司 | Liquid crystal display panel and manufacturing method thereof |
| CN104538555A (en) * | 2014-12-02 | 2015-04-22 | 深圳市华星光电技术有限公司 | OLED packaging structure and OLED packaging method |
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|---|---|---|---|---|
| CN102135687A (en) * | 2009-11-03 | 2011-07-27 | 深超光电（深圳）有限公司 | Display panel |
| CN101866583A (en) * | 2010-02-26 | 2010-10-20 | 信利半导体有限公司 | Rear cover and manufacturing method thereof |
| CN103033992A (en) * | 2012-12-21 | 2013-04-10 | 京东方科技集团股份有限公司 | Liquid crystal display substrate and preparation method thereof and liquid crystal display device |
| CN104216189A (en) * | 2014-09-26 | 2014-12-17 | 南京中电熊猫液晶显示科技有限公司 | Liquid crystal display panel and manufacturing method thereof |
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